Re: [PATCH v3 2/2] net: dsa: mt7530: Use GPIO polarity to generate correct reset sequence

[Krzysztof Kozlowski <krzk@kernel.org>]

On 04/12/2025 18:23, Krzysztof Kozlowski wrote:
> On 04/12/2025 18:11, Vladimir Oltean wrote:
>> On Thu, Dec 04, 2025 at 05:48:07PM +0100, Krzysztof Kozlowski wrote:
>>> Both are the same - inverter or NOT gate, same stuff. It is just
>>> connecting wire to pull up, not actual component on the board (although
>>> one could make and buy such component as well...). We never describe
>>> these inverters in the DTS, these are just too trivial circuits, thus
>>> the final GPIO_ACTIVE_XXX should already include whatever is on the wire
>>> between SoC and device.
>>
>> Please read what Andrew said:
>> https://lore.kernel.org/netdev/3fbc4e67-b931-421c-9d83-2214aaa2f6ed@lunn.ch/
>>
>>   Assuming there is not a NOT gate placed between the GPIO and the reset
>>   pin, because the board designer decided to do that for some reason?
>>                    ~~~~~~~~~~~~~~
>>
>> You two are *not* talking about the same thing. I dismissed the
> 
> 
> It's the same thing. NOT gate is just pulling some pin down or up.

Although transistor would be still needed, so indeed that's still a bit
more than a wire and resistor as I implied.

It looks like:
https://www.electronics-tutorials.ws/wp-content/uploads/2018/05/logic-log47.gif


> 
>> probability of there being a NOT gate in the form of a discrete chip on
> 
> We do not describe NOT gates as discreet chips. I don't think anyone
> actually places something as NOT gate. It's logical NOT gate, but on
> circuit it is just pull up/down as I said multiple times. The pull +
> resistor is the "NOT gate".
> 
> It's so easy and that's why it is potentially so common design.


We still do not describe transistors in DTS. We do not describe NOT
gates. The final flag should include that as I said.


Best regards,
Krzysztof