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Thu, 14 Aug 2025 20:18:25 -0700 (PDT) MIME-Version: 1.0 References: <20250805135447.149231-1-laura.nao@collabora.com> <20250805135447.149231-3-laura.nao@collabora.com> In-Reply-To: <20250805135447.149231-3-laura.nao@collabora.com> From: Chen-Yu Tsai Date: Fri, 15 Aug 2025 12:18:14 +0900 X-Gm-Features: Ac12FXwqbJqR6dXDCHoREy9cuJVuDHi_sxjr2uRku7Hw7ujClZ2WhTJ_l5duokI Message-ID: Subject: Re: [PATCH v4 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC To: Laura Nao Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com, guangjie.song@mediatek.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, =?UTF-8?B?TsOtY29sYXMgRiAuIFIgLiBBIC4gUHJhZG8=?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250814_201827_432333_1825E324 X-CRM114-Status: GOOD ( 24.82 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, Aug 5, 2025 at 10:55=E2=80=AFPM Laura Nao = wrote: > > MT8196 uses a combination of set/clr registers to control the PLL > enable state, along with a FENC bit to check the preparation status. > Add new set of PLL clock operations with support for set/clr enable and > FENC status logic. > > Reviewed-by: N=C3=ADcolas F. R. A. Prado > Reviewed-by: AngeloGioacchino Del Regno > Signed-off-by: Laura Nao > --- > drivers/clk/mediatek/clk-pll.c | 42 +++++++++++++++++++++++++++++++++- > drivers/clk/mediatek/clk-pll.h | 5 ++++ > 2 files changed, 46 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pl= l.c > index 49ca25dd5418..8f46de77f42d 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -37,6 +37,13 @@ int mtk_pll_is_prepared(struct clk_hw *hw) > return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) !=3D 0; > } > > +static int mtk_pll_fenc_is_prepared(struct clk_hw *hw) > +{ > + struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); > + > + return readl(pll->fenc_addr) & pll->fenc_mask; Nits: I'd do a double-negate (!!) just to indicate that we only care about true or false. Also, why do we need to store fenc_mask instead of just shifting the bit here? Same goes for the register address. |pll| has the base address. Why do we need to pre-calculate it? The code is OK; it just seems a bit wasteful on memory. Either way, this is Reviewed-by: Chen-Yu Tsai > +} > + > static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 = fin, > u32 pcw, int postdiv) > { > @@ -274,6 +281,25 @@ void mtk_pll_unprepare(struct clk_hw *hw) > writel(r, pll->pwr_addr); > } > > +static int mtk_pll_prepare_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); > + > + writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); > + > + /* Wait 20us after enable for the PLL to stabilize */ > + udelay(20); > + > + return 0; > +} > + > +static void mtk_pll_unprepare_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_pll *pll =3D to_mtk_clk_pll(hw); > + > + writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr); > +} > + > const struct clk_ops mtk_pll_ops =3D { > .is_prepared =3D mtk_pll_is_prepared, > .prepare =3D mtk_pll_prepare, > @@ -283,6 +309,16 @@ const struct clk_ops mtk_pll_ops =3D { > .set_rate =3D mtk_pll_set_rate, > }; > > +const struct clk_ops mtk_pll_fenc_clr_set_ops =3D { > + .is_prepared =3D mtk_pll_fenc_is_prepared, > + .prepare =3D mtk_pll_prepare_setclr, > + .unprepare =3D mtk_pll_unprepare_setclr, > + .recalc_rate =3D mtk_pll_recalc_rate, > + .round_rate =3D mtk_pll_round_rate, > + .set_rate =3D mtk_pll_set_rate, > +}; > +EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops); > + > struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, > const struct mtk_pll_data *data, > void __iomem *base, > @@ -315,6 +351,9 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_cl= k_pll *pll, > pll->hw.init =3D &init; > pll->data =3D data; > > + pll->fenc_addr =3D base + data->fenc_sta_ofs; > + pll->fenc_mask =3D BIT(data->fenc_sta_bit); > + > init.name =3D data->name; > init.flags =3D (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; > init.ops =3D pll_ops; > @@ -337,12 +376,13 @@ struct clk_hw *mtk_clk_register_pll(const struct mt= k_pll_data *data, > { > struct mtk_clk_pll *pll; > struct clk_hw *hw; > + const struct clk_ops *pll_ops =3D data->ops ? data->ops : &mtk_pl= l_ops; > > pll =3D kzalloc(sizeof(*pll), GFP_KERNEL); > if (!pll) > return ERR_PTR(-ENOMEM); > > - hw =3D mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops); > + hw =3D mtk_clk_register_pll_ops(pll, data, base, pll_ops); > if (IS_ERR(hw)) > kfree(pll); > > diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pl= l.h > index c4d06bb11516..7fdc5267a2b5 100644 > --- a/drivers/clk/mediatek/clk-pll.h > +++ b/drivers/clk/mediatek/clk-pll.h > @@ -29,6 +29,7 @@ struct mtk_pll_data { > u32 reg; > u32 pwr_reg; > u32 en_mask; > + u32 fenc_sta_ofs; > u32 pd_reg; > u32 tuner_reg; > u32 tuner_en_reg; > @@ -51,6 +52,7 @@ struct mtk_pll_data { > u32 en_clr_reg; > u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ > u8 pcw_chg_bit; > + u8 fenc_sta_bit; > }; > > /* > @@ -72,6 +74,8 @@ struct mtk_clk_pll { > void __iomem *en_addr; > void __iomem *en_set_addr; > void __iomem *en_clr_addr; > + void __iomem *fenc_addr; > + u32 fenc_mask; > const struct mtk_pll_data *data; > }; > > @@ -82,6 +86,7 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data = *plls, int num_plls, > struct clk_hw_onecell_data *clk_data); > > extern const struct clk_ops mtk_pll_ops; > +extern const struct clk_ops mtk_pll_fenc_clr_set_ops; > > static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) > { > -- > 2.39.5 >