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Wed, 12 Feb 2025 18:02:08 -0500 (EST) Date: Thu, 13 Feb 2025 00:02:06 +0100 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Roger Pau =?utf-8?B?TW9ubsOp?= , Boris Ostrovsky , Felix Fietkau , Lorenzo Bianconi , Ryder Lee , Jan Beulich , Alex Williamson , Deren Wu , Kai-Heng Feng , Shayne Chen , Sean Wang , Leon Yen , linux-mediatek@lists.infradead.org, regressions@lists.linux.dev, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: Re: [PATCH] PCI: Avoid FLR for Mediatek MT7922 WiFi Message-ID: References: <20250212193516.88741-1-helgaas@kernel.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0tz+zSavbvKwuCEI" Content-Disposition: inline In-Reply-To: <20250212193516.88741-1-helgaas@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250212_150216_509298_F72A828F X-CRM114-Status: GOOD ( 23.36 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org --0tz+zSavbvKwuCEI Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Thu, 13 Feb 2025 00:02:06 +0100 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Roger Pau =?utf-8?B?TW9ubsOp?= , Boris Ostrovsky , Felix Fietkau , Lorenzo Bianconi , Ryder Lee , Jan Beulich , Alex Williamson , Deren Wu , Kai-Heng Feng , Shayne Chen , Sean Wang , Leon Yen , linux-mediatek@lists.infradead.org, regressions@lists.linux.dev, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: Re: [PATCH] PCI: Avoid FLR for Mediatek MT7922 WiFi On Wed, Feb 12, 2025 at 01:35:16PM -0600, Bjorn Helgaas wrote: > From: Bjorn Helgaas >=20 > The Mediatek MT7922 WiFi device advertises FLR support, but it apparently > does not work, and all subsequent config reads return ~0: >=20 > pci 0000:01:00.0: [14c3:0616] type 00 class 0x028000 PCIe Endpoint > pciback 0000:01:00.0: not ready 65535ms after FLR; giving up >=20 > After an FLR, pci_dev_wait() waits for the device to become ready. Prior > to d591f6804e7e ("PCI: Wait for device readiness with Configuration RRS"), > it polls PCI_COMMAND until it is something other that PCI_POSSIBLE_ERROR > (~0). If it times out, pci_dev_wait() returns -ENOTTY and > __pci_reset_function_locked() tries the next available reset method. > Typically this is Secondary Bus Reset, which does work, so the MT7922 is > eventually usable. >=20 > After d591f6804e7e, if Configuration Request Retry Status Software > Visibility (RRS SV) is enabled, pci_dev_wait() polls PCI_VENDOR_ID until = it > is something other than the special 0x0001 Vendor ID that indicates a > completion with RRS status. >=20 > When RRS SV is enabled, reads of PCI_VENDOR_ID should return either 0x000= 1, > i.e., the config read was completed with RRS, or a valid Vendor ID. On t= he > MT7922, it seems that all config reads after FLR return ~0 indefinitely. > When pci_dev_wait() reads PCI_VENDOR_ID and gets 0xffff, it assumes that's > a valid Vendor ID and the device is now ready, so it returns with success. >=20 > After pci_dev_wait() returns success, we restore config space and continu= e. > Since the MT7922 is not actually ready after the FLR, the restore fails a= nd > the device is unusable. >=20 > We considered changing pci_dev_wait() to continue polling if a > PCI_VENDOR_ID read returns either 0x0001 or 0xffff. This "works" as it d= id > before d591f6804e7e, although we have to wait for the timeout and then fa= ll > back to SBR. But it doesn't work for SR-IOV VFs, which *always* return > 0xffff as the Vendor ID. >=20 > Mark Mediatek MT7922 WiFi devices to avoid the use of FLR completely. Th= is > will cause fallback to another reset method, such as SBR. >=20 > Fixes: d591f6804e7e ("PCI: Wait for device readiness with Configuration R= RS") > Link: https://github.com/QubesOS/qubes-issues/issues/9689#issuecomment-25= 82927149 > Link: https://lore.kernel.org/r/Z4pHll_6GX7OUBzQ@mail-itl > Signed-off-by: Bjorn Helgaas It works, thanks! Tested-by: Marek Marczykowski-G=C3=B3recki > --- > drivers/pci/quirks.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index b84ff7bade82..82b21e34c545 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -5522,7 +5522,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443,= quirk_intel_qat_vf_cap); > * AMD Matisse USB 3.0 Host Controller 0x149c > * Intel 82579LM Gigabit Ethernet Controller 0x1502 > * Intel 82579V Gigabit Ethernet Controller 0x1503 > - * > + * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter > */ > static void quirk_no_flr(struct pci_dev *dev) > { > @@ -5534,6 +5534,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, = quirk_no_flr); > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); > =20 > /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ > static void quirk_no_flr_snet(struct pci_dev *dev) > --=20 > 2.34.1 >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --0tz+zSavbvKwuCEI Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmetKG4ACgkQ24/THMrX 1yxrrQf8DcaaeLNDT4iNQ62TsecJBfBfwazR8kITzW+Ljwe2R5+WlZlSB58A/yN3 MAO8oyedNHISFcJ2YiqrGW/kFPGf3ns7PFfohV6DBYyNTjoj1UNywkWZ0zxXuaxH YnNLoNJeOZEVW86+MOgJZ67MaQqGbuuv2juS7SPVwteezRykssZLvepfPIonJiNt vK4WylRTvPH+Kkkf5Ys744gDdSd4virRagaIxrytlbF3BV6n1o5UTuuaYwRfJ/kj J+jAHvmFBHD2zEa1qCodVG/2GS1BuRD9TZ/dGHLUGH+vTikCUttyplbXpuhwgAoR Lb6nsNLNMm4iXqwgyfTw306hP01rVQ== =EIdg -----END PGP SIGNATURE----- --0tz+zSavbvKwuCEI--