From: Daniel Golle <daniel@makrotopia.org>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
"Uwe Kleine-König" <u.kleine-koenig@baylibre.com>,
"Sam Shih" <sam.shih@mediatek.com>,
"Frank Wunderlich" <frank-w@public-files.de>,
"Daniel Golle" <daniel@makrotopia.org>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>
Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical
Date: Fri, 1 Nov 2024 03:19:39 +0000 [thread overview]
Message-ID: <ZyRIy22aS_Yjoavg@pidgin.makrotopia.org> (raw)
SPI0 clocks have wrongly been marked as critical while, probably due
to the SPI driver not requesting them. This can (and should) be addressed
in device tree instead.
Remove CLK_IS_CRITICAL flag from clocks related to SPI0.
Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
index ef8267319d91..c40e18c27f12 100644
--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
@@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[] = {
GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
CLK_IS_CRITICAL),
- GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
- CLK_IS_CRITICAL),
+ GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12),
GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
- GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
- CLK_IS_CRITICAL),
+ GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15),
GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
--
2.47.0
next reply other threads:[~2024-11-01 3:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-01 3:19 Daniel Golle [this message]
2025-09-21 16:30 ` [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical Stephen Boyd
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