From: Matthias Brugger <matthias.bgg@gmail.com>
To: Rui Salvaterra <rsalvaterra@gmail.com>,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: ryder.lee@mediatek.com, daniel@makrotopia.org
Subject: Re: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
Date: Fri, 29 Apr 2022 14:58:25 +0200 [thread overview]
Message-ID: <a9300186-07f8-30c4-b5d8-e88f6f0ee629@gmail.com> (raw)
In-Reply-To: <20220428225755.785153-1-rsalvaterra@gmail.com>
On 29/04/2022 00:57, Rui Salvaterra wrote:
> On an MT7622 system, the kernel complains of not being able to detect the cache
> hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
> order to fix this.
>
> Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Applied, thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 6f8cb3ad1e84..3d6eaf6dd078 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -80,6 +80,7 @@ cpu0: cpu@0 {
> enable-method = "psci";
> clock-frequency = <1300000000>;
> cci-control-port = <&cci_control2>;
> + next-level-cache = <&L2>;
> };
>
> cpu1: cpu@1 {
> @@ -94,6 +95,12 @@ cpu1: cpu@1 {
> enable-method = "psci";
> clock-frequency = <1300000000>;
> cci-control-port = <&cci_control2>;
> + next-level-cache = <&L2>;
> + };
> +
> + L2: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> };
> };
>
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prev parent reply other threads:[~2022-04-29 12:58 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 22:57 [PATCH] arm64: dts: mt7622: specify the L2 cache topology Rui Salvaterra
2022-04-29 12:58 ` Matthias Brugger [this message]
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