* [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps
@ 2025-08-14 12:54 payne.lin
2025-08-15 9:43 ` CK Hu (胡俊光)
2025-08-20 16:17 ` Vinod Koul
0 siblings, 2 replies; 3+ messages in thread
From: payne.lin @ 2025-08-14 12:54 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Bincai Liu, Payne Lin
From: Bincai Liu <bincai.liu@mediatek.com>
Mipi dphy can support up to 4k30 without dsc.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
Signed-off-by: Payne Lin <payne.lin@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
index 553725e1269c..b8233c496070 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
- return clamp_val(rate, 125000000, 1600000000);
+ return clamp_val(rate, 125000000, 2500000000);
}
static const struct clk_ops mtk_mipi_tx_pll_ops = {
--
2.45.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps
2025-08-14 12:54 [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps payne.lin
@ 2025-08-15 9:43 ` CK Hu (胡俊光)
2025-08-20 16:17 ` Vinod Koul
1 sibling, 0 replies; 3+ messages in thread
From: CK Hu (胡俊光) @ 2025-08-15 9:43 UTC (permalink / raw)
To: vkoul@kernel.org, Chunfeng Yun (云春峰),
chunkuang.hu@kernel.org, AngeloGioacchino Del Regno,
Payne Lin (林于平), p.zabel@pengutronix.de,
matthias.bgg@gmail.com, kishon@kernel.org
Cc: Jh Hsu (許希孜),
Project_Global_Chrome_Upstream_Group,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Sirius Wang (王皓昱),
linux-arm-kernel@lists.infradead.org,
Vince-WL Liu (劉文龍),
linux-mediatek@lists.infradead.org,
Bincai Liu (刘彬才),
linux-phy@lists.infradead.org
On Thu, 2025-08-14 at 20:54 +0800, payne.lin wrote:
> From: Bincai Liu <bincai.liu@mediatek.com>
>
> Mipi dphy can support up to 4k30 without dsc.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
> Signed-off-by: Payne Lin <payne.lin@mediatek.com>
> ---
> drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> index 553725e1269c..b8233c496070 100644
> --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> @@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
> static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long *prate)
> {
> - return clamp_val(rate, 125000000, 1600000000);
> + return clamp_val(rate, 125000000, 2500000000);
> }
>
> static const struct clk_ops mtk_mipi_tx_pll_ops = {
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps
2025-08-14 12:54 [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps payne.lin
2025-08-15 9:43 ` CK Hu (胡俊光)
@ 2025-08-20 16:17 ` Vinod Koul
1 sibling, 0 replies; 3+ messages in thread
From: Vinod Koul @ 2025-08-20 16:17 UTC (permalink / raw)
To: payne.lin
Cc: Chun-Kuang Hu, Philipp Zabel, Chunfeng Yun,
Kishon Vijay Abraham I, Matthias Brugger,
AngeloGioacchino Del Regno, dri-devel, linux-mediatek,
linux-arm-kernel, linux-phy, linux-kernel,
Project_Global_Chrome_Upstream_Group, sirius.wang, vince-wl.liu,
jh.hsu, Bincai Liu
On 14-08-25, 20:54, payne.lin wrote:
> From: Bincai Liu <bincai.liu@mediatek.com>
>
> Mipi dphy can support up to 4k30 without dsc.
Good, how does that translate to below value change, can you please
explain?
>
> Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
> Signed-off-by: Payne Lin <payne.lin@mediatek.com>
> ---
> drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> index 553725e1269c..b8233c496070 100644
> --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> @@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
> static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long *prate)
> {
> - return clamp_val(rate, 125000000, 1600000000);
> + return clamp_val(rate, 125000000, 2500000000);
> }
>
> static const struct clk_ops mtk_mipi_tx_pll_ops = {
> --
> 2.45.2
--
~Vinod
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-08-20 20:50 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-14 12:54 [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps payne.lin
2025-08-15 9:43 ` CK Hu (胡俊光)
2025-08-20 16:17 ` Vinod Koul
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).