> On Wed, Oct 15, 2025 at 09:15:11AM +0200, Lorenzo Bianconi wrote:
> > AN7583 chipset relies on different definitions for source-port
> > identifier used for hw offloading. In order to support hw offloading
> > in AN7583 controller, refactor src port configuration in
> > airhoha_set_gdm2_loopback routine and introduce get_src_port_id
> > callback.
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  drivers/net/ethernet/airoha/airoha_eth.c  | 75 +++++++++++++++++++++----------
> >  drivers/net/ethernet/airoha/airoha_eth.h  | 11 +++--
> >  drivers/net/ethernet/airoha/airoha_regs.h |  5 +--
> >  3 files changed, 60 insertions(+), 31 deletions(-)
> > 
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > index 5f6b5ab52e0265f7bb56b008ca653d64e04ff2d2..76c82750b3ae89a9fa81c64d3b7c3578b369480c 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > @@ -1682,11 +1682,14 @@ static int airoha_dev_set_macaddr(struct net_device *dev, void *p)
> >  	return 0;
> >  }
> >  
> > -static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port)
> > +static int airhoha_set_gdm2_loopback(struct airoha_gdm_port *port)
> >  {
> >  	u32 pse_port = port->id == 3 ? FE_PSE_PORT_GDM3 : FE_PSE_PORT_GDM4;
> >  	struct airoha_eth *eth = port->qdma->eth;
> >  	u32 chan = port->id == 3 ? 4 : 0;
> > +	/* XXX: handle XSI_USB_PORT and XSI_PCE1_PORT */
> > +	u32 nbq = port->id == 3 ? 4 : 0;
> > +	int src_port;
> 
> I think this code could benefit for names (defines) for port ids.
> It's a bit clearer in airoha_en7581_get_src_port_id(). But the
> numbers seem kind of magic in this function.

ack, I will fix it in v2.

Regards,
Lorenzo

> 
> >  
> >  	/* Forward the traffic to the proper GDM port */
> >  	airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port);
> > @@ -1709,29 +1712,23 @@ static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port)
> >  	airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2));
> >  	airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2));
> >  
> > -	if (port->id == 3) {
> > -		/* FIXME: handle XSI_PCE1_PORT */
> > -		airoha_fe_rmw(eth, REG_FE_WAN_PORT,
> > -			      WAN1_EN_MASK | WAN1_MASK | WAN0_MASK,
> > -			      FIELD_PREP(WAN0_MASK, HSGMII_LAN_PCIE0_SRCPORT));
> > -		airoha_fe_rmw(eth,
> > -			      REG_SP_DFT_CPORT(HSGMII_LAN_PCIE0_SRCPORT >> 3),
> > -			      SP_CPORT_PCIE0_MASK,
> > -			      FIELD_PREP(SP_CPORT_PCIE0_MASK,
> > -					 FE_PSE_PORT_CDM2));
> > -	} else {
> > -		/* FIXME: handle XSI_USB_PORT */
> > +	src_port = eth->soc->ops.get_src_port_id(port, nbq);
> > +	if (src_port < 0)
> > +		return src_port;
> > +
> > +	airoha_fe_rmw(eth, REG_FE_WAN_PORT,
> > +		      WAN1_EN_MASK | WAN1_MASK | WAN0_MASK,
> > +		      FIELD_PREP(WAN0_MASK, src_port));
> > +	airoha_fe_rmw(eth, REG_SP_DFT_CPORT(src_port >> 3),
> > +		      SP_CPORT_MASK(src_port & 0x7),
> > +		      FE_PSE_PORT_CDM2 << __ffs(SP_CPORT_MASK(src_port & 0x7)));
> 
> Likewise, 3 and 0x7 a bit magical here.
> 
> > +
> > +	if (port->id != 3)
> >  		airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6,
> >  			      FC_ID_OF_SRC_PORT24_MASK,
> >  			      FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2));
> 
> ... and 2 here.
> 
> > -		airoha_fe_rmw(eth, REG_FE_WAN_PORT,
> > -			      WAN1_EN_MASK | WAN1_MASK | WAN0_MASK,
> > -			      FIELD_PREP(WAN0_MASK, HSGMII_LAN_ETH_SRCPORT));
> > -		airoha_fe_rmw(eth,
> > -			      REG_SP_DFT_CPORT(HSGMII_LAN_ETH_SRCPORT >> 3),
> > -			      SP_CPORT_ETH_MASK,
> > -			      FIELD_PREP(SP_CPORT_ETH_MASK, FE_PSE_PORT_CDM2));
> > -	}
> > +
> > +	return 0;
> >  }
> 
> ...
> 
> > @@ -3055,11 +3057,38 @@ static const char * const en7581_xsi_rsts_names[] = {
> >  	"xfp-mac",
> >  };
> >  
> > +static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq)
> > +{
> > +	switch (port->id) {
> > +	case 3:
> > +		/* 7581 SoC supports PCIe serdes on GDM3 port */
> > +		if (nbq == 4)
> > +			return HSGMII_LAN_7581_PCIE0_SRCPORT;
> > +		if (nbq == 5)
> > +			return HSGMII_LAN_7581_PCIE1_SRCPORT;
> > +		break;
> > +	case 4:
> > +		/* 7581 SoC supports eth and usb serdes on GDM4 port */
> > +		if (!nbq)
> > +			return HSGMII_LAN_7581_ETH_SRCPORT;
> > +		if (nbq == 1)
> > +			return HSGMII_LAN_7581_USB_SRCPORT;
> > +		break;
> > +	default:
> > +		break;
> > +	}
> > +
> > +	return -EINVAL;
> > +}
> 
> ...