From: Krzysztof Kozlowski <krzk@kernel.org>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Laura Nao <laura.nao@collabora.com>,
wenst@chromium.org
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
guangjie.song@mediatek.com, kernel@collabora.com,
krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com,
mturquette@baylibre.com, netdev@vger.kernel.org,
nfraprado@collabora.com, p.zabel@pengutronix.de,
richardcochran@gmail.com, robh@kernel.org, sboyd@kernel.org
Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers
Date: Mon, 4 Aug 2025 16:21:30 +0200 [thread overview]
Message-ID: <c16070db-c086-45b8-bc0d-9e3bc02924b6@kernel.org> (raw)
In-Reply-To: <62edb8e3-aff6-4225-b520-f4b73aef145d@collabora.com>
On 04/08/2025 16:15, AngeloGioacchino Del Regno wrote:
> Il 04/08/25 15:58, Krzysztof Kozlowski ha scritto:
>> On 04/08/2025 15:27, AngeloGioacchino Del Regno wrote:
>>>
>>> We discussed about aggregating votes, yes, in software - this instead is a
>>> *broken* hardware that does the aggregation internally and does not require
>>> nor want external drivers to do the aggregation.
>>>
>>>> Maybe it is just the name, so avoid all the confusing "votes" if this is
>>>> not voting system. If this is a voting system, then don't use custom
>>>> phandles.
>>>
>>> Being it fundamentally *broken*, this being a voting system is what the hardware
>>> initially wanted to be - but effectively, since it requires YOU to:
>>> - Make sure that power supplies are turned on, if not, turn them on by "touching"
>>> HW registers (so, without any assistance from the voter MCU), if any;
>>> - Turn on parent clocks manually, if any, before using the "voter mcu" to try
>>> to ungate that clock; and
>>> - Enable the "FENC" manually, after the mcu says that the clock was ungated.
>>
>>
>> I understand that "YOU" as Linux driver, when you want to do something
>> (e.g. toggle) a clock?
>
> "you" == Linux driver, yes.
>
>> If so this looks a lot like power domain, although with some differences.
>>
>
> A power domain ungates power to something.
Does more, it is not a simple supply.
>
> These are clocks, giving a (x) (M)Hz signal to something.
Your earlier message about "YOU" said:
" - Make sure that power supplies are turned on, if not, turn them on
by "touching"
HW registers (so, without any assistance from the voter MCU), if any;"
so not a simple clocks stuff.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-04 15:04 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 10:56 [PATCH v3 00/27] Add support for MT8196 clock controllers Laura Nao
2025-07-30 10:56 ` [PATCH v3 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-07-30 10:56 ` [PATCH v3 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-07-30 10:56 ` [PATCH v3 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-07-30 10:56 ` [PATCH v3 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-07-30 10:56 ` [PATCH v3 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-08-04 14:05 ` Krzysztof Kozlowski
2025-08-04 14:33 ` AngeloGioacchino Del Regno
2025-07-30 10:56 ` [PATCH v3 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-07-30 10:56 ` [PATCH v3 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-07-30 10:56 ` [PATCH v3 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-07-30 10:56 ` [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-01 13:57 ` Rob Herring
2025-08-03 8:17 ` Krzysztof Kozlowski
2025-08-04 8:35 ` Laura Nao
2025-08-04 9:16 ` Krzysztof Kozlowski
2025-08-04 9:27 ` AngeloGioacchino Del Regno
2025-08-04 11:01 ` Krzysztof Kozlowski
2025-08-04 13:27 ` AngeloGioacchino Del Regno
2025-08-04 13:58 ` Krzysztof Kozlowski
2025-08-04 14:15 ` AngeloGioacchino Del Regno
2025-08-04 14:21 ` Krzysztof Kozlowski [this message]
2025-08-04 14:25 ` AngeloGioacchino Del Regno
2025-08-04 14:19 ` Krzysztof Kozlowski
2025-08-04 14:31 ` AngeloGioacchino Del Regno
2025-08-04 14:33 ` Krzysztof Kozlowski
2025-08-04 14:35 ` AngeloGioacchino Del Regno
2025-08-03 8:15 ` Krzysztof Kozlowski
2025-07-30 10:56 ` [PATCH v3 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-07-30 10:56 ` [PATCH v3 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-07-30 10:56 ` [PATCH v3 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-07-30 10:56 ` [PATCH v3 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-07-30 10:56 ` [PATCH v3 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-07-30 10:56 ` [PATCH v3 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-07-30 10:56 ` [PATCH v3 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao
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