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Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Eric Dumazet , kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Date: Wed, 21 Oct 2026 11:43:39 +0200 In-Reply-To: References: <20261016-dwmac-mediatek-mt8189-v3-0-25daf2bbcf35@collabora.com> <20261016-dwmac-mediatek-mt8189-v3-2-25daf2bbcf35@collabora.com> Organization: Collabora Ltd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.60.2 (3.60.2-2.fc44) X-Archived-By: MIME-Version: 1.0 X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261021_104422_962124_7E9C4DC9 X-CRM114-Status: GOOD ( 20.34 ) X-Spam-Score: -0.2 (/) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Andrew, On Fri, 2026-10-16 at 17:40 +0200, Andrew Lunn wrote: > > Finally, update "mediatek,rx-delay-ps" and "mediatek,tx-delay-ps" > > property > > description to add MT8189 RX/TX delay stage divider values, as they > > differ from existing supported SoC. >=20 > These should be mark deprecated and the standard rx-internal-delay-ps > and tx-internal-delay-ps used in there place for new devices. >=20 I agree, it makes sense to use them to describe the RGMII internal delay configurations rather than the two existing vendor properties (mediatek,rx-delay-ps and mediatek,tx-delay-ps), and deprecate them, by adding a deprecated flag and the comments you've suggested. It would also need an additional patch for the driver to handle them (while keeping backward compatibility). But what is bothering me is these two vendor properties description says they can be used in MII and RMII phy mode cases. The driver uses them indeed also to fine tune the RX/TX_CLK (in MII) or the REF_CLK (in RMII) configuration. rx/tx-internal-delay-ps properties are limited to RGMII only ([1]). So they can not substitute them as it and with their description it would wrong to use them for MII/RMII. At the moment, in the upstream devicetrees, there is no "mediatek,rx- delay-ps" use and the "mediatek,tx-delay-ps" use are very few and only for RGMII phy modes (either rgmii-rxid or rmgii-id), so no MII/RMII real use cases. So, how to proceed then to make these bindings right? Use rx/tx-internal-delay-ps properties for RGMII and mediatek,rx/tx- delay-ps for MII/RMII or do you see another solution ? Best regards, Louis-Alexis [1]: https://elixir.bootlin.com/linux/v7.3/source/Documentation/devicetree/bindi= ngs/net/ethernet-controller.yaml#L251 > > @@ -86,8 +85,10 @@ properties: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 or will round down. Range 0~31*170= . > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT2712 RMII/MII interface, All= owed value need to be a > > multiple of 550, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 or will round down. Range 0~31*550= . > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT8188/MT8195 RGMII/RMII/MII interf= ace, Allowed value > > need to be a multiple of 290, > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 or will round down. Range 0~31*290. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT8188/MT8195 RGMII/RMII/MII interf= ace, Allowed value > > need to be a > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 multiple of 290, or will round down. Ra= nge 0~31*290. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT8189 RGMII/RMII/MII interface, Al= lowed value need to > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 be a multiple of 180, or will round dow= n. Range 0~31*180. >=20 > Please make this: >=20 > For MT8189 RGMII/RMII/MII interface, this property is not used, the > standard tx-internal-delay-ps should be used instead. >=20 > > @@ -96,8 +97,10 @@ properties: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 or will round down. Range 0~31*170= . > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT2712 RMII/MII interface, All= owed value need to be a > > multiple of 550, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 or will round down. Range 0~31*550= . > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT8188/MT8195 RGMII/RMII/MII interf= ace, Allowed value > > need to be a multiple > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 of 290, or will round down. Range 0~31*= 290. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT8188/MT8195 RGMII/RMII/MII interf= ace, Allowed value > > need to be a > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 multiple of 290, or will round down. Ra= nge 0~31*290. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For MT8189 RGMII/RMII/MII interface, Al= lowed value need to > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 be a multiple of 180, or will round dow= n. Range 0~31*180. >=20 > Same here. >=20 > =C2=A0=C2=A0=C2=A0=C2=A0 Andrew