From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: "CK Hu (胡俊光)" <ck.hu@mediatek.com>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>,
"airlied@gmail.com" <airlied@gmail.com>,
"bisson.gary@gmail.com" <bisson.gary@gmail.com>,
"simona@ffwll.ch" <simona@ffwll.ch>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>
Cc: "dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable
Date: Wed, 25 Feb 2026 14:16:43 +0100 [thread overview]
Message-ID: <c81b458a-76db-4977-941b-5c9ddca0231a@collabora.com> (raw)
In-Reply-To: <80cecc13015aca7fe68dd40845e60af4bad42223.camel@mediatek.com>
Il 25/02/26 07:20, CK Hu (胡俊光) ha scritto:
> On Tue, 2026-01-20 at 12:36 +0100, Gary Bisson wrote:
>> External email : Please do not click links or open attachments until you have verified the sender or the content.
>>
>>
>> Some bridges, such as the TI SN65DSI83, require the HS clock to be
>> running in order to lock its PLL during its own pre-enable function.
>>
>> Without this change, the bridge gives the following error:
>> sn65dsi83 14-002c: failed to lock PLL, ret=-110
>> sn65dsi83 14-002c: Unexpected link status 0x01
>> sn65dsi83 14-002c: reset the pipe
>>
>> Move the necessary functions from enable to pre-enable.
>
> Looks good to me, but this change the flow for all SoC and panel,
> so I would wait for more SoC and more panel test.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
Tested on
- MT6795 Sony Xperia M5 w/DSI panel (with local changes, as the panel is not
upstream yet)
- MT8395 Radxa NIO-12L w/ Radxa Display 8HD
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Nice patch, btw ;-)
Cheers,
Angelo
>>
>> Signed-off-by: Gary Bisson <bisson.gary@gmail.com>
>> ---
>> Tested on Tungsten510 module with sn65dsi83 + tm070jdhg30 panel.
>>
>> Left mtk_dsi_set_mode() as part of the enable function to mimic what is
>> done in the Samsung DSIM driver which is known to be working the TI
>> bridge.
>> ---
>> drivers/gpu/drm/mediatek/mtk_dsi.c | 35 +++++++++++++++++------------------
>> 1 file changed, 17 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
>> index 0e2bcd5f67b7..b560245d1be9 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>> @@ -672,6 +672,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
>> }
>> }
>>
>> +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
>> +{
>> + if (!dsi->lanes_ready) {
>> + dsi->lanes_ready = true;
>> + mtk_dsi_rxtx_control(dsi);
>> + usleep_range(30, 100);
>> + mtk_dsi_reset_dphy(dsi);
>> + mtk_dsi_clk_ulp_mode_leave(dsi);
>> + mtk_dsi_lane0_ulp_mode_leave(dsi);
>> + mtk_dsi_clk_hs_mode(dsi, 0);
>> + usleep_range(1000, 3000);
>> + /* The reaction time after pulling up the mipi signal for dsi_rx */
>> + }
>> +}
>> +
>> static int mtk_dsi_poweron(struct mtk_dsi *dsi)
>> {
>> struct device *dev = dsi->host.dev;
>> @@ -724,6 +739,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
>> mtk_dsi_set_vm_cmd(dsi);
>> mtk_dsi_config_vdo_timing(dsi);
>> mtk_dsi_set_interrupt_enable(dsi);
>> + mtk_dsi_lane_ready(dsi);
>> + mtk_dsi_clk_hs_mode(dsi, 1);
>>
>> return 0;
>> err_disable_engine_clk:
>> @@ -769,30 +786,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
>> dsi->lanes_ready = false;
>> }
>>
>> -static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
>> -{
>> - if (!dsi->lanes_ready) {
>> - dsi->lanes_ready = true;
>> - mtk_dsi_rxtx_control(dsi);
>> - usleep_range(30, 100);
>> - mtk_dsi_reset_dphy(dsi);
>> - mtk_dsi_clk_ulp_mode_leave(dsi);
>> - mtk_dsi_lane0_ulp_mode_leave(dsi);
>> - mtk_dsi_clk_hs_mode(dsi, 0);
>> - usleep_range(1000, 3000);
>> - /* The reaction time after pulling up the mipi signal for dsi_rx */
>> - }
>> -}
>> -
>> static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
>> {
>> if (dsi->enabled)
>> return;
>>
>> - mtk_dsi_lane_ready(dsi);
>> mtk_dsi_set_mode(dsi);
>> - mtk_dsi_clk_hs_mode(dsi, 1);
>> -
>> mtk_dsi_start(dsi);
>>
>> dsi->enabled = true;
>>
>> ---
>> base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
>> change-id: 20260120-mtkdsi-29e4c84e7b38
>>
>> Best regards,
>> --
>> Gary Bisson <bisson.gary@gmail.com>
>>
>>
>
next prev parent reply other threads:[~2026-02-25 13:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-20 11:36 [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable Gary Bisson
2026-02-25 6:20 ` CK Hu (胡俊光)
2026-02-25 8:20 ` Chen-Yu Tsai
2026-02-25 13:16 ` AngeloGioacchino Del Regno [this message]
2026-03-22 12:48 ` Chun-Kuang Hu
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