Re: [v4,PATCH 1/3] drm/mediatek: dpi dual edge sample mode support

[Rex-BC Chen <rex-bc.chen@mediatek.com>]

Hello CK,

Thanks for your review.

On Wed, 2021-05-26 at 08:01 +0800, Chun-Kuang Hu wrote:
> Hi, Rex:
> 
> Rex-BC Chen <rex-bc.chen@mediatek.com> 於 2021年5月25日 週二 下午8:15寫道：
> > 
> > DPI can sample on falling, rising or both edge.
> > When DPI sample the data both rising and falling edge.
> > It can reduce half data io pins.
> > Use num_output_fmts to determine whether it is dual edge mode.
> > 
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dpi.c | 17 ++++++++++++++++-
> >  1 file changed, 16 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index bea91c81626e..d3b883c97aaf 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -83,6 +83,7 @@ struct mtk_dpi {
> >         struct pinctrl *pinctrl;
> >         struct pinctrl_state *pins_gpio;
> >         struct pinctrl_state *pins_dpi;
> > +       bool ddr_edge_sel;
> 
> I would like to keep output_fmt instead of ddr_edge_sel.
> Initialize output_fmt to MEDIA_BUS_FMT_RGB888_1X24 in this patch.
> 
It means that I may initialize output_fmt in probe and set value in
mtk_dpi_bridge_atomic_check() of patch[3/3]?
> >         int refcount;
> >  };
> > 
> > @@ -122,6 +123,8 @@ struct mtk_dpi_conf {
> >         u32 reg_h_fre_con;
> >         u32 max_clock_khz;
> >         bool edge_sel_en;
> > +       const u32 *output_fmts;
> > +       u32 num_output_fmts;
> 
> Move these to next patch.
> 
I will do this in next version.
> >  };
> > 
> >  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val,
> > u32 mask)
> > @@ -381,6 +384,16 @@ static void mtk_dpi_config_color_format(struct
> > mtk_dpi *dpi,
> >         }
> >  }
> > 
> > +static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
> > +{
> > +       if (dpi->conf->num_output_fmts > 1) {
> > +               mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN |
> > DDR_4PHASE,
> > +                            DDR_EN | DDR_4PHASE);
> > +               mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
> > +                            dpi->ddr_edge_sel ? EDGE_SEL : 0,
> > EDGE_SEL);
> > +       }
> 
> if (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
>    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE) {
>     mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, DDR_EN |
> DDR_4PHASE);
>     mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
>                              dpi->output_fmt ==
> MEDIA_BUS_FMT_RGB888_2X12_LE ? EDGE_SEL : 0, EDGE_SEL);
> } else {
>     mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
> }
> 
I will modify this code in next version.
> > +}
> > +
> >  static void mtk_dpi_power_off(struct mtk_dpi *dpi)
> >  {
> >         if (WARN_ON(dpi->refcount == 0))
> > @@ -455,7 +468,8 @@ static int mtk_dpi_set_display_mode(struct
> > mtk_dpi *dpi,
> >         pll_rate = clk_get_rate(dpi->tvd_clk);
> > 
> >         vm.pixelclock = pll_rate / factor;
> > -       clk_set_rate(dpi->pixel_clk, vm.pixelclock);
> > +       clk_set_rate(dpi->pixel_clk,
> > +                    vm.pixelclock * ((dpi->conf->num_output_fmts >
> > 1) ? 2 : 1));
> 
> if (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
>    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)
>     clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
> else
>     clk_set_rate(dpi->pixel_clk, vm.pixelclock);
> 
I will modify this code in next version.
> >         vm.pixelclock = clk_get_rate(dpi->pixel_clk);
> > 
> >         dev_dbg(dpi->dev, "Got  PLL %lu Hz, pixel clock %lu Hz\n",
> > @@ -519,6 +533,7 @@ static int mtk_dpi_set_display_mode(struct
> > mtk_dpi *dpi,
> >         mtk_dpi_config_yc_map(dpi, dpi->yc_map);
> >         mtk_dpi_config_color_format(dpi, dpi->color_format);
> >         mtk_dpi_config_2n_h_fre(dpi);
> > +       mtk_dpi_dual_edge(dpi);
> >         mtk_dpi_config_disable_edge(dpi);
> >         mtk_dpi_sw_reset(dpi, false);
> > 
> > --
> > 2.18.0

BRs,
Rex-BC Chen
> > 
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