Re: [1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

[Rex-BC Chen <rex-bc.chen@mediatek.com>]

Hello Angelo,

Thanks for yor review.
I add reply comment below:

On Tue, 2022-02-15 at 14:54 +0100, AngeloGioacchino Del Regno wrote:
> Il 15/02/22 14:19, Rex-BC Chen ha scritto:
> > There are different software reset registers for difference MTK
> > SoCs.
> > Therefore, we add a new variable "sw0_rst_offset" to control it.
> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
> >   drivers/soc/mediatek/mtk-mmsys.c    | 6 ++++--
> >   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
> >   3 files changed, 7 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> > b/drivers/soc/mediatek/mt8183-mmsys.h
> > index 9dee485807c9..0c021f4b76d2 100644
> > --- a/drivers/soc/mediatek/mt8183-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> > @@ -25,6 +25,8 @@
> >   #define MT8183_RDMA0_SOUT_COLOR0		0x1
> >   #define MT8183_RDMA1_SOUT_DSI0			0x1
> >   
> > +#define MT8183_MMSYS_SW0_RST_B			0x140
> > +
> >   static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[]
> > = {
> >   	{
> >   		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 0da25069ffb3..cab62c3eac05 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8173-mm",
> >   	.routes = mmsys_default_routing_table,
> >   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> >   };
> >   
> >   static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8183-mm",
> >   	.routes = mmsys_mt8183_routing_table,
> >   	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> >   };
> >   
> >   static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > @@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct
> > reset_controller_dev *rcdev, unsigned l
> >   
> >   	spin_lock_irqsave(&mmsys->lock, flags);
> >   
> > -	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
> > +	reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
> >   
> >   	if (assert)
> >   		reg &= ~BIT(id);
> >   	else
> >   		reg |= BIT(id);
> >   
> > -	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
> > +	writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
> >   
> >   	spin_unlock_irqrestore(&mmsys->lock, flags);
> >   
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 8b0ed05117ea..83320019b4cf 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -78,8 +78,6 @@
> >   #define DSI_SEL_IN_RDMA				0x1
> >   #define DSI_SEL_IN_MASK				0x1
> >   
> > -#define MMSYS_SW0_RST_B				0x140
> > -
> >   struct mtk_mmsys_routes {
> >   	u32 from_comp;
> >   	u32 to_comp;
> > @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
> >   	const char *clk_driver;
> >   	const struct mtk_mmsys_routes *routes;
> >   	const unsigned int num_routes;
> > +	const unsigned int sw0_rst_offset;
> 
> I don't think that this offset will ever be larger than 0xffff.
> Can we use u16 here instead?
> 
Yes, the value of offset is enough using u16.
I will modify this in next version.

BRs,
Rex
> >   };
> >   
> >   /*
> 
> 
> 


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