From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99F84C433EF for ; Mon, 11 Jul 2022 06:22:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TJW695w0QAgY3y3ZKqDD452aFyPVCvRpVBTpxCB4Tjo=; b=ve+QTfO650sve0murc17AhyrCx 4tQQPlkII3rHL5NtKya2rO3q/m1OrWuPwl9yWom2ErsqvSBxsgwHPoSOhRlyvFNHJnVAvWruBz9Zu 2Hb4Uuz3l+cSiWDnbw6JMmL4e1s3vqOjqmH2djRq8+CrX5lmiTxaIKECTafmts1ejcj2vw3PotksK YUMhNSusWZAzs2Tr3Geuas3inv+0drM5S5rlsevi9h2FLb10aSBBiRRwCkkkuNT7FnvrrJrwXeLmJ v+UYmkpUOw5dR6p/hHD9GXl+tYKmCleg3PqEgwgb6cKIB6benNYO98/i9mOPROMzXqOwj1UJtR92x fIiqpHfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oAmo6-00GNzs-TH; Mon, 11 Jul 2022 06:22:10 +0000 Received: from [216.200.240.184] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oAmnt-00GNw5-Hu; Mon, 11 Jul 2022 06:22:01 +0000 X-UUID: 86ba5ce326ee48028dba5df3a8e98035-20220710 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:f940dfbf-b226-4425-9a62-d841a712edbc,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:0f94e32,CLOUDID:10b321d7-5d6d-4eaf-a635-828a3ee48b7c,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 86ba5ce326ee48028dba5df3a8e98035-20220710 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2030162259; Sun, 10 Jul 2022 23:21:47 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 11 Jul 2022 14:01:09 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 11 Jul 2022 14:01:09 +0800 Message-ID: Subject: Re: [PATCH v24 07/10] soc: mediatek: mmsys: add mmsys for support 64 reset bits From: Nancy.Lin To: Matthias Brugger , Rob Herring , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Date: Mon, 11 Jul 2022 14:01:09 +0800 In-Reply-To: <5841cdea-2587-5bd8-3e6c-19e49121677a@gmail.com> References: <20220622130824.29143-1-nancy.lin@mediatek.com> <20220622130824.29143-8-nancy.lin@mediatek.com> <5841cdea-2587-5bd8-3e6c-19e49121677a@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220710_232157_605191_19AEF841 X-CRM114-Status: GOOD ( 25.73 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Matthias, Thanks for the review. On Fri, 2022-07-08 at 17:42 +0200, Matthias Brugger wrote: > > On 22/06/2022 15:08, Nancy.Lin wrote: > > Add mmsys for support 64 reset bits. It is a preparation for MT8195 > > vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits. > > > > 1. Add the number of reset bits in mmsys private data > > 2. move the whole "reset register code section" behind the > > "get mmsys->data" code section for getting the num_resets in mmsys- > > >data. > > > > Signed-off-by: Nancy.Lin > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > Reviewed-by: CK Hu > > Tested-by: Bo-Chen Chen > > --- > > drivers/soc/mediatek/mtk-mmsys.c | 35 ++++++++++++++++++++------- > > ----- > > drivers/soc/mediatek/mtk-mmsys.h | 1 + > > 2 files changed, 23 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c > > b/drivers/soc/mediatek/mtk-mmsys.c > > index 16be77d5acac..47b72ae72cc2 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -20,6 +20,8 @@ > > #include "mt8195-mmsys.h" > > #include "mt8365-mmsys.h" > > > > +#define MMSYS_SW_RESET_PER_REG 32 > > + > > static const struct mtk_mmsys_driver_data > > mt2701_mmsys_driver_data = { > > .clk_driver = "clk-mt2701-mm", > > .routes = mmsys_default_routing_table, > > @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data > > mt8173_mmsys_driver_data = { > > .routes = mmsys_default_routing_table, > > .num_routes = ARRAY_SIZE(mmsys_default_routing_table), > > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, > > + .num_resets = 32, > > }; > > > > static const struct mtk_mmsys_match_data mt8173_mmsys_match_data > > = { > > @@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data > > mt8183_mmsys_driver_data = { > > .routes = mmsys_mt8183_routing_table, > > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), > > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, > > + .num_resets = 32, > > }; > > > > static const struct mtk_mmsys_match_data mt8183_mmsys_match_data > > = { > > @@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data > > mt8186_mmsys_driver_data = { > > .routes = mmsys_mt8186_routing_table, > > .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), > > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, > > + .num_resets = 32, > > }; > > > > static const struct mtk_mmsys_match_data mt8186_mmsys_match_data > > = { > > @@ -288,10 +293,14 @@ static int mtk_mmsys_reset_update(struct > > reset_controller_dev *rcdev, unsigned l > > { > > struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, > > rcdev); > > unsigned long flags; > > + u32 offset; > > + > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); > > + id = id % MMSYS_SW_RESET_PER_REG; > > > > spin_lock_irqsave(&mmsys->lock, flags); > > > > - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, > > BIT(id), > > + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset + > > offset, BIT(id), > > assert ? 0 : BIT(id), NULL); > > reg = mmsys->data->sw0_rst_offset + offset; > mtk_mmsys_update_bits(mmsys, reg, BIT(id), > assert ? 0 : BIT(id), NULL); > > Other then that, patch looks good. > By the way setting val depending on assert in the function call gets > (for me) > hard to read, as I said earlier. > > Regards, > Matthias > OK, I will add reg variable and modify it as you said in [1]. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220622130824.29143-5-nancy.lin@mediatek.com/ BRs, Nancy > > > > spin_unlock_irqrestore(&mmsys->lock, flags); > > @@ -349,18 +358,6 @@ static int mtk_mmsys_probe(struct > > platform_device *pdev) > > return ret; > > } > > > > - spin_lock_init(&mmsys->lock); > > - > > - mmsys->rcdev.owner = THIS_MODULE; > > - mmsys->rcdev.nr_resets = 32; > > - mmsys->rcdev.ops = &mtk_mmsys_reset_ops; > > - mmsys->rcdev.of_node = pdev->dev.of_node; > > - ret = devm_reset_controller_register(&pdev->dev, &mmsys- > > >rcdev); > > - if (ret) { > > - dev_err(&pdev->dev, "Couldn't register mmsys reset > > controller: %d\n", ret); > > - return ret; > > - } > > - > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > if (!res) { > > dev_err(dev, "Couldn't get mmsys resource\n"); > > @@ -382,6 +379,18 @@ static int mtk_mmsys_probe(struct > > platform_device *pdev) > > mmsys->data = match_data->drv_data[0]; > > } > > > > + spin_lock_init(&mmsys->lock); > > + > > + mmsys->rcdev.owner = THIS_MODULE; > > + mmsys->rcdev.nr_resets = mmsys->data->num_resets; > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; > > + mmsys->rcdev.of_node = pdev->dev.of_node; > > + ret = devm_reset_controller_register(&pdev->dev, &mmsys- > > >rcdev); > > + if (ret) { > > + dev_err(&pdev->dev, "Couldn't register mmsys reset > > controller: %d\n", ret); > > + return ret; > > + } > > + > > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > > ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); > > if (ret) > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h > > b/drivers/soc/mediatek/mtk-mmsys.h > > index f01ba206481d..20a271b80b3b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.h > > +++ b/drivers/soc/mediatek/mtk-mmsys.h > > @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data { > > const struct mtk_mmsys_routes *routes; > > const unsigned int num_routes; > > const u16 sw0_rst_offset; > > + const u32 num_resets; > > }; > > > > struct mtk_mmsys_match_data {