Re: [PATCH v5 05/18] clk: mediatek: Add MT8189 vlpckgen clock support

David Lechner
2026-02-19T21:10:53Z

On 2/2/26 12:28 AM, irving.ch.lin wrote:
> From: Irving-CH Lin <irving-ch.lin@mediatek.com>
>
> Add support for the MT8189 vlpckgen clock controller, which provides
> muxes and dividers for clock selection in vlp domain for other IP blocks.
>
> Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
> ---

...

> +static const struct mtk_gate vlp_ck_clks[] = {
> + GATE_VLP_CK(CLK_VLP_CK_VADSYS_VLP_26M_EN, "vlp_vadsys_vlp_26m", "clk26m", 1),

In mediatek,mt8189-clk.h, we have:

#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24
#define CLK_VLP_CK_SEJ_13M_EN 25
#define CLK_VLP_CK_SEJ_26M_EN 26
#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 27

Are we missing the middle two clocks here?

Or should the be omitted from the header file?

> + GATE_VLP_CK_FLAGS(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, "VLP_fmipi_csi_up26m",
> + "osc_d10", 11, CLK_IS_CRITICAL),
> +};
> +