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From: "Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>
To: "aford173@gmail.com" <aford173@gmail.com>
Cc: "Guangjie Song (宋光杰)" <Guangjie.Song@mediatek.com>,
	"robh@kernel.org" <robh@kernel.org>,
	"kernel@collabora.com" <kernel@collabora.com>,
	"Sirius Wang (王皓昱)" <Sirius.Wang@mediatek.com>,
	"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"richardcochran@gmail.com" <richardcochran@gmail.com>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"Laura Nao" <laura.nao@collabora.com>,
	"Nicolas Prado" <nfraprado@collabora.com>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"Singo Chang (張興國)" <Singo.Chang@mediatek.com>,
	"Paul-pl Chen (陳柏霖)" <Paul-pl.Chen@mediatek.com>,
	"wenst@chromium.org" <wenst@chromium.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"sboyd@kernel.org" <sboyd@kernel.org>
Subject: Re: [PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao clock support
Date: Thu, 9 Apr 2026 06:30:08 +0000	[thread overview]
Message-ID: <e147ef12bf73dc28a497c9b95c10faba7b293eca.camel@mediatek.com> (raw)
In-Reply-To: <CAHCN7x+K25H-QWLDA6SoGSzxv9koO0wFOrjfWNePc+0AfjCVZg@mail.gmail.com>

> 
[snip]

> > > > > +static const struct of_device_id
> > > > > of_match_clk_mt8196_vdisp_ao[]
> > > > > = {
> > > > > + { .compatible = "mediatek,mt8196-vdisp-ao", .data =
> > > > > &mm_v_mcd },
> > > > 
> > > > Hi Laura,
> > > > 
> > > > We are going to send mtk-mmsys driver for MT8196 recently, but
> > > > we
> > > > found
> > > > the compatible name is used here.
> > > > 
> > > > As your commit message, vdisp-ao is integrated with the mtk-
> > > > mmsys
> > > > driver, which registers the vdisp-ao clock driver via 
> > > > platform_device_register_data().
> > > > 
> > > > Shouldn't this compatible name belong to mmsys driver for
> > > > MT8196?
> > > > 
> > > 
> > > That's right, my fault for missing that! Thanks for the heads up.
> > > 
> > > I'm aware Angelo is currently restructuring mediatek-drm
> > > (including 
> > > mmsys and mutex), and that might affect the way vdisp-ao is
> > > loaded
> > > too. 
> > > So I'm not sure whether it makes sense to send a patch to fix
> > > this 
> > > right away.
> > 
> > OK, we'll try to contact Angelo from other places.
> > Thanks for your confirmation!
> > 
> 
> 
> If anyone wants me to test anything, I have a Chromebook with the
> mt8196 that I can test code, so feel free to CC me on anything that
> you want tested.  I'd love to see this stuff pushed upstream.
> 
> thanks
> 
> adam 

Hi Adam,
However, we still need some more time to discuss and refactor this.
We'll send the new patch if necessary.
Thank you for your help!

Regards,
Jason-JH Lin

> > 
> > Regards,
> > Jason-JH.Lin
> > 
> > > 
> > > Best,
> > > 
> > > Laura
> > > 
> > 


  parent reply	other threads:[~2026-04-09  6:30 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-29  9:18 [PATCH v5 00/27] Add support for MT8196 clock controllers Laura Nao
2025-08-29  9:18 ` [PATCH v5 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-08-29  9:18 ` [PATCH v5 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-08-29  9:18 ` [PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-09-05  4:09   ` Chen-Yu Tsai
2025-08-29  9:18 ` [PATCH v5 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-08-29  9:18 ` [PATCH v5 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-09-05  4:11   ` Chen-Yu Tsai
2025-08-29  9:18 ` [PATCH v5 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-09-05  4:13   ` Chen-Yu Tsai
2025-09-05  8:20   ` AngeloGioacchino Del Regno
2025-08-29  9:18 ` [PATCH v5 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-09-05  4:25   ` Chen-Yu Tsai
2025-08-29  9:18 ` [PATCH v5 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-08-29  9:18 ` [PATCH v5 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-29  9:18 ` [PATCH v5 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-08-29  9:18 ` [PATCH v5 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-08-29  9:18 ` [PATCH v5 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-08-29  9:18 ` [PATCH v5 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-09-05  5:01   ` Chen-Yu Tsai
2025-09-05  8:20   ` AngeloGioacchino Del Regno
2025-08-29  9:19 ` [PATCH v5 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-09-05  5:05   ` Chen-Yu Tsai
2025-09-05  8:11     ` AngeloGioacchino Del Regno
2025-08-29  9:19 ` [PATCH v5 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-09-05  6:36   ` Chen-Yu Tsai
2025-09-05  8:40   ` AngeloGioacchino Del Regno
2025-08-29  9:19 ` [PATCH v5 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-09-05  7:24   ` Chen-Yu Tsai
2025-08-29  9:19 ` [PATCH v5 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-08-29  9:19 ` [PATCH v5 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-08-29  9:19 ` [PATCH v5 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-09-05  8:04   ` Chen-Yu Tsai
2025-09-05  8:39   ` AngeloGioacchino Del Regno
2025-09-05  8:53     ` Chen-Yu Tsai
2025-09-15 10:33       ` AngeloGioacchino Del Regno
2025-08-29  9:19 ` [PATCH v5 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-08-29  9:19 ` [PATCH v5 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-08-29  9:19 ` [PATCH v5 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-09-05  8:03   ` Chen-Yu Tsai
2025-09-05  8:40   ` AngeloGioacchino Del Regno
2025-08-29  9:19 ` [PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2026-04-02  6:30   ` Jason-JH Lin (林睿祥)
2026-04-02 10:05     ` Laura Nao
2026-04-03  8:54       ` Jason-JH Lin (林睿祥)
     [not found]         ` <CAHCN7x+K25H-QWLDA6SoGSzxv9koO0wFOrjfWNePc+0AfjCVZg@mail.gmail.com>
2026-04-09  6:30           ` Jason-JH Lin (林睿祥) [this message]
2025-08-29  9:19 ` [PATCH v5 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-08-29  9:19 ` [PATCH v5 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-08-29  9:19 ` [PATCH v5 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-08-29  9:19 ` [PATCH v5 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao

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