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Thu, 25 Aug 2022 03:55:19 -0700 (PDT) Message-ID: Date: Thu, 25 Aug 2022 12:55:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.1.2 Subject: Re: [PATCH] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 Content-Language: en-US To: Bo-Chen Chen , Krzysztof Kozlowski , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" Cc: =?UTF-8?B?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= , =?UTF-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?= , =?UTF-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?= , "chunkuang.hu@kernel.org" , "angelogioacchino.delregno@collabora.com" , "hsinyi@google.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , Project_Global_Chrome_Upstream_Group References: <20220825055658.12429-1-rex-bc.chen@mediatek.com> <3ff08ae9-a4b6-2b74-23cb-69ea1d7e1033@linaro.org> From: Matthias Brugger In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220825_035523_565329_2F5F310D X-CRM114-Status: GOOD ( 20.69 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 25/08/2022 08:59, Bo-Chen Chen wrote: > On Thu, 2022-08-25 at 14:11 +0800, Krzysztof Kozlowski wrote: >> On 25/08/2022 08:56, Bo-Chen Chen wrote: >>> From: "Jason-JH.Lin" >>> >>> For previous MediaTek SoCs, such as MT8173, there are 2 display HW >>> pipelines binding to 1 mmsys with the same power domain, the same >>> clock driver and the same mediatek-drm driver. >>> >>> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding >>> to >>> 2 different power domains, different clock drivers and different >>> mediatek-drm drivers. drop clock driver example here. >> >> I don't see binding to different clock drivers and anyway that's not >> really an argument here. Please focus in description on hardware >> properties, IOW, are devices compatible or different. What is the >> incompatible difference between VDOSYS0 and 1? >> >> Best regards, >> Krzysztof > > Hello Krzysztof, > > Thanks for yor review. > > From the functions perspective: > > Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, > GAMMA, DITHER. > They are related to PQ (Picture Quality) functions and they makes > VDOSYS0 supports PQ function while they are not including in VDOSYS1. > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > component). > It makes VDOSYS1 supports the HDR function while it's not including in > VDOSYS0. > Please include a description of this in the commit message. > About mediatek ETHDR, you can refer to this series: > > https://lore.kernel.org/all/20220819061456.8042-2-nancy.lin@mediatek.com/ > > To summary: > Only VDOSYS0 can support PQ adjustment. > Only VDOSYS1 can support HDR adjustment. > > Is this description ok for you? > If it is ok, I will put them into commit message in next version. > > BRs, > Bo-Chen >