* [PATCH v8 1/9] drm/mediatek: rename macros, add chip prefix
From: YT Shen @ 2016-09-12 12:01 UTC (permalink / raw)
To: dri-devel, Philipp Zabel
Cc: Daniel Vetter, Jie Qiu, Mao Huang, yingjoe.chen, Dan Carpenter,
Jitao Shi, linux-mediatek, Matthias Brugger, shaoming chen,
linux-arm-kernel, srv_heupstream, emil.l.velikov, linux-kernel,
Sascha Hauer, Maxime Ripard
In-Reply-To: <1473681672-47144-1-git-send-email-yt.shen@mediatek.com>
Add MT8173 prefix for hardware related macros.
Signed-off-by: YT Shen <yt.shen@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 60 +++++++++++++++++-----------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 17ba935..2fc4321 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -36,21 +36,21 @@
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
-#define MUTEX_MOD_DISP_OVL0 BIT(11)
-#define MUTEX_MOD_DISP_OVL1 BIT(12)
-#define MUTEX_MOD_DISP_RDMA0 BIT(13)
-#define MUTEX_MOD_DISP_RDMA1 BIT(14)
-#define MUTEX_MOD_DISP_RDMA2 BIT(15)
-#define MUTEX_MOD_DISP_WDMA0 BIT(16)
-#define MUTEX_MOD_DISP_WDMA1 BIT(17)
-#define MUTEX_MOD_DISP_COLOR0 BIT(18)
-#define MUTEX_MOD_DISP_COLOR1 BIT(19)
-#define MUTEX_MOD_DISP_AAL BIT(20)
-#define MUTEX_MOD_DISP_GAMMA BIT(21)
-#define MUTEX_MOD_DISP_UFOE BIT(22)
-#define MUTEX_MOD_DISP_PWM0 BIT(23)
-#define MUTEX_MOD_DISP_PWM1 BIT(24)
-#define MUTEX_MOD_DISP_OD BIT(25)
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
@@ -80,21 +80,21 @@ struct mtk_ddp {
};
static const unsigned int mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = MUTEX_MOD_DISP_AAL,
- [DDP_COMPONENT_COLOR0] = MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_COLOR1] = MUTEX_MOD_DISP_COLOR1,
- [DDP_COMPONENT_GAMMA] = MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OD] = MUTEX_MOD_DISP_OD,
- [DDP_COMPONENT_OVL0] = MUTEX_MOD_DISP_OVL0,
- [DDP_COMPONENT_OVL1] = MUTEX_MOD_DISP_OVL1,
- [DDP_COMPONENT_PWM0] = MUTEX_MOD_DISP_PWM0,
- [DDP_COMPONENT_PWM1] = MUTEX_MOD_DISP_PWM1,
- [DDP_COMPONENT_RDMA0] = MUTEX_MOD_DISP_RDMA0,
- [DDP_COMPONENT_RDMA1] = MUTEX_MOD_DISP_RDMA1,
- [DDP_COMPONENT_RDMA2] = MUTEX_MOD_DISP_RDMA2,
- [DDP_COMPONENT_UFOE] = MUTEX_MOD_DISP_UFOE,
- [DDP_COMPONENT_WDMA0] = MUTEX_MOD_DISP_WDMA0,
- [DDP_COMPONENT_WDMA1] = MUTEX_MOD_DISP_WDMA1,
+ [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
+ [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
+ [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
+ [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
+ [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
+ [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
--
1.9.1
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^ permalink raw reply related
* [PATCH v8 0/9] MT2701 DRM support
From: YT Shen @ 2016-09-12 12:01 UTC (permalink / raw)
To: dri-devel, Philipp Zabel
Cc: Daniel Vetter, Jie Qiu, Mao Huang, yingjoe.chen, Dan Carpenter,
Jitao Shi, linux-mediatek, Matthias Brugger, shaoming chen,
linux-arm-kernel, srv_heupstream, emil.l.velikov, linux-kernel,
Sascha Hauer, Maxime Ripard
This is MT2701 DRM support PATCH v8, based on 4.8-rc1.
We add DSI interrupt control, transfer function for MIPI DSI panel support.
Most codes are the same, except some register changed.
For example:
- DISP_OVL address offset changed, color format definition changed.
- DISP_RDMA fifo size changed.
- DISP_COLOR offset changed.
- MIPI_TX setting changed.
We add a new component DDP_COMPONENT_BLS, and the connections are updated.
OVL -> RDMA -> COLOR -> BLS -> DSI
RDMA -> DPI
And we have shadow register support in MT2701.
We remove dts patch from the patch series, which depends on MT2701 CCF and scpsys.
Changes since v7:
- Remove redundant codes
- Move the definition of DDP_COMPONENT_BLS to patch of "drm/mediatek: update display module connections"
- Move _dsi_irq_wait_queue into platform driver data
- Move mtk_dsi_irq_data_clear() to patch of "drm/mediatek: add dsi interrupt control"
- Add more descriptions in the commit messages
Changes since v6:
- Change data type of irq_data to u32
- Rewrite mtk_dsi_host_transfer() for simplify
- Move some MIPI_TX config to patch of "drm/mediatek: add *driver_data for different hardware settings".
- Remove device tree from this patch series
Changes since v5:
- Remove DPI device tree and compatible string
- Use one wait queue to handle interrupt status
- Update the interrupt check flow and DSI_INT_ALL_BITS
- Use same function for host read/write command
- various fixes
Changes since v4:
- Add messages when timeout in mtk_disp_mutex_acquire()
- Add descriptions for DISP_REG_MUTEX registers
- Move connection settings for display modules to a separate patch
- Remove 'mt2701-disp-wdma' because it is unused
- Move cleaning up and renaming to a separate patch
- Use wait_event_interruptible_timeout() to replace polling
- Remove irq_num from mtk_dsi structure
- Remove redundant and debug codes
Changes since v3:
- Add DSI support for MIPI DSI panels
- Update BLS binding to PWM nodes
- Remove ufoe device nodes
- Remove redundant parentheses
- Remove global variable initialization
Changes since v2:
- Rename mtk_ddp_mux_sel to mtk_ddp_sout_sel
- Update mt2701_mtk_ddp_ext components
- Changed to prefix naming
- Reorder the patch series
- Use of_device_get_match_data() to get driver private data
- Use iopoll macros to implement mtk_disp_mutex_acquire()
- Removed empty device tree nodes
Changes since v1:
- Removed BLS bindings and codes, which belong to pwm driver
- Moved mtk_disp_mutex_acquire() just before mtk_crtc_ddp_config()
- Split patch into smaller parts
- Added const keyword to constant structure
- Removed codes for special memory align
The PATCH depends on the following patch:
https://patchwork.kernel.org/patch/9289401/ ("dt-bindings: ARM: Mediatek: Document bindings for MT2701")
https://patchwork.kernel.org/patch/9222997/ ("dt-bindings: pwm: Add MediaTek display PWM bindings")
Thanks,
yt.shen
YT Shen (7):
drm/mediatek: rename macros, add chip prefix
drm/mediatek: add *driver_data for different hardware settings
drm/mediatek: add shadow register support
drm/mediatek: update display module connections
drm/mediatek: cleaning up and refine
drm/mediatek: update DSI sub driver flow
drm/mediatek: add support for Mediatek SoC MT2701
shaoming chen (2):
drm/mediatek: add dsi interrupt control
drm/mediatek: add dsi transfer function
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 ++-
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 17 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 +++--
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 138 ++++++---
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 34 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 54 +++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 429 ++++++++++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 70 +++--
11 files changed, 714 insertions(+), 161 deletions(-)
--
1.9.1
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^ permalink raw reply
* Re: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701
From: YT Shen @ 2016-09-12 10:16 UTC (permalink / raw)
To: CK Hu
Cc: Daniel Vetter, Jie Qiu, Mao Huang, yingjoe.chen, Dan Carpenter,
Jitao Shi, Sascha Hauer, linux-mediatek, dri-devel,
Matthias Brugger, shaoming chen, linux-arm-kernel, srv_heupstream,
emil.l.velikov, linux-kernel, Maxime Ripard
In-Reply-To: <1473226653.11736.33.camel@mtksdaap41>
Hi CK,
On Wed, 2016-09-07 at 13:37 +0800, CK Hu wrote:
> Hi, YT:
>
> On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > This patch add support for the Mediatek MT2701 DISP subsystem.
> > There is only one OVL engine in MT2701.
> >
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
>
> [snip...]
>
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 4b4e449..465819b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match {
> >
> > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL },
> > + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL },
>
> I think BLS is different than PWM, so this statement should be
>
> [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL };
The BLS module actually is a multifunction device, one of them is the
PWM function. We only upstream PWM function [1] now, and it is
accepted. When there are real use case (gamma function), we will update
this part. What do you think?
Regards,
yt.shen
[1] https://patchwork.kernel.org/patch/9223001/
>
>
> > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> > [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
>
> Regards,
> CK
>
>
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^ permalink raw reply
* Re: [PATCH v7 4/9] drm/mediatek: update display module connections
From: YT Shen @ 2016-09-12 10:16 UTC (permalink / raw)
To: CK Hu
Cc: Daniel Vetter, Jie Qiu, Mao Huang, yingjoe.chen, Dan Carpenter,
Jitao Shi, Sascha Hauer, linux-mediatek, dri-devel,
Matthias Brugger, shaoming chen, linux-arm-kernel, srv_heupstream,
emil.l.velikov, linux-kernel, Maxime Ripard
In-Reply-To: <1473147546.11736.7.camel@mtksdaap41>
Hi CK,
On Tue, 2016-09-06 at 15:39 +0800, CK Hu wrote:
> Hi, YT:
>
> On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > update connections for OVL, RDMA, BLS, DSI
> >
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
>
> [snip...]
>
> > @@ -111,6 +119,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > value = OVL0_MOUT_EN_COLOR0;
> > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > + value = OVL_MOUT_EN_RDMA;
> > } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
> > *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD_MOUT_EN_RDMA0;
> > @@ -148,6 +159,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > value = COLOR1_SEL_IN_OVL1;
> > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>
> DDP_COMPONENT_BLS is a new symbol which is defined in 9th patch of this
> series. I think the definition of DDP_COMPONENT_BLS should be in front
> of this patch.
OK, we will move the definition to this patch.
Regards,
yt.shen
>
> > + *addr = DISP_REG_CONFIG_DSI_SEL;
> > + value = DSI_SEL_IN_BLS;
> > } else {
> > value = 0;
> > }
> > @@ -155,6 +169,15 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > return value;
> > }
> >
>
> Regards,
> CK
>
>
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^ permalink raw reply
* Re: [PATCH v7 7/9] drm/mediatek: add dsi transfer function
From: YT Shen @ 2016-09-12 10:16 UTC (permalink / raw)
To: CK Hu
Cc: Daniel Vetter, Jie Qiu, Mao Huang, yingjoe.chen, Dan Carpenter,
Jitao Shi, Sascha Hauer, linux-mediatek, dri-devel,
Matthias Brugger, shaoming chen, linux-arm-kernel, srv_heupstream,
emil.l.velikov, linux-kernel, Maxime Ripard
In-Reply-To: <1473215632.11736.21.camel@mtksdaap41>
Hi CK,
On Wed, 2016-09-07 at 10:33 +0800, CK Hu wrote:
> Hi, YT:
>
> On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > From: shaoming chen <shaoming.chen@mediatek.com>
> >
> > add dsi read/write commands for transfer function
> >
> > Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 188 +++++++++++++++++++++++++++++++++++++
> > 1 file changed, 188 insertions(+)
> >
>
> [snip...]
>
> >
> > +static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
> > +{
> > + dsi->irq_data &= ~irq_bit;
> > +}
> > +
>
> [snip...]
>
> > +
> > +static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
> > + unsigned int timeout)
> > +{
> > + s32 ret = 0;
> > + unsigned long jiffies = msecs_to_jiffies(timeout);
> > +
> > + ret = wait_event_interruptible_timeout(_dsi_irq_wait_queue,
> > + dsi->irq_data & irq_flag,
> > + jiffies);
> > + if (ret == 0) {
> > + dev_info(dsi->dev, "Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
> > +
> > + mtk_dsi_enable(dsi);
> > + mtk_dsi_reset_engine(dsi);
> > + }
> > +
> > + return ret;
> > +}
>
> I think mtk_dsi_irq_data_clear() and mtk_dsi_wait_for_irq_done() should
> be moved to the 6th patch [1] of this series because these two functions
> deal the irq control.
We will move mtk_dsi_irq_data_clear() to patch "drm/mediatek: add dsi
interrupt control" and put mtk_dsi_wait_for_irq_done() here, because it
is used in the transfer function.
Regards,
yt.shen
>
>
> [1] https://patchwork.kernel.org/patch/9310819/
>
>
> Regards,
> CK
>
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^ permalink raw reply
* Re: [PATCH v7 6/9] drm/mediatek: add dsi interrupt control
From: YT Shen @ 2016-09-12 10:16 UTC (permalink / raw)
To: CK Hu
Cc: Daniel Vetter, Jie Qiu, Mao Huang, yingjoe.chen, Dan Carpenter,
Jitao Shi, Sascha Hauer, linux-mediatek, dri-devel,
Matthias Brugger, shaoming chen, linux-arm-kernel, srv_heupstream,
emil.l.velikov, linux-kernel, Maxime Ripard
In-Reply-To: <1473212348.11736.16.camel@mtksdaap41>
Hi CK,
On Wed, 2016-09-07 at 09:39 +0800, CK Hu wrote:
> Hi, YT:
>
> On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > From: shaoming chen <shaoming.chen@mediatek.com>
> >
> > add dsi interrupt control
> >
> > Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 76 ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 76 insertions(+)
> >
>
> [snip...]
>
> >
> > +static wait_queue_head_t _dsi_irq_wait_queue;
>
> I think it's better to move this global variable into platform driver
> data. Maybe one day you have two dsi device and one global variable is
> not enough.
OK, we will move _dsi_irq_wait_queue into platform driver data.
>
> > +
>
> [snip...]
>
> > +
> > +static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
> > +{
> > + struct mtk_dsi *dsi = dev_id;
> > + u32 status, tmp;
> > + u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
> > +
> > + status = readl(dsi->regs + DSI_INTSTA);
>
> If you define as
>
> status = readl(dsi->regs + DSI_INTSTA) & flag;
>
> You can remove 'flag' in below statements and reduce code size.
Will do.
>
> > +
> > + if (status & flag) {
> > + do {
> > + mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
> > + tmp = readl(dsi->regs + DSI_INTSTA);
> > + } while (tmp & DSI_BUSY);
> > +
> > + mtk_dsi_mask(dsi, DSI_INTSTA, status & flag, 0);
> > + mtk_dsi_irq_data_set(dsi, status & flag);
> > + wake_up_interruptible(&_dsi_irq_wait_queue);
> > + }
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
>
> [snip...]
>
> >
> > @@ -869,8 +926,27 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> > return ret;
> > }
> >
> > + irq_num = platform_get_irq(pdev, 0);
> > + if (irq_num < 0) {
> > + dev_err(&pdev->dev, "failed to request dsi irq resource\n");
> > + return -EPROBE_DEFER;
> > + }
> > +
> > + irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
> > + ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
> > + IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
> > + return -EPROBE_DEFER;
> > + }
> > +
> > + dsi->irq_data = 0;
>
> You use devm_kzalloc() to allocate 'dsi', so this statement is
> redundant.
Will remove.
Regards,
yt.shen
>
> > + dev_info(dev, "dsi irq num is 0x%x\n", irq_num);
> > +
> > platform_set_drvdata(pdev, dsi);
> >
> > + init_waitqueue_head(&_dsi_irq_wait_queue);
> > +
> > return component_add(&pdev->dev, &mtk_dsi_component_ops);
> > }
>
>
> Regards,
> CK
>
>
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^ permalink raw reply
* Re: [PATCH v7 8/9] drm/mediatek: update DSI sub driver flow
From: YT Shen @ 2016-09-12 10:15 UTC (permalink / raw)
To: CK Hu
Cc: dri-devel, Philipp Zabel, David Airlie, Matthias Brugger,
Daniel Kurtz, Mao Huang, Bibby Hsieh, Daniel Vetter,
Thierry Reding, Jie Qiu, Maxime Ripard, Chris Wilson,
shaoming chen, Jitao Shi, Boris Brezillon, Dan Carpenter,
linux-arm-kernel, linux-mediatek, linux-kernel
In-Reply-To: <1473224283.11736.27.camel@mtksdaap41>
Hi CK,
On Wed, 2016-09-07 at 12:58 +0800, CK Hu wrote:
> Hi, YT:
>
> On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > This patch update enable/disable flow of DSI module and MIPI TX module
> >
> > Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
>
> I think the description is too simple. Please briefly describe WHY of
> this patch. The original enable/disable flow is workable, so why do you
> need this patch? Without this patch, what problem would happen?
Got it, we will update more descriptions in the next version.
There is no transfer/interrupt function in the upstream DSI driver.
We also implement the following function [1][2] in this patch series.
Original flow works on there is a bridge chip: DSI -> bridge -> panel.
In this case: DSI -> panel, the DSI sub driver flow should be updated.
We need to initialize DSI first so that we can send commands to panel.
[1] https://patchwork.kernel.org/patch/9310819/
drm/mediatek: add dsi interrupt control
[2] https://patchwork.kernel.org/patch/9310823/
drm/mediatek: add dsi transfer function
>
> Regards,
> CK
>
>
^ permalink raw reply
* Re: [PATCH 1/4] Document: DT: Add bindings for mediatek MT6797 SoC Platform
From: Marc Zyngier @ 2016-09-12 7:57 UTC (permalink / raw)
To: Mars Cheng
Cc: Matthias Brugger, Rob Herring, Mark Rutland, Michael Turquette,
Stephen Boyd, Erin Lo, James Liao,
linux-clk-u79uwXL29TY76Z2rM5mHXA, CC Hwang, Loda Choui,
Miles Chen, Scott Shu, Jades Shih, Yingjoe Chen, My Chuang,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <1473645103.27628.6.camel@mtkswgap22>
On 12/09/16 02:51, Mars Cheng wrote:
> On Thu, 2016-09-08 at 15:32 +0100, Marc Zyngier wrote:
>> On 08/09/16 15:08, Mars Cheng wrote:
>>> Hi Marc
>>>
>>> Thanks for your review. the response inlined.
>>>
>>> On Thu, 2016-09-08 at 13:37 +0100, Marc Zyngier wrote:
>>>> On 08/09/16 11:49, Mars Cheng wrote:
>>>>> This adds DT binding documentation for Mediatek MT6797.
>>>>>
>>>>> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>>>>> ---
>>> [...]
>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
>>>>> index 9d1d72c..3d97eb4 100644
>>>>> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
>>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
>>>>> @@ -8,6 +8,7 @@ Required properties:
>>>>> "mediatek,mt8173-sysirq"
>>>>> "mediatek,mt8135-sysirq"
>>>>> "mediatek,mt8127-sysirq"
>>>>> + "mediatek,mt6797-sysirq"
>>>>> "mediatek,mt6795-sysirq"
>>>>> "mediatek,mt6755-sysirq"
>>>>> "mediatek,mt6592-sysirq"
>>>>> @@ -21,7 +22,8 @@ Required properties:
>>>>> - interrupt-parent: phandle of irq parent for sysirq. The parent must
>>>>> use the same interrupt-cells format as GIC.
>>>>> - reg: Physical base address of the intpol registers and length of memory
>>>>> - mapped region.
>>>>> + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg,
>>>>> + others need 1.
>>>>
>>>> Two things:
>>>>
>>>> - Please make this a separate patch that can be reviewed independently
>>>> of the rest of the changes, which are just adding new compatible
>>>> identifiers.
>>>
>>> Will fix this in the next patch set.
>>>
>>>>
>>>> - Why can't you simply expose it as a separate controller? Looking at
>>>> the way you're changing the corresponding driver, it looks like you're
>>>> simply adding an extra base/size. If you simply had a base for the
>>>> corresponding GIC interrupts, you could handle as many region as you
>>>> want, and have a more generic driver.
>>>>
>>>
>>> May I know the meaning of "simply expose it as a separate controller"?
>>
>> At the moment, you have something like this:
>>
>> sysirq: intpol-controller@10200620 {
>> compatible = "mediatek,mt6755-sysirq",
>> "mediatek,mt6577-sysirq";
>> interrupt-controller;
>> #interrupt-cells = <3>;
>> interrupt-parent = <&gic>;
>> reg = <0 0x10200620 0 0x20>;
>> };
>>
>> I suggest that, when you have a second base (which is effectively
>> another controller), you add:
>>
>> sysirq2: intpol-controller@10201620 {
>> compatible = "mediatek,mt6755-sysirq",
>> "mediatek,mt6577-sysirq";
>> interrupt-controller;
>> #interrupt-cells = <3>;
>> interrupt-parent = <&gic>;
>> irq-base = <32>;
>> reg = <0 0x10201620 0 0x20>;
>> };
>>
>> Where irq-base is the first SPI this is connected to (the lack of
>> property indicates implies that irq-base is 0). This becomes a very
>> simple change in the driver.
>>
>>> Or you might like to suggest me any similar driver as a reference? I
>>> will examine it. Current design is based on the fact: We expect
>>> irq-mtk-sysirq needs the optional second base but the third one will not
>>> happen.
>>>
>>> If we really need more than 2 bases, we can figure out a more generic
>>> driver at the time, right?
>>
>> I'd rather fix the driver and the binding to do the right thing once and
>> for all. In my experience, you will need to add a third base in six
>> months, and a fourth soon after. I'd rather either support an arbitrary
>> number of bases, or a single one per controller (and have multiple
>> controllers).
> Hi Marc
>
> Thanks for suggesting this approach I never thought.
>
> However, I will modify the irq-mtk-sysirq driver to handle as many bases
> as we specify in current node in the next patch set. Will not use the
> second interrupt node in DT. The main reason is to simplify the writing
> of DT. Or we need to know which interrupt node to be specified for other
> nodes. As you said that might be the third or fourth bases, that will
> complicate the writing of DT more.
>
> Would you think this is OK?
There is still one thing that is not completely obvious to me: How do
you map a new set of registers to the corresponding base GIC SPI?
At the moment, this is an implicit SPI0 (hwirq 32 on the GIC). I don't
think assuming that all the banks will forever be contiguous is a safe
bet, so introducing some form of sparseness support seems beneficial.
As for simplifying the DT, I'm not convinced either. You already deal
with two interrupt controllers (the GIC and this intpol), which means
you need to locally annotate some DT nodes to point to the GIC. With my
scheme, you keep annotating more (or use the extended interrupt
specifier notation), but that doesn't feel like a massive burden. How
often do you write a DT from scratch?
Anyway, this is up to you. My only requirements is about being able to
support an arbitrary numbers of register sets, with arbitrary SPI bases.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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^ permalink raw reply
* Re: [PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
From: CK Hu @ 2016-09-12 3:15 UTC (permalink / raw)
To: Bibby Hsieh
Cc: Junzhi Zhao, linux-kernel, Sascha Hauer, Daniel Vetter,
Cawa Cheng, dri-devel, Mao Huang, linux-mediatek,
Matthias Brugger, Yingjoe Chen, linux-arm-kernel
In-Reply-To: <1471417088-2993-4-git-send-email-bibby.hsieh@mediatek.com>
Hi, Bibby:
Sorry for the late reply.
On Wed, 2016-08-17 at 14:58 +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao <junzhi.zhao@mediatek.com>
>
> Pixel clock should be 297MHz when resolution is 4K.
>
From the code you modified, I think title should be: "Enlarge pll_rate
range from (<original lower bound>, <original upper bound>) to (<new
lower bound>, <new upper bound>)"
In description, you can explain the pll_rate for 4K and this enlargement
could support more resolution include 4K (Not only 4K).
> Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 0186e50..90fb831 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> unsigned long pll_rate;
> unsigned int factor;
>
> + /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
> pix_rate = 1000UL * mode->clock;
> - if (mode->clock <= 74000)
> + if (mode->clock <= 27000)
> + factor = 16 * 3;
> + else if (mode->clock <= 84000)
> factor = 8 * 3;
> - else
> + else if (mode->clock <= 167000)
> factor = 4 * 3;
> + else
> + factor = 2 * 3;
> pll_rate = pix_rate * factor;
>
> dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
Regards,
CK
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH 4/4] clk: mediatek: Add MT6797 clock support
From: Mars Cheng @ 2016-09-12 2:10 UTC (permalink / raw)
To: Stephen Boyd
Cc: Matthias Brugger, Rob Herring, Marc Zyngier, Mark Rutland,
Michael Turquette, Erin Lo, James Liao, linux-clk, CC Hwang,
Loda Choui, Miles Chen, Scott Shu, Jades Shih, Yingjoe Chen,
My Chuang, linux-kernel, linux-mediatek, devicetree, wsd_upstream
In-Reply-To: <81301905-0feb-06c1-8fbf-7424338e7f34@codeaurora.org>
Hi Stephen
Thanks for your review. Response inlined.
On Thu, 2016-09-08 at 12:50 -0700, Stephen Boyd wrote:
> On 09/08/2016 03:49 AM, Mars Cheng wrote:
> > Add MT6797 clock support, include topckgen, apmixedsys,
> > infracfg and subsystem clocks.
> >
> > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt6797.dtsi | 66 ++-
>
> Please don't combine dts and clk driver changes together. We generally
> don't take dts changes through clk tree.
OK, will separate clk driver in single submit next time.
>
> > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > index 5aa6204..ce91ecb 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -56,6 +56,42 @@ config COMMON_CLK_MT2701_BDPSYS
> > ---help---
> > This driver supports Mediatek MT2701 bdpsys clocks.
> >
>
> What tree is this based on?
Also 4.8-rc1, will base on clk-next to sent the patch.
>
> > +config COMMON_CLK_MT6797
> > + bool "Clock driver for Mediatek MT6797"
> > + depends on COMMON_CLK
>
> This sort of depends shouldn't be necessary.
>
Got it. Will fix like this:
+config COMMON_CLK_MT6797
+ bool "Clock driver for Mediatek MT6797"
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ ---help---
+ This driver supports Mediatek MT6797 basic clocks.
> > + select COMMON_CLK_MEDIATEK
> > + default ARCH_MEDIATEK
> > + ---help---
> > + This driver supports Mediatek MT6797 basic clocks.
> > +
> >
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/clk-mt6797-img.c
> > new file mode 100644
> > index 0000000..4ecd201
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797-img.c
> > @@ -0,0 +1,87 @@
> > +/* Copyright (c) 2016 MediaTek Inc.
> > + * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
>
> clk-provider.h?
Sure. Will fix it.
>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mt6797-clk.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +static const struct mtk_gate_regs img_cg_regs = {
> > + .set_ofs = 0x0004,
> > + .clr_ofs = 0x0008,
> > + .sta_ofs = 0x0000,
> > +};
> > +
> > +#define GATE_IMG(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &img_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > + }
> > +
> > +static const struct mtk_gate img_clks[] = {
> > + GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
> > + GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
> > + GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
> > + GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
> > +};
> > +
> > +static int mtk_imgsys_init(struct device *dev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
> > + if (!clk_data) {
> > + pr_err("%s: alloc failed\n", __func__);
>
> Allocations already print a big error message so this is useless.
OK, will just return error code.
>
> > + goto alloc_err;
> > + }
> > +
> > + mtk_clk_register_gates(dev->of_node, img_clks, ARRAY_SIZE(img_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
> > + clk_data);
> > + if (r)
> > + pr_err("%s: could not register clock provider: %d\n",
> > + __func__, r);
> > +
> > + return r;
> > +
> > +alloc_err:
> > + return -ENOMEM;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt6797_img[] = {
> > + { .compatible = "mediatek,mt6797-imgsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt6797_img_probe(struct platform_device *pdev)
> > +{
> > + return mtk_imgsys_init(&pdev->dev);
> > +}
> > +
> > +static struct platform_driver clk_mt6797_img_drv = {
> > + .probe = clk_mt6797_img_probe,
> > + .driver = {
> > + .name = "clk-mt6797-img",
> > + .of_match_table = of_match_clk_mt6797_img,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt6797_img_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/clk-mt6797-mm.c
> > new file mode 100644
> > index 0000000..77f0342
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797-mm.c
> > @@ -0,0 +1,146 @@
> > +/*
> > + * Copyright (c) 2016 MediaTek Inc.
> > + * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
>
> clk-provider.h?
Will fix it.
>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mt6797-clk.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +static const struct mtk_gate_regs mm0_cg_regs = {
> > + .set_ofs = 0x0104,
> > + .clr_ofs = 0x0108,
> > + .sta_ofs = 0x0100,
> > +};
> > +
> > +static const struct mtk_gate_regs mm1_cg_regs = {
> > + .set_ofs = 0x0114,
> > + .clr_ofs = 0x0118,
> > + .sta_ofs = 0x0110,
> > +};
> > +
> > +#define GATE_MM0(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &mm0_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > +}
> > +
> > +#define GATE_MM1(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &mm1_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > +}
> > +
> > +static const struct mtk_gate mm_clks[] = {
> > + GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
> > + GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
> > + GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),
> > + GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),
> > + GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
> > + GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),
> > + GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
> > + GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
> > + GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
> > + GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
> > + GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),
> > + GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
> > + GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
> > + GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
> > + GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
> > + GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
> > + GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),
> > + GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
> > + GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),
> > + GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
> > + GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),
> > + GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
> > + GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
> > + GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),
> > + GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),
> > + GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
> > + GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
> > + GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),
> > + GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),
> > + GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),
> > + GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),
> > + GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
> > + GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),
> > + GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),
> > + GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),
> > + GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",
> > + "dpi0_sel", 5),
> > + GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",
> > + "mm_sel", 6),
> > + GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",
> > + "mjc_sel", 7),
> > + GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",
> > + "mm_sel", 8),
> > + GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),
> > + GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",
> > + "clk26m", 1),
> > + GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",
> > + "clk26m", 3),
> > +};
> > +
> > +static void mtk_mmsys_init(struct device *dev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_MM_NR);
> > + if (!clk_data) {
> > + pr_err("%s: alloc failed\n", __func__);
>
> Copy pasta!
Will use a macro to simplify these similar code.
>
> > + goto alloc_err;
> > + }
> > +
> > + mtk_clk_register_gates(dev->of_node, mm_clks, ARRAY_SIZE(mm_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > + if (r)
> > + pr_err("%s: could not register clock provider: %d\n",
> > + __func__, r);
> > +
> > + return r;
> > +
> > +alloc_err:
> > + return -ENOMEM;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt6797_mm[] = {
> > + { .compatible = "mediatek,mt6797-mmsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt6797_mm_probe(struct platform_device *pdev)
> > +{
> > + return mtk_mmsys_init(&pdev->dev);
> > +}
> > +
> > +static struct platform_driver clk_mt6797_mm_drv = {
> > + .probe = clk_mt6797_mm_probe,
> > + .driver = {
> > + .name = "clk-mt6797-mm",
> > + .of_match_table = of_match_clk_mt6797_mm,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt6797_mm_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/clk-mt6797-vdec.c
> > new file mode 100644
> > index 0000000..48cba6b
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c
> > @@ -0,0 +1,102 @@
> > +/*
> > + * Copyright (c) 2016 MediaTek Inc.
> > + * Author: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
>
> The pattern has emerged.
Will fix it as the above.
>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt6797-clk.h>
> > +
> > +static const struct mtk_gate_regs vdec0_cg_regs = {
> > + .set_ofs = 0x0000,
> > + .clr_ofs = 0x0004,
> > + .sta_ofs = 0x0000,
> > +};
> > +
> > +static const struct mtk_gate_regs vdec1_cg_regs = {
> > + .set_ofs = 0x0008,
> > + .clr_ofs = 0x000c,
> > + .sta_ofs = 0x0008,
> > +};
> > +
> > +#define GATE_VDEC0(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &vdec0_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr_inv, \
> > +}
> > +
> > +#define GATE_VDEC1(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &vdec1_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr_inv, \
> > +}
> > +
> > +static const struct mtk_gate vdec_clks[] = {
> > + GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),
> > + GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
> > + GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
> > + GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),
> > +};
> > +
> > +static void mtk_vdecsys_init(struct device *dev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
> > + if (!clk_data) {
> > + pr_err("%s: alloc failed\n", __func__);
>
> Can't we consolidate this stuff?
>
Same as the above. Will use a macro to simplify it.
> > + goto alloc_err;
> > + }
> > +
> > + mtk_clk_register_gates(dev->of_node, vdec_clks, ARRAY_SIZE(vdec_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, clk_data);
> > + if (r)
> > + pr_err("%s: could not register clock provider: %d\n",
> > + __func__, r);
> > + return r;
> > +
> > +alloc_err:
> > + return -ENOMEM;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt6797_vdec[] = {
> > + { .compatible = "mediatek,mt6797-vdecsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt6797_vdec_probe(struct platform_device *pdev)
> > +{
> > + return mtk_vdecsys_init(&pdev->dev);
> > +}
> > +
> > +static struct platform_driver clk_mt6797_vdec_drv = {
> > + .probe = clk_mt6797_vdec_probe,
> > + .driver = {
> > + .name = "clk-mt6797-vdec",
> > + .of_match_table = of_match_clk_mt6797_vdec,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt6797_vdec_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/clk-mt6797-venc.c
> > new file mode 100644
> > index 0000000..787e010
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797-venc.c
> > @@ -0,0 +1,86 @@
> > +/*
> > + * Copyright (c) 2016 MediaTek Inc.
> > + * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
>
> Sigh.
>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt6797-clk.h>
> > +
> > +static const struct mtk_gate_regs venc_cg_regs = {
> > + .set_ofs = 0x0004,
> > + .clr_ofs = 0x0008,
> > + .sta_ofs = 0x0000,
> > +};
> > +
> > +#define GATE_VENC(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &venc_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr_inv, \
> > + }
> > +
> > +static const struct mtk_gate venc_clks[] = {
> > + GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0),
> > + GATE_VENC(CLK_VENC_1, "venc_1", "venc_sel", 4),
> > + GATE_VENC(CLK_VENC_2, "venc_2", "venc_sel", 8),
> > + GATE_VENC(CLK_VENC_3, "venc_3", "venc_sel", 12),
> > +};
> > +
> > +static void mtk_vencsys_init(struct device_node *node)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_VENC_NR);
> > + if (!clk_data) {
> > + pr_err("%s: alloc failed\n", __func__);
> > + goto alloc_err;
> > + }
> > +
> > + mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > + if (r)
> > + pr_err("%s: could not register clock provider: %d\n",
> > + __func__, r);
> > + return r;
> > +alloc_err:
> > + return -ENOMEM;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt6797_venc[] = {
> > + { .compatible = "mediatek,mt6797-vencsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt6797_venc_probe(struct platform_device *pdev)
> > +{
> > + return mtk_vencsys_init(pdev->dev.of_node);
> > +}
> > +
> > +static struct platform_driver clk_mt6797_venc_drv = {
> > + .probe = clk_mt6797_venc_probe,
> > + .driver = {
> > + .name = "clk-mt6797-venc",
> > + .of_match_table = of_match_clk_mt6797_venc,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt6797_venc_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
> > new file mode 100644
> > index 0000000..a851d0f
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797.c
> > @@ -0,0 +1,716 @@
> > +/*
> > + * Copyright (c) 2016 MediaTek Inc.
> > + * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
>
> Used?
Sould ne clk-provider.h too.
>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt6797-clk.h>
> > +
> > +/*
> > + * For some clocks, we don't care what their actual rates are. And these
> > + * clocks may change their rate on different products or different scenarios.
> > + * So we model these clocks' rate as 0, to denote it's not an actual rate.
> > + */
> > +
> > +static DEFINE_SPINLOCK(mt6797_clk_lock);
> > +
> > +static const struct mtk_fixed_factor top_divs[] = {
> > + FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
> > + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
> > + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
> > + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
> > + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
> > + FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
> > + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
> > + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
> > + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
> > + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
> > + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
> > + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
> > + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
> > + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
> > + FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
> > + FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
> > + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
> > + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
> > + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
> > + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
> > + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
> > + FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
> > + FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
> > + FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
> > + FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
> > + FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
> > + FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
> > + FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
> > + FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
> > + FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
> > + FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
> > + FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
> > + FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
> > + FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
> > + FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
> > + FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
> > + FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
> > + FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
> > + FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
> > + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
> > + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
> > + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
> > + FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
> > + FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
> > + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
> > + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
> > + FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
> > +};
> > +
> > +static const char * const axi_parents[] = {
> > + "clk26m",
> > + "syspll_d7",
> > + "ulposc_axi_ck_mux",
> > +};
> > +
> > +static const char * const ulposc_axi_ck_mux_parents[] = {
> > + "syspll1_d4",
> > + "ulposc_axi_ck_mux_pre",
> > +};
> > +
> > +static const char * const ulposc_axi_ck_mux_pre_parents[] = {
> > + "ulposc_d2",
> > + "ulposc_d3",
> > +};
> > +
> > +static const char * const ddrphycfg_parents[] = {
> > + "clk26m",
> > + "syspll3_d2",
> > + "syspll2_d4",
> > + "syspll1_d8",
> > +};
> > +
> > +static const char * const mm_parents[] = {
> > + "clk26m",
> > + "imgpll_ck",
> > + "univpll1_d2",
> > + "syspll1_d2",
> > +};
> > +
> > +static const char * const pwm_parents[] = {
> > + "clk26m",
> > + "univpll2_d4",
> > + "ulposc_d2",
> > + "ulposc_d3",
> > + "ulposc_d8",
> > + "ulposc_d10",
> > + "ulposc_d4",
> > +};
> > +
> > +static const char * const vdec_parents[] = {
> > + "clk26m",
> > + "vdecpll_ck",
> > + "imgpll_ck",
> > + "syspll_d3",
> > + "univpll_d5",
> > + "clk26m",
> > + "clk26m",
> > +};
> > +
> > +static const char * const venc_parents[] = {
> > + "clk26m",
> > + "codecpll_ck",
> > + "syspll_d3",
> > +};
> > +
> > +static const char * const mfg_parents[] = {
> > + "clk26m",
> > + "mfgpll_ck",
> > + "syspll_d3",
> > + "univpll_d3",
> > +};
> > +
> > +static const char * const camtg[] = {
> > + "clk26m",
> > + "univpll_d26",
> > + "univpll2_d2",
> > +};
> > +
> > +static const char * const uart_parents[] = {
> > + "clk26m",
> > + "univpll2_d8",
> > +};
> > +
> > +static const char * const spi_parents[] = {
> > + "clk26m",
> > + "syspll3_d2",
> > + "syspll2_d4",
> > + "ulposc_spi_ck_mux",
> > +};
> > +
> > +static const char * const ulposc_spi_ck_mux_parents[] = {
> > + "ulposc_d2",
> > + "ulposc_d3",
> > +};
> > +
> > +static const char * const usb20_parents[] = {
> > + "clk26m",
> > + "univpll1_d8",
> > + "syspll4_d2",
> > +};
> > +
> > +static const char * const msdc50_0_hclk_parents[] = {
> > + "clk26m",
> > + "syspll1_d2",
> > + "syspll2_d2",
> > + "syspll4_d2",
> > +};
> > +
> > +static const char * const msdc50_0_parents[] = {
> > + "clk26m",
> > + "msdcpll",
> > + "syspll_d3",
> > + "univpll1_d4",
> > + "syspll2_d2",
> > + "syspll_d7",
> > + "msdcpll_d2",
> > + "univpll1_d2",
> > + "univpll_d3",
> > +};
> > +
> > +static const char * const msdc30_1_parents[] = {
> > + "clk26m",
> > + "univpll2_d2",
> > + "msdcpll_d2",
> > + "univpll1_d4",
> > + "syspll2_d2",
> > + "syspll_d7",
> > + "univpll_d7",
> > +};
> > +
> > +static const char * const msdc30_2_parents[] = {
> > + "clk26m",
> > + "univpll2_d8",
> > + "syspll2_d8",
> > + "syspll1_d8",
> > + "msdcpll_d8",
> > + "syspll3_d4",
> > + "univpll_d26",
> > +};
> > +
> > +static const char * const audio_parents[] = {
> > + "clk26m",
> > + "syspll3_d4",
> > + "syspll4_d4",
> > + "syspll1_d16",
> > +};
> > +
> > +static const char * const aud_intbus_parents[] = {
> > + "clk26m",
> > + "syspll1_d4",
> > + "syspll4_d2",
> > +};
> > +
> > +static const char * const pmicspi_parents[] = {
> > + "clk26m",
> > + "univpll_d26",
> > + "syspll3_d4",
> > + "syspll1_d8",
> > + "ulposc_d4",
> > + "ulposc_d8",
> > + "syspll2_d8",
> > +};
> > +
> > +static const char * const scp_parents[] = {
> > + "clk26m",
> > + "syspll_d3",
> > + "ulposc_ck",
> > + "univpll_d5",
> > +};
> > +
> > +static const char * const atb_parents[] = {
> > + "clk26m",
> > + "syspll1_d2",
> > + "syspll_d5",
> > +};
> > +
> > +static const char * const mjc_parents[] = {
> > + "clk26m",
> > + "imgpll_ck",
> > + "univpll_d5",
> > + "syspll1_d2",
> > +};
> > +
> > +static const char * const dpi0_parents[] = {
> > + "clk26m",
> > + "tvdpll_d2",
> > + "tvdpll_d4",
> > + "tvdpll_d8",
> > + "tvdpll_d16",
> > + "clk26m",
> > + "clk26m",
> > +};
> > +
> > +static const char * const aud_1_parents[] = {
> > + "clk26m",
> > + "apll1_ck",
> > +};
> > +
> > +static const char * const aud_2_parents[] = {
> > + "clk26m",
> > + "apll2_ck",
> > +};
> > +
> > +static const char * const ssusb_top_sys_parents[] = {
> > + "clk26m",
> > + "univpll3_d2",
> > +};
> > +
> > +static const char * const spm_parents[] = {
> > + "clk26m",
> > + "syspll1_d8",
> > +};
> > +
> > +static const char * const bsi_spi_parents[] = {
> > + "clk26m",
> > + "syspll_d3_d3",
> > + "syspll1_d4",
> > + "syspll_d7",
> > +};
> > +
> > +static const char * const audio_h_parents[] = {
> > + "clk26m",
> > + "apll2_ck",
> > + "apll1_ck",
> > + "univpll_d7",
> > +};
> > +
> > +static const char * const mfg_52m_parents[] = {
> > + "clk26m",
> > + "univpll2_d8",
> > + "univpll2_d4",
> > + "univpll2_d4",
> > +};
> > +
> > +static const char * const anc_md32_parents[] = {
> > + "clk26m",
> > + "syspll1_d2",
> > + "univpll_d5",
> > +};
> > +
> > +static const struct mtk_composite top_muxes[] = {
> > + MUX_GATE(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
> > + ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1,
> > + INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
> > + ulposc_axi_ck_mux_parents, 0x0040, 2, 1, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
> > + 0x0040, 0, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
> > + 0x0040, 16, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
> > + 0x0040, 24, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
> > + MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
> > + MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
> > + MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
> > + MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
> > + MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
> > + MUX_GATE(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
> > + ulposc_spi_ck_mux_parents, 0x0060, 18, 1,
> > + INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
> > + 0x0060, 24, 2, 31),
> > + MUX_GATE(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
> > + msdc50_0_hclk_parents, 0x0070, 8, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
> > + 0x0070, 16, 4, 23),
> > + MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
> > + 0x0070, 24, 3, 31),
> > + MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
> > + 0x0080, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
> > + 0x0080, 16, 2, 23),
> > + MUX_GATE(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
> > + 0x0080, 24, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
> > + 0x0090, 0, 3, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
> > + 0x0090, 8, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
> > + 0x0090, 16, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
> > + MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
> > + 0x00A0, 16, 1, 23),
> > + MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
> > + 0x00A0, 24, 1, 31),
> > + MUX_GATE(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
> > + ssusb_top_sys_parents, 0x00B0, 8, 1, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
> > + 0x00C0, 0, 1, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
> > + 0x00C0, 8, 2, INVALID_MUX_GATE_BIT),
> > + MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
> > + 0x00C0, 16, 2, 23),
> > + MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
> > + 0x00C0, 24, 2, 31),
> > + MUX_GATE(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
> > + 0x0104, 1, 2, INVALID_MUX_GATE_BIT),
> > +};
> > +
> > +static const struct mtk_gate_regs infra0_cg_regs = {
> > + .set_ofs = 0x0080,
> > + .clr_ofs = 0x0084,
> > + .sta_ofs = 0x0090,
> > +};
> > +
> > +static const struct mtk_gate_regs infra1_cg_regs = {
> > + .set_ofs = 0x0088,
> > + .clr_ofs = 0x008c,
> > + .sta_ofs = 0x0094,
> > +};
> > +
> > +static const struct mtk_gate_regs infra2_cg_regs = {
> > + .set_ofs = 0x00a8,
> > + .clr_ofs = 0x00ac,
> > + .sta_ofs = 0x00b0,
> > +};
> > +
> > +#define GATE_ICG0(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &infra0_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > +}
> > +
> > +#define GATE_ICG1(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &infra1_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > +}
> > +
> > +#define GATE_ICG2(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &infra2_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > +}
> > +
> > +static const struct mtk_gate infra_gates[] = {
> > + GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
> > + GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
> > + GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
> > + GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
> > + GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
> > + GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
> > + GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
> > + GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
> > + GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
> > + GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
> > + GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
> > + GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
> > + GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
> > + GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
> > + GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
> > + GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
> > + GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
> > + GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
> > + GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
> > + GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
> > + GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
> > + GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
> > + GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
> > + GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
> > + GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
> > + GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
> > + GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
> > + GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
> > + GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
> > + GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
> > + GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
> > + GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
> > + GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
> > + GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
> > + GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
> > + GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
> > + GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
> > + GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
> > + GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
> > + GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
> > + GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
> > + GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
> > + "axi_sel", 12),
> > + GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
> > + "axi_sel", 13),
> > + GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
> > + GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
> > + GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
> > + GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
> > + GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
> > + GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
> > + GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
> > + GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
> > + GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
> > + GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
> > + GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
> > + GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
> > + GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
> > + GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
> > + GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
> > + GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
> > + GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
> > + GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
> > + GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
> > + GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
> > + GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
> > + GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
> > + GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
> > + GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
> > + GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
> > + GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
> > + GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
> > + GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
> > + GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
> > + GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
> > + GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
> > + GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
> > + "ssusb_top_sys_sel", 24),
> > + GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
> > + GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
> > + GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
> > + "clk26m", 27),
> > + GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
> > + "axi_sel", 28),
> > + GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
> > + GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
> > + GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
> > + GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
> > +};
> > +
> > +static const struct mtk_fixed_factor infra_divs[] = {
> > + FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
> > +};
> > +
> > +#define MT6797_PLL_FMAX (3000UL * MHZ)
> > +
> > +#define CON0_MT6797_RST_BAR BIT(24)
> > +
> > +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
> > + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
> > + _pcw_shift, _div_table) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .reg = _reg, \
> > + .pwr_reg = _pwr_reg, \
> > + .en_mask = _en_mask, \
> > + .flags = _flags, \
> > + .rst_bar_mask = CON0_MT6797_RST_BAR, \
> > + .fmax = MT6797_PLL_FMAX, \
> > + .pcwbits = _pcwbits, \
> > + .pd_reg = _pd_reg, \
> > + .pd_shift = _pd_shift, \
> > + .tuner_reg = _tuner_reg, \
> > + .pcw_reg = _pcw_reg, \
> > + .pcw_shift = _pcw_shift, \
> > + .div_table = _div_table, \
> > +}
> > +
> > +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
> > + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
> > + _pcw_shift) \
> > + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
> > + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
> > + NULL)
> > +
> > +static const struct mtk_pll_data plls[] = {
> > + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, 0, 21,
> > + 0x220, 4, 0x0, 0x224, 0),
> > + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
> > + 0x230, 4, 0x0, 0x234, 14),
> > + PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
> > + 0x244, 24, 0x0, 0x244, 0),
> > + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
> > + 0x250, 4, 0x0, 0x254, 0),
> > + PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
> > + 0x260, 4, 0x0, 0x264, 0),
> > + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
> > + 0x270, 4, 0x0, 0x274, 0),
> > + PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
> > + 0x290, 4, 0x0, 0x294, 0),
> > + PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
> > + 0x2E4, 4, 0x0, 0x2E8, 0),
> > + PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
> > + 0x2A0, 4, 0x2A8, 0x2A4, 0),
> > + PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
> > + 0x2B4, 4, 0x2BC, 0x2B8, 0),
> > +};
> > +
> > +static struct clk_onecell_data * __init mtk_topckgen_init(struct device *dev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + struct resource mem;
> > + void __iomem *base;
> > +
> > + if (of_address_to_resource(dev->of_node, 0, &mem)) {
>
> Please use platform APIs instead of OF APIs.
>
Will fix it.
> > + pr_err("%s: get resource failed\n", __func__);
> > + goto res_err;
> > + }
> > +
> > + base = devm_ioremap(dev, mem.start, resource_size(&mem));
> > + if (!base) {
> > + pr_err("%s: ioremap failed\n", __func__);
> > + goto ioremap_err;
> > + }
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
> > + if (!clk_data) {
> > + pr_err("%s: alloc failed\n", __func__);
> > + goto alloc_err;
> > + }
> > +
> > + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
> > + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
> > + &mt6797_clk_lock, clk_data);
> > +
> > + return clk_data;
> > +
> > +alloc_err:
> > + devm_iounmap(dev, base);
> > +res_err:
> > +ioremap_err:
> > + return NULL;
> > +}
> > +
> > +static struct clk_onecell_data * __init mtk_infrasys_init(struct device *dev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > + if (!clk_data) {
> > + pr_err("%s: alloc failed\n", __func__);
> > + goto alloc_err;
> > + }
> > +
> > + mtk_clk_register_gates(dev->of_node, infra_gates,
> > + ARRAY_SIZE(infra_gates), clk_data);
> > + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
> > +
> > + return clk_data;
> > +
> > +alloc_err:
> > + return NULL;
> > +}
> > +
> > +static struct clk_onecell_data * __init mtk_apmixedsys_init(struct device *dev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
> > + if (!clk_data) {
> > + pr_err("%s: alloc failed\n", __func__);
> > + goto alloc_err;
> > + }
> > +
> > + mtk_clk_register_plls(dev->of_node, plls, ARRAY_SIZE(plls), clk_data);
> > +
> > + return clk_data;
> > +
> > +alloc_err:
> > + return NULL;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt6797[] = {
> > + {
> > + .compatible = "mediatek,mt6797-topckgen",
> > + .data = mtk_topckgen_init,
> > + }, {
> > + .compatible = "mediatek,mt6797-infracfg",
> > + .data = mtk_infrasys_init,
> > + }, {
> > + .compatible = "mediatek,mt6797-apmixedsys",
> > + .data = mtk_apmixedsys_init,
> > + }, {
> > + /* sentinel */
> > + }
> > +};
> > +
> > +static int clk_mt6797_probe(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data * (*clk_init)(struct device *);
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_init = of_device_get_match_data(&pdev->dev);
> > + if (!clk_init) {
> > + pr_err("%s: matched clk not found\n", __func__);
> > + return -EINVAL;
> > + }
> > +
> > + clk_data = clk_init(&pdev->dev);
> > + if (!clk_data) {
> > + pr_err("%s: clk init failed\n", __func__);
> > + return -EINVAL;
> > + }
> > +
> > + r = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
> > + clk_data);
> > + if (r) {
> > + pr_err("%s: could not register clock provider: %d\n",
> > + __func__, r);
> > + return r;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static struct platform_driver clk_mt6797_drv = {
> > + .probe = clk_mt6797_probe,
> > + .driver = {
> > + .name = "clk-mt6797",
> > + .owner = THIS_MODULE,
> > + .of_match_table = of_match_clk_mt6797,
> > + },
> > +};
> > +
> > +static int __init clk_mt6797_init(void)
> > +{
> > + return platform_driver_register(&clk_mt6797_drv);
> > +}
> > +
> > +arch_initcall(clk_mt6797_init);
> > diff --git a/include/dt-bindings/clock/mt6797-clk.h b/include/dt-bindings/clock/mt6797-clk.h
> > new file mode 100644
> > index 0000000..6f32e6b
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/mt6797-clk.h
> > @@ -0,0 +1,281 @@
> > +/*
> > +* Copyright (c) 2016 MediaTek Inc.
> > +* Author: Kevin Chen <kevin-cw.chen@mediatek.com>
> > +*
> > +* This program is free software; you can redistribute it and/or modify
> > +* it under the terms of the GNU General Public License version 2 as
> > +* published by the Free Software Foundation.
> > +*
> > +* This program is distributed in the hope that it will be useful,
> > +* but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > +* GNU General Public License for more details.
> > +*/
> > +
> > +#ifndef _DT_BINDINGS_CLK_MT6797_H
> > +#define _DT_BINDINGS_CLK_MT6797_H
> > +
> > +/* TOPCKGEN */
> > +#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1
> > +#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2
> > +#define CLK_TOP_MUX_AXI 3
> > +#define CLK_TOP_MUX_MEM 4
> > +#define CLK_TOP_MUX_DDRPHYCFG 5
> > +#define CLK_TOP_MUX_MM 6
> > +#define CLK_TOP_MUX_PWM 7
> > +#define CLK_TOP_MUX_VDEC 8
> > +#define CLK_TOP_MUX_VENC 9
> > +#define CLK_TOP_MUX_MFG 10
> > +#define CLK_TOP_MUX_CAMTG 11
> > +#define CLK_TOP_MUX_UART 12
> > +#define CLK_TOP_MUX_SPI 13
> > +#define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14
> > +#define CLK_TOP_MUX_USB20 15
> > +#define CLK_TOP_MUX_MSDC50_0_HCLK 16
> > +#define CLK_TOP_MUX_MSDC50_0 17
> > +#define CLK_TOP_MUX_MSDC30_1 18
> > +#define CLK_TOP_MUX_MSDC30_2 19
> > +#define CLK_TOP_MUX_AUDIO 20
> > +#define CLK_TOP_MUX_AUD_INTBUS 21
> > +#define CLK_TOP_MUX_PMICSPI 22
> > +#define CLK_TOP_MUX_SCP 23
> > +#define CLK_TOP_MUX_ATB 24
> > +#define CLK_TOP_MUX_MJC 25
> > +#define CLK_TOP_MUX_DPI0 26
> > +#define CLK_TOP_MUX_AUD_1 27
> > +#define CLK_TOP_MUX_AUD_2 28
> > +#define CLK_TOP_MUX_SSUSB_TOP_SYS 29
> > +#define CLK_TOP_MUX_SPM 30
> > +#define CLK_TOP_MUX_BSI_SPI 31
> > +#define CLK_TOP_MUX_AUDIO_H 32
> > +#define CLK_TOP_MUX_ANC_MD32 33
> > +#define CLK_TOP_MUX_MFG_52M 34
> > +#define CLK_TOP_SYSPLL_CK 35
> > +#define CLK_TOP_SYSPLL_D2 36
> > +#define CLK_TOP_SYSPLL1_D2 37
> > +#define CLK_TOP_SYSPLL1_D4 38
> > +#define CLK_TOP_SYSPLL1_D8 39
> > +#define CLK_TOP_SYSPLL1_D16 40
> > +#define CLK_TOP_SYSPLL_D3 41
> > +#define CLK_TOP_SYSPLL_D3_D3 42
> > +#define CLK_TOP_SYSPLL2_D2 43
> > +#define CLK_TOP_SYSPLL2_D4 44
> > +#define CLK_TOP_SYSPLL2_D8 45
> > +#define CLK_TOP_SYSPLL_D5 46
> > +#define CLK_TOP_SYSPLL3_D2 47
> > +#define CLK_TOP_SYSPLL3_D4 48
> > +#define CLK_TOP_SYSPLL_D7 49
> > +#define CLK_TOP_SYSPLL4_D2 50
> > +#define CLK_TOP_SYSPLL4_D4 51
> > +#define CLK_TOP_UNIVPLL_CK 52
> > +#define CLK_TOP_UNIVPLL_D7 53
> > +#define CLK_TOP_UNIVPLL_D26 54
> > +#define CLK_TOP_SSUSB_PHY_48M_CK 55
> > +#define CLK_TOP_USB_PHY48M_CK 56
> > +#define CLK_TOP_UNIVPLL_D2 57
> > +#define CLK_TOP_UNIVPLL1_D2 58
> > +#define CLK_TOP_UNIVPLL1_D4 59
> > +#define CLK_TOP_UNIVPLL1_D8 60
> > +#define CLK_TOP_UNIVPLL_D3 61
> > +#define CLK_TOP_UNIVPLL2_D2 62
> > +#define CLK_TOP_UNIVPLL2_D4 63
> > +#define CLK_TOP_UNIVPLL2_D8 64
> > +#define CLK_TOP_UNIVPLL_D5 65
> > +#define CLK_TOP_UNIVPLL3_D2 66
> > +#define CLK_TOP_UNIVPLL3_D4 67
> > +#define CLK_TOP_UNIVPLL3_D8 68Groundhog day?
> > +#define CLK_TOP_ULPOSC_CK_ORG 69
> > +#define CLK_TOP_ULPOSC_CK 70
> > +#define CLK_TOP_ULPOSC_D2 71
> > +#define CLK_TOP_ULPOSC_D3 72
> > +#define CLK_TOP_ULPOSC_D4 73
> > +#define CLK_TOP_ULPOSC_D8 74
> > +#define CLK_TOP_ULPOSC_D10 75
> > +#define CLK_TOP_APLL1_CK 76
> > +#define CLK_TOP_APLL2_CK 77
> > +#define CLK_TOP_MFGPLL_CK 78
> > +#define CLK_TOP_MFGPLL_D2 79
> > +#define CLK_TOP_IMGPLL_CK 80
> > +#define CLK_TOP_IMGPLL_D2 81
> > +#define CLK_TOP_IMGPLL_D4 82
> > +#define CLK_TOP_CODECPLL_CK 83
> > +#define CLK_TOP_CODECPLL_D2 84
> > +#define CLK_TOP_VDECPLL_CK 85
> > +#define CLK_TOP_TVDPLL_CK 86
> > +#define CLK_TOP_TVDPLL_D2 87
> > +#define CLK_TOP_TVDPLL_D4 88
> > +#define CLK_TOP_TVDPLL_D8 89
> > +#define CLK_TOP_TVDPLL_D16 90
> > +#define CLK_TOP_MSDCPLL_CK 91
> > +#define CLK_TOP_MSDCPLL_D2 92
> > +#define CLK_TOP_MSDCPLL_D4 93
> > +#define CLK_TOP_MSDCPLL_D8 94
> > +#define CLK_TOP_NR 95
> > +
> > +/* APMIXED_SYS */
> > +#define CLK_APMIXED_MAINPLL 1
> > +#define CLK_APMIXED_UNIVPLL 2
> > +#define CLK_APMIXED_MFGPLL 3
> > +#define CLK_APMIXED_MSDCPLL 4
> > +#define CLK_APMIXED_IMGPLL 5
> > +#define CLK_APMIXED_TVDPLL 6
> > +#define CLK_APMIXED_CODECPLL 7
> > +#define CLK_APMIXED_VDECPLL 8
> > +#define CLK_APMIXED_APLL1 9
> > +#define CLK_APMIXED_APLL2 10
> > +#define CLK_APMIXED_NR 11
> > +
> > +/* INFRA_SYS */
> > +#define CLK_INFRA_PMIC_TMR 1
> > +#define CLK_INFRA_PMIC_AP 2
> > +#define CLK_INFRA_PMIC_MD 3
> > +#define CLK_INFRA_PMIC_CONN 4
> > +#define CLK_INFRA_SCP 5
> > +#define CLK_INFRA_SEJ 6
> > +#define CLK_INFRA_APXGPT 7
> > +#define CLK_INFRA_SEJ_13M 8
> > +#define CLK_INFRA_ICUSB 9
> > +#define CLK_INFRA_GCE 10
> > +#define CLK_INFRA_THERM 11
> > +#define CLK_INFRA_I2C0 12
> > +#define CLK_INFRA_I2C1 13
> > +#define CLK_INFRA_I2C2 14
> > +#define CLK_INFRA_I2C3 15
> > +#define CLK_INFRA_PWM_HCLK 16
> > +#define CLK_INFRA_PWM1 17
> > +#define CLK_INFRA_PWM2 18
> > +#define CLK_INFRA_PWM3 19
> > +#define CLK_INFRA_PWM4 20
> > +#define CLK_INFRA_PWM 21
> > +#define CLK_INFRA_UART0 22
> > +#define CLK_INFRA_UART1 23
> > +#define CLK_INFRA_UART2 24
> > +#define CLK_INFRA_UART3 25
> > +#define CLK_INFRA_MD2MD_CCIF_0 26
> > +#define CLK_INFRA_MD2MD_CCIF_1 27
> > +#define CLK_INFRA_MD2MD_CCIF_2 28
> > +#define CLK_INFRA_FHCTL 29
> > +#define CLK_INFRA_BTIF 30
> > +#define CLK_INFRA_MD2MD_CCIF_3 31
> > +#define CLK_INFRA_SPI 32
> > +#define CLK_INFRA_MSDC0 33
> > +#define CLK_INFRA_MD2MD_CCIF_4 34
> > +#define CLK_INFRA_MSDC1 35
> > +#define CLK_INFRA_MSDC2 36
> > +#define CLK_INFRA_MD2MD_CCIF_5 37
> > +#define CLK_INFRA_GCPU 38
> > +#define CLK_INFRA_TRNG 39
> > +#define CLK_INFRA_AUXADC 40
> > +#define CLK_INFRA_CPUM 41
> > +#define CLK_INFRA_AP_C2K_CCIF_0 42
> > +#define CLK_INFRA_AP_C2K_CCIF_1 43
> > +#define CLK_INFRA_CLDMA 44
> > +#define CLK_INFRA_DISP_PWM 45
> > +#define CLK_INFRA_AP_DMA 46
> > +#define CLK_INFRA_DEVICE_APC 47
> > +#define CLK_INFRA_L2C_SRAM 48
> > +#define CLK_INFRA_CCIF_AP 49
> > +#define CLK_INFRA_AUDIO 50
> > +#define CLK_INFRA_CCIF_MD 51
> > +#define CLK_INFRA_DRAMC_F26M 52
> > +#define CLK_INFRA_I2C4 53
> > +#define CLK_INFRA_I2C_APPM 54
> > +#define CLK_INFRA_I2C_GPUPM 55
> > +#define CLK_INFRA_I2C2_IMM 56
> > +#define CLK_INFRA_I2C2_ARB 57
> > +#define CLK_INFRA_I2C3_IMM 58
> > +#define CLK_INFRA_I2C3_ARB 59
> > +#define CLK_INFRA_I2C5 60
> > +#define CLK_INFRA_SYS_CIRQ 61
> > +#define CLK_INFRA_SPI1 62
> > +#define CLK_INFRA_DRAMC_B_F26M 63
> > +#define CLK_INFRA_ANC_MD32 64
> > +#define CLK_INFRA_ANC_MD32_32K 65
> > +#define CLK_INFRA_DVFS_SPM1 66
> > +#define CLK_INFRA_AES_TOP0 67
> > +#define CLK_INFRA_AES_TOP1 68
> > +#define CLK_INFRA_SSUSB_BUS 69
> > +#define CLK_INFRA_SPI2 70
> > +#define CLK_INFRA_SPI3 71
> > +#define CLK_INFRA_SPI4 72
> > +#define CLK_INFRA_SPI5 73
> > +#define CLK_INFRA_IRTX 74
> > +#define CLK_INFRA_SSUSB_SYS 75
> > +#define CLK_INFRA_SSUSB_REF 76
> > +#define CLK_INFRA_AUDIO_26M 77
> > +#define CLK_INFRA_AUDIO_26M_PAD_TOP 78
> > +#define CLK_INFRA_MODEM_TEMP_SHARE 79
> > +#define CLK_INFRA_VAD_WRAP_SOC 80
> > +#define CLK_INFRA_DRAMC_CONF 81
> > +#define CLK_INFRA_DRAMC_B_CONF 82
> > +#define CLK_INFRA_MFG_VCG 83
> > +#define CLK_INFRA_13M 84
> > +#define CLK_INFRA_NR 85
>
> Weird spacing here?
>
Will fix it.
> > +
> > +/* IMG_SYS */
> > +#define CLK_IMG_FDVT 1
> > +#define CLK_IMG_DPE 2
> > +#define CLK_IMG_DIP 3
> > +#define CLK_IMG_LARB6 4
> > +#define CLK_IMG_NR 5
>
> Same here.
>
Will fix it.
> > +
> > +/* MM_SYS */
> > +#define CLK_MM_SMI_COMMON 1
> > +#define CLK_MM_SMI_LARB0 2
> > +#define CLK_MM_SMI_LARB5 3
> > +#define CLK_MM_CAM_MDP 4
> > +#define CLK_MM_MDP_RDMA0 5
> > +#define CLK_MM_MDP_RDMA1 6
> > +#define CLK_MM_MDP_RSZ0 7
> > +#define CLK_MM_MDP_RSZ1 8
> > +#define CLK_MM_MDP_RSZ2 9
> > +#define CLK_MM_MDP_TDSHP 10
> > +#define CLK_MM_MDP_COLOR 11
> > +#define CLK_MM_MDP_WDMA 12
> > +#define CLK_MM_MDP_WROT0 13
> > +#define CLK_MM_MDP_WROT1 14
> > +#define CLK_MM_FAKE_ENG 15
> > +#define CLK_MM_DISP_OVL0 16
> > +#define CLK_MM_DISP_OVL1 17
> > +#define CLK_MM_DISP_OVL0_2L 18
> > +#define CLK_MM_DISP_OVL1_2L 19
> > +#define CLK_MM_DISP_RDMA0 20
> > +#define CLK_MM_DISP_RDMA1 21
> > +#define CLK_MM_DISP_WDMA0 22
> > +#define CLK_MM_DISP_WDMA1 23
> > +#define CLK_MM_DISP_COLOR 24
> > +#define CLK_MM_DISP_CCORR 25
> > +#define CLK_MM_DISP_AAL 26
> > +#define CLK_MM_DISP_GAMMA 27Groundhog day?
> > +#define CLK_MM_DISP_OD 28
> > +#define CLK_MM_DISP_DITHER 29
> > +#define CLK_MM_DISP_UFOE 30
> > +#define CLK_MM_DISP_DSC 31
> > +#define CLK_MM_DISP_SPLIT 32
> > +#define CLK_MM_DSI0_MM_CLOCK 33
> > +#define CLK_MM_DSI1_MM_CLOCK 34
> > +#define CLK_MM_DPI_MM_CLOCK 35
> > +#define CLK_MM_DPI_INTERFACE_CLOCK 36
> > +#define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37
> > +#define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38
> > +#define CLK_MM_DISP_OVL0_MOUT_CLOCK 39
> > +#define CLK_MM_FAKE_ENG2 40
> > +#define CLK_MM_DSI0_INTERFACE_CLOCK 41
> > +#define CLK_MM_DSI1_INTERFACE_CLOCK 42
> > +#define CLK_MM_NR 43
>
> Ditto.
>
> > +
> > +/* VDEC_SYS */
> > +#define CLK_VDEC_CKEN_ENG 1
> > +#define CLK_VDEC_ACTIVE 2
> > +#define CLK_VDEC_CKEN 3
> > +#define CLK_VDEC_LARB1_CKEN 4
> > +#define CLK_VDEC_NR 5
>
> Another one
>
> > +
> > +/* VENC_SYS */
> > +#define CLK_VENC_0 1
> > +#define CLK_VENC_1 2
> > +#define CLK_VENC_2 3
> > +#define CLK_VENC_3 4
> > +#define CLK_VENC_NR 5
> >
>
> Again.
>
Will fix the space issue.
Thanks a lot.
^ permalink raw reply
* Re: [PATCH 1/4] Document: DT: Add bindings for mediatek MT6797 SoC Platform
From: Mars Cheng @ 2016-09-12 1:51 UTC (permalink / raw)
To: Marc Zyngier
Cc: Matthias Brugger, Rob Herring, Mark Rutland, Michael Turquette,
Stephen Boyd, Erin Lo, James Liao,
linux-clk-u79uwXL29TY76Z2rM5mHXA, CC Hwang, Loda Choui,
Miles Chen, Scott Shu, Jades Shih, Yingjoe Chen, My Chuang,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
wsd_upstream-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <57D17667.1020201-5wv7dgnIgG8@public.gmane.org>
On Thu, 2016-09-08 at 15:32 +0100, Marc Zyngier wrote:
> On 08/09/16 15:08, Mars Cheng wrote:
> > Hi Marc
> >
> > Thanks for your review. the response inlined.
> >
> > On Thu, 2016-09-08 at 13:37 +0100, Marc Zyngier wrote:
> >> On 08/09/16 11:49, Mars Cheng wrote:
> >>> This adds DT binding documentation for Mediatek MT6797.
> >>>
> >>> Signed-off-by: Mars Cheng <mars.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >>> ---
> > [...]
> >>
> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> >>> index 9d1d72c..3d97eb4 100644
> >>> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> >>> @@ -8,6 +8,7 @@ Required properties:
> >>> "mediatek,mt8173-sysirq"
> >>> "mediatek,mt8135-sysirq"
> >>> "mediatek,mt8127-sysirq"
> >>> + "mediatek,mt6797-sysirq"
> >>> "mediatek,mt6795-sysirq"
> >>> "mediatek,mt6755-sysirq"
> >>> "mediatek,mt6592-sysirq"
> >>> @@ -21,7 +22,8 @@ Required properties:
> >>> - interrupt-parent: phandle of irq parent for sysirq. The parent must
> >>> use the same interrupt-cells format as GIC.
> >>> - reg: Physical base address of the intpol registers and length of memory
> >>> - mapped region.
> >>> + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg,
> >>> + others need 1.
> >>
> >> Two things:
> >>
> >> - Please make this a separate patch that can be reviewed independently
> >> of the rest of the changes, which are just adding new compatible
> >> identifiers.
> >
> > Will fix this in the next patch set.
> >
> >>
> >> - Why can't you simply expose it as a separate controller? Looking at
> >> the way you're changing the corresponding driver, it looks like you're
> >> simply adding an extra base/size. If you simply had a base for the
> >> corresponding GIC interrupts, you could handle as many region as you
> >> want, and have a more generic driver.
> >>
> >
> > May I know the meaning of "simply expose it as a separate controller"?
>
> At the moment, you have something like this:
>
> sysirq: intpol-controller@10200620 {
> compatible = "mediatek,mt6755-sysirq",
> "mediatek,mt6577-sysirq";
> interrupt-controller;
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> reg = <0 0x10200620 0 0x20>;
> };
>
> I suggest that, when you have a second base (which is effectively
> another controller), you add:
>
> sysirq2: intpol-controller@10201620 {
> compatible = "mediatek,mt6755-sysirq",
> "mediatek,mt6577-sysirq";
> interrupt-controller;
> #interrupt-cells = <3>;
> interrupt-parent = <&gic>;
> irq-base = <32>;
> reg = <0 0x10201620 0 0x20>;
> };
>
> Where irq-base is the first SPI this is connected to (the lack of
> property indicates implies that irq-base is 0). This becomes a very
> simple change in the driver.
>
> > Or you might like to suggest me any similar driver as a reference? I
> > will examine it. Current design is based on the fact: We expect
> > irq-mtk-sysirq needs the optional second base but the third one will not
> > happen.
> >
> > If we really need more than 2 bases, we can figure out a more generic
> > driver at the time, right?
>
> I'd rather fix the driver and the binding to do the right thing once and
> for all. In my experience, you will need to add a third base in six
> months, and a fourth soon after. I'd rather either support an arbitrary
> number of bases, or a single one per controller (and have multiple
> controllers).
Hi Marc
Thanks for suggesting this approach I never thought.
However, I will modify the irq-mtk-sysirq driver to handle as many bases
as we specify in current node in the next patch set. Will not use the
second interrupt node in DT. The main reason is to simplify the writing
of DT. Or we need to know which interrupt node to be specified for other
nodes. As you said that might be the third or fourth bases, that will
complicate the writing of DT more.
Would you think this is OK?
Thanks.
>
> Thanks,
>
> M.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 3/6] pinctrl: mediatek: constify gpio_chip structures
From: Julia Lawall @ 2016-09-11 12:14 UTC (permalink / raw)
To: Linus Walleij
Cc: kernel-janitors, Matthias Brugger, linux-gpio, linux-arm-kernel,
linux-mediatek, linux-kernel
In-Reply-To: <1473596082-32690-1-git-send-email-Julia.Lawall@lip6.fr>
These structures are only used to copy into other structures, so declare
them as const.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index ba2b03d..f9aef2a 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -1054,7 +1054,7 @@ static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
return 0;
}
-static struct gpio_chip mtk_gpio_chip = {
+static const struct gpio_chip mtk_gpio_chip = {
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
^ permalink raw reply related
* [PATCH 0/6] constify gpio_chip structures
From: Julia Lawall @ 2016-09-11 12:14 UTC (permalink / raw)
To: linux-kernel
Cc: kernel-janitors, linux-gpio, linux-arm-kernel,
bcm-kernel-feedback-list, linux-mediatek, alsa-devel
Constify gpio_chip structures
---
drivers/gpio/gpio-arizona.c | 2 +-
drivers/gpio/gpio-bcm-kona.c | 2 +-
drivers/gpio/gpio-da9052.c | 2 +-
drivers/gpio/gpio-da9055.c | 2 +-
drivers/gpio/gpio-it87.c | 2 +-
drivers/gpio/gpio-lp873x.c | 2 +-
drivers/gpio/gpio-lpc18xx.c | 2 +-
drivers/gpio/gpio-pisosr.c | 2 +-
drivers/gpio/gpio-sch.c | 2 +-
drivers/gpio/gpio-stmpe.c | 2 +-
drivers/gpio/gpio-tc3589x.c | 2 +-
drivers/gpio/gpio-tpic2810.c | 2 +-
drivers/gpio/gpio-tps65086.c | 2 +-
drivers/gpio/gpio-tps65218.c | 2 +-
drivers/gpio/gpio-tps65912.c | 2 +-
drivers/gpio/gpio-ts4900.c | 2 +-
drivers/gpio/gpio-twl4030.c | 2 +-
drivers/gpio/gpio-wm831x.c | 2 +-
drivers/gpio/gpio-wm8350.c | 2 +-
drivers/gpio/gpio-wm8994.c | 2 +-
drivers/mfd/sm501.c | 2 +-
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +-
drivers/pinctrl/stm32/pinctrl-stm32.c | 2 +-
sound/soc/codecs/rt5677.c | 2 +-
sound/soc/codecs/wm5100.c | 2 +-
sound/soc/codecs/wm8903.c | 2 +-
sound/soc/codecs/wm8962.c | 2 +-
sound/soc/codecs/wm8996.c | 2 +-
sound/soc/soc-ac97.c | 2 +-
29 files changed, 29 insertions(+), 29 deletions(-)
^ permalink raw reply
* [PATCH -next] drm/mediatek: Remove redundant dev_err call in mtk_drm_probe()
From: Wei Yongjun @ 2016-09-10 12:33 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, David Airlie, Matthias Brugger
Cc: Wei Yongjun, dri-devel, linux-arm-kernel, linux-mediatek,
linux-kernel
From: Wei Yongjun <weiyongjun1@huawei.com>
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 72c1ae4..f4f90e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -365,12 +365,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
private->config_regs = devm_ioremap_resource(dev, mem);
- if (IS_ERR(private->config_regs)) {
- ret = PTR_ERR(private->config_regs);
- dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
- ret);
- return ret;
- }
+ if (IS_ERR(private->config_regs))
+ return PTR_ERR(private->config_regs);
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(dev->of_node->parent, node) {
^ permalink raw reply related
* Re: [PATCH] [media] platform: constify vb2_ops structures
From: Benoit Parrot @ 2016-09-09 16:03 UTC (permalink / raw)
To: Julia Lawall
Cc: Sylwester Nawrocki, kernel-janitors, Fabien Dessenne,
linux-samsung-soc, Krzysztof Kozlowski, Kukjin Kim, Andrzej Hajda,
Kamil Debski, Kyungmin Park, Guennadi Liakhovetski,
Ludovic Desroches, Hyun Kwon, Laurent Pinchart,
Mauro Carvalho Chehab, Michal Simek, Sören Brinkmann,
linux-media, linux-arm-kernel
In-Reply-To: <1473379150-17315-1-git-send-email-Julia.Lawall@lip6.fr>
Hi,
Thanks for the patch.
Julia Lawall <Julia.Lawall@lip6.fr> wrote on Fri [2016-Sep-09 01:59:10 +0200]:
> Check for vb2_ops structures that are only stored in the ops field of a
> vb2_queue structure. That field is declared const, so vb2_ops structures
> that have this property can be declared as const also.
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @r disable optional_qualifier@
> identifier i;
> position p;
> @@
> static struct vb2_ops i@p = { ... };
>
> @ok@
> identifier r.i;
> struct vb2_queue e;
> position p;
> @@
> e.ops = &i@p;
>
> @bad@
> position p != {r.p,ok.p};
> identifier r.i;
> struct vb2_ops e;
> @@
> e@i@p
>
> @depends on !bad disable optional_qualifier@
> identifier r.i;
> @@
> static
> +const
> struct vb2_ops i = { ... };
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
>
> ---
> drivers/media/platform/exynos-gsc/gsc-m2m.c | 2 +-
> drivers/media/platform/exynos4-is/fimc-capture.c | 2 +-
> drivers/media/platform/exynos4-is/fimc-m2m.c | 2 +-
> drivers/media/platform/m2m-deinterlace.c | 2 +-
> drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c | 2 +-
> drivers/media/platform/mx2_emmaprp.c | 2 +-
> drivers/media/platform/rcar-vin/rcar-dma.c | 2 +-
> drivers/media/platform/rcar_jpu.c | 2 +-
> drivers/media/platform/s5p-g2d/g2d.c | 2 +-
> drivers/media/platform/s5p-jpeg/jpeg-core.c | 2 +-
> drivers/media/platform/sh_vou.c | 2 +-
> drivers/media/platform/soc_camera/atmel-isi.c | 2 +-
> drivers/media/platform/soc_camera/rcar_vin.c | 2 +-
> drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 2 +-
> drivers/media/platform/sti/bdisp/bdisp-v4l2.c | 2 +-
For the following 2 drivers,
> drivers/media/platform/ti-vpe/cal.c | 2 +-
> drivers/media/platform/ti-vpe/vpe.c | 2 +-
Reviewed-by: Benoit Parrot <bparrot@ti.com>
> drivers/media/platform/vim2m.c | 2 +-
> drivers/media/platform/xilinx/xilinx-dma.c | 2 +-
> 19 files changed, 19 insertions(+), 19 deletions(-)
Regards,
Benoit Parrot
^ permalink raw reply
* [PATCH v2 4/4] arm64: dts: mediatek: Add Video Decoder for MT8173
From: Tiffany Lin @ 2016-09-09 15:48 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Matthias Brugger, Daniel Kurtz, Pawel Osciak
Cc: Eddie Huang, Yingjoe Chen, linux-kernel, linux-media,
linux-mediatek, Tiffany.lin, Tiffany Lin
In-Reply-To: <1473436087-21943-4-git-send-email-tiffany.lin@mediatek.com>
Add video decoder node for MT8173
Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 44 ++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 10f638f..2872cd7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -974,6 +974,50 @@
#clock-cells = <1>;
};
+ vcodec_dec: vcodec@16000000 {
+ compatible = "mediatek,mt8173-vcodec-dec";
+ reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
+ <0 0x16020000 0 0x1000>, /* VDEC_MISC */
+ <0 0x16021000 0 0x800>, /* VDEC_LD */
+ <0 0x16021800 0 0x800>, /* VDEC_TOP */
+ <0 0x16022000 0 0x1000>, /* VDEC_CM */
+ <0 0x16023000 0 0x1000>, /* VDEC_AD */
+ <0 0x16024000 0 0x1000>, /* VDEC_AV */
+ <0 0x16025000 0 0x1000>, /* VDEC_PP */
+ <0 0x16026800 0 0x800>, /* VDEC_HWD */
+ <0 0x16027000 0 0x800>, /* VDEC_HWQ */
+ <0 0x16027800 0 0x800>, /* VDEC_HWB */
+ <0 0x16028400 0 0x400>; /* VDEC_HWG */
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb1>;
+ iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
+ mediatek,vpu = <&vpu>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
+ <&topckgen CLK_TOP_UNIVPLL_D2>,
+ <&topckgen CLK_TOP_CCI400_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_VCODECPLL>,
+ <&apmixedsys CLK_APMIXED_VENCPLL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>,
+ <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ clock-names = "vcodecpll",
+ "univpll_d2",
+ "clk_cci400_sel",
+ "vdec_sel",
+ "vdecpll",
+ "vencpll",
+ "venc_lt_sel",
+ "vdec_bus_clk_src";
+ };
+
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x16010000 0 0x1000>;
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 3/4] vcodec: mediatek: Add V4L2_PIX_FMT_MT21C support for v4l2 decoder
From: Tiffany Lin @ 2016-09-09 15:48 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Matthias Brugger, Daniel Kurtz, Pawel Osciak
Cc: Tiffany Lin, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yingjoe Chen,
Eddie Huang, linux-media-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1473436087-21943-3-git-send-email-tiffany.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Add V4L2_PIX_FMT_MT21C support
Signed-off-by: Tiffany Lin <tiffany.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
index 28a8453..fd3befc 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
@@ -25,7 +25,7 @@
#include "mtk_vcodec_dec_pm.h"
#define OUT_FMT_IDX 0
-#define CAP_FMT_IDX 0
+#define CAP_FMT_IDX 3
#define MTK_VDEC_MIN_W 64U
#define MTK_VDEC_MIN_H 64U
@@ -48,6 +48,11 @@ static struct mtk_video_fmt mtk_video_formats[] = {
.type = MTK_FMT_DEC,
.num_planes = 1,
},
+ {
+ .fourcc = V4L2_PIX_FMT_MT21C,
+ .type = MTK_FMT_FRAME,
+ .num_planes = 2,
+ },
};
static const struct mtk_codec_framesizes mtk_vdec_framesizes[] = {
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 2/4] docs-rst: Add compressed video formats used on MT8173 codec driver
From: Tiffany Lin @ 2016-09-09 15:48 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Matthias Brugger, Daniel Kurtz, Pawel Osciak
Cc: Eddie Huang, Yingjoe Chen, linux-kernel, linux-media,
linux-mediatek, Tiffany.lin, Tiffany Lin
In-Reply-To: <1473436087-21943-2-git-send-email-tiffany.lin@mediatek.com>
Add V4L2_PIX_FMT_MT21C documentation
Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
---
Documentation/media/uapi/v4l/pixfmt-reserved.rst | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/media/uapi/v4l/pixfmt-reserved.rst b/Documentation/media/uapi/v4l/pixfmt-reserved.rst
index 0dd2f7f..0989e99 100644
--- a/Documentation/media/uapi/v4l/pixfmt-reserved.rst
+++ b/Documentation/media/uapi/v4l/pixfmt-reserved.rst
@@ -339,7 +339,17 @@ please make a proposal on the linux-media mailing list.
array. Anything what's in between the UYVY lines is JPEG data and
should be concatenated to form the JPEG stream.
+ - .. _V4L2-PIX-FMT-MT21C:
+ - ``V4L2_PIX_FMT_MT21C``
+
+ - 'MT21C'
+
+ - Compressed two-planar YVU420 format used by Mediatek MT8173.
+ The compression is lossless.
+ It is an opaque intermediate format, and MDP HW could convert
+ V4L2_PIX_FMT_MT21C to V4L2_PIX_FMT_NV12M,
+ V4L2_PIX_FMT_YUV420M and V4L2_PIX_FMT_YVU420.
.. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}|
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 1/4] v4l: add Mediatek compressed video block format
From: Tiffany Lin @ 2016-09-09 15:48 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Matthias Brugger, Daniel Kurtz, Pawel Osciak
Cc: Tiffany Lin, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yingjoe Chen,
Eddie Huang, linux-media-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1473436087-21943-1-git-send-email-tiffany.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Add V4L2_PIX_FMT_MT21C format used on MT8173 driver.
It is compressed format and need MT8173 MDP driver to transfer to other
standard format.
Signed-off-by: Tiffany Lin <tiffany.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
include/uapi/linux/videodev2.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index 2bd1581..1d45c58 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1288,6 +1288,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_PIX_FMT_JPGL: descr = "JPEG Lite"; break;
case V4L2_PIX_FMT_SE401: descr = "GSPCA SE401"; break;
case V4L2_PIX_FMT_S5C_UYVY_JPG: descr = "S5C73MX interleaved UYVY/JPEG"; break;
+ case V4L2_PIX_FMT_MT21C: descr = "Mediatek Compressed Format"; break;
default:
WARN(1, "Unknown pixelformat 0x%08x\n", fmt->pixelformat);
if (fmt->description[0])
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 43326c3..ddd0083 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -635,6 +635,7 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_Y8I v4l2_fourcc('Y', '8', 'I', ' ') /* Greyscale 8-bit L/R interleaved */
#define V4L2_PIX_FMT_Y12I v4l2_fourcc('Y', '1', '2', 'I') /* Greyscale 12-bit L/R interleaved */
#define V4L2_PIX_FMT_Z16 v4l2_fourcc('Z', '1', '6', ' ') /* Depth data 16-bit */
+#define V4L2_PIX_FMT_MT21C v4l2_fourcc('M', 'T', '2', '1') /* Mediatek compressed block mode */
/* SDR formats - used only for Software Defined Radio devices */
#define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') /* IQ u8 */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 0/4] Add V4L2_PIX_FMT_MT21C format for MT8173 codec driver
From: Tiffany Lin @ 2016-09-09 15:48 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Matthias Brugger, Daniel Kurtz, Pawel Osciak
Cc: Eddie Huang, Yingjoe Chen, linux-kernel, linux-media,
linux-mediatek, Tiffany.lin, Tiffany Lin
This patch series add Mediatek compressed block format V4L2_PIX_FMT_MT21C,
the decoder driver will decoded bitstream to V4L2_PIX_FMT_MT21C format.
User space applications could use MT8173 MDP driver to convert V4L2_PIX_FMT_MT21C
to V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M and V4L2_PIX_FMT_YVU420.
MDP driver[1] is stand alone driver.
Usage:
MT21C -> MT8173 MDP -> NV12M/YUV420M/YVU420 NV12M/NV21M/YUV420M/YVU420M -> mt8173 Encoder -> H264/VP8
H264/VP8/VP9 -> mtk8173 Decoder -> MT21C
When encode with MT21 source, the pipeline will be:
MT21C -> MDP driver-> NV12M/NV21M/YUV420M/YVU420M -> Encoder -> H264/VP8
When playback, the pipeline will be:
H264/VP8/VP9 -> Decoder driver -> MT21C -> MDP Driver -> DRM
[1]https://patchwork.kernel.org/patch/9305329/
---
v2: add more information for MT21C in docs-rst
---
Tiffany Lin (4):
v4l: add Mediatek compressed video block format
docs-rst: Add compressed video formats used on MT8173 codec driver
vcodec: mediatek: Add V4L2_PIX_FMT_MT21C support for v4l2 decoder
arm64: dts: mediatek: Add Video Decoder for MT8173
Documentation/media/uapi/v4l/pixfmt-reserved.rst | 10 +++++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 44 ++++++++++++++++++++
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 7 +++-
drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
include/uapi/linux/videodev2.h | 1 +
5 files changed, 62 insertions(+), 1 deletion(-)
--
1.7.9.5
^ permalink raw reply
* Re: [PATCH] [media] platform: constify vb2_ops structures
From: Jacek Anaszewski @ 2016-09-09 9:48 UTC (permalink / raw)
To: Julia Lawall, Sylwester Nawrocki
Cc: kernel-janitors, Fabien Dessenne, linux-samsung-soc,
Krzysztof Kozlowski, Kukjin Kim, Andrzej Hajda, Kamil Debski,
Kyungmin Park, Benoit Parrot, Guennadi Liakhovetski,
Ludovic Desroches, Hyun Kwon, Laurent Pinchart,
Mauro Carvalho Chehab, Michal Simek, Sören Brinkmann,
linux-media, linux-arm-kernel, linux-kernel
In-Reply-To: <1473379150-17315-1-git-send-email-Julia.Lawall@lip6.fr>
Hi Julia,
On 09/09/2016 01:59 AM, Julia Lawall wrote:
> Check for vb2_ops structures that are only stored in the ops field of a
> vb2_queue structure. That field is declared const, so vb2_ops structures
> that have this property can be declared as const also.
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.lip6.fr/)
>
[...]
> diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c
> index 785e693..d9c07b8 100644
> --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
> +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
> @@ -2538,7 +2538,7 @@ static void s5p_jpeg_stop_streaming(struct vb2_queue *q)
> pm_runtime_put(ctx->jpeg->dev);
> }
>
> -static struct vb2_ops s5p_jpeg_qops = {
> +static const struct vb2_ops s5p_jpeg_qops = {
> .queue_setup = s5p_jpeg_queue_setup,
> .buf_prepare = s5p_jpeg_buf_prepare,
> .buf_queue = s5p_jpeg_buf_queue,
> diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
> index e967fcf..44323cb 100644
> --- a/drivers/media/platform/ti-vpe/cal.c
> +++ b/drivers/media/platform/ti-vpe/cal.c
> @@ -1379,7 +1379,7 @@ static void cal_stop_streaming(struct vb2_queue *vq)
> cal_runtime_put(ctx->dev);
> }
Thanks for the patch.
For s5p-jpeg driver:
Reviewed-by: Jacek Anaszewski <j.anaszewski@samsung.com>
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH] [media] platform: constify vb2_ops structures
From: Fabien DESSENNE @ 2016-09-09 8:53 UTC (permalink / raw)
To: Julia Lawall, Sylwester Nawrocki
Cc: kernel-janitors-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Kamil Debski, Andrzej Hajda, Laurent Pinchart,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Michal Simek, Krzysztof Kozlowski, Kukjin Kim,
Sören Brinkmann, Mikhail Ulyanov,
linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Benoit Parrot,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Matthias Brugger, Mauro Carvalho Chehab, Jacek Anaszewski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <1473379150-17315-1-git-send-email-Julia.Lawall-L2FTfq7BK8M@public.gmane.org>
Hi
On 09/09/2016 01:59 AM, Julia Lawall wrote:
> Check for vb2_ops structures that are only stored in the ops field of a
> vb2_queue structure. That field is declared const, so vb2_ops structures
> that have this property can be declared as const also.
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @r disable optional_qualifier@
> identifier i;
> position p;
> @@
> static struct vb2_ops i@p = { ... };
>
> @ok@
> identifier r.i;
> struct vb2_queue e;
> position p;
> @@
> e.ops = &i@p;
>
> @bad@
> position p != {r.p,ok.p};
> identifier r.i;
> struct vb2_ops e;
> @@
> e@i@p
>
> @depends on !bad disable optional_qualifier@
> identifier r.i;
> @@
> static
> +const
> struct vb2_ops i = { ... };
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall-L2FTfq7BK8M@public.gmane.org>
>
> ---
> drivers/media/platform/exynos-gsc/gsc-m2m.c | 2 +-
> drivers/media/platform/exynos4-is/fimc-capture.c | 2 +-
> drivers/media/platform/exynos4-is/fimc-m2m.c | 2 +-
> drivers/media/platform/m2m-deinterlace.c | 2 +-
> drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c | 2 +-
> drivers/media/platform/mx2_emmaprp.c | 2 +-
> drivers/media/platform/rcar-vin/rcar-dma.c | 2 +-
> drivers/media/platform/rcar_jpu.c | 2 +-
> drivers/media/platform/s5p-g2d/g2d.c | 2 +-
> drivers/media/platform/s5p-jpeg/jpeg-core.c | 2 +-
> drivers/media/platform/sh_vou.c | 2 +-
> drivers/media/platform/soc_camera/atmel-isi.c | 2 +-
> drivers/media/platform/soc_camera/rcar_vin.c | 2 +-
> drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 2 +-
For this driver:
> drivers/media/platform/sti/bdisp/bdisp-v4l2.c | 2 +-
Reviewed-by: Fabien Dessenne <fabien.dessenne-qxv4g6HH51o@public.gmane.org>
> drivers/media/platform/ti-vpe/cal.c | 2 +-
> drivers/media/platform/ti-vpe/vpe.c | 2 +-
> drivers/media/platform/vim2m.c | 2 +-
> drivers/media/platform/xilinx/xilinx-dma.c | 2 +-
> 19 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/media/platform/xilinx/xilinx-dma.c b/drivers/media/platform/xilinx/xilinx-dma.c
> index 7ae1a13..1d5836c 100644
> --- a/drivers/media/platform/xilinx/xilinx-dma.c
> +++ b/drivers/media/platform/xilinx/xilinx-dma.c
> @@ -474,7 +474,7 @@ static void xvip_dma_stop_streaming(struct vb2_queue *vq)
> spin_unlock_irq(&dma->queued_lock);
> }
>
> -static struct vb2_ops xvip_dma_queue_qops = {
> +static const struct vb2_ops xvip_dma_queue_qops = {
> .queue_setup = xvip_dma_queue_setup,
> .buf_prepare = xvip_dma_buffer_prepare,
> .buf_queue = xvip_dma_buffer_queue,
> diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c
> index 30211f6..46de657 100644
> --- a/drivers/media/platform/soc_camera/atmel-isi.c
> +++ b/drivers/media/platform/soc_camera/atmel-isi.c
> @@ -536,7 +536,7 @@ static void stop_streaming(struct vb2_queue *vq)
> pm_runtime_put(ici->v4l2_dev.dev);
> }
>
> -static struct vb2_ops isi_video_qops = {
> +static const struct vb2_ops isi_video_qops = {
> .queue_setup = queue_setup,
> .buf_init = buffer_init,
> .buf_prepare = buffer_prepare,
> diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c
> index 785e693..d9c07b8 100644
> --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
> +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
> @@ -2538,7 +2538,7 @@ static void s5p_jpeg_stop_streaming(struct vb2_queue *q)
> pm_runtime_put(ctx->jpeg->dev);
> }
>
> -static struct vb2_ops s5p_jpeg_qops = {
> +static const struct vb2_ops s5p_jpeg_qops = {
> .queue_setup = s5p_jpeg_queue_setup,
> .buf_prepare = s5p_jpeg_buf_prepare,
> .buf_queue = s5p_jpeg_buf_queue,
> diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
> index e967fcf..44323cb 100644
> --- a/drivers/media/platform/ti-vpe/cal.c
> +++ b/drivers/media/platform/ti-vpe/cal.c
> @@ -1379,7 +1379,7 @@ static void cal_stop_streaming(struct vb2_queue *vq)
> cal_runtime_put(ctx->dev);
> }
>
> -static struct vb2_ops cal_video_qops = {
> +static const struct vb2_ops cal_video_qops = {
> .queue_setup = cal_queue_setup,
> .buf_prepare = cal_buffer_prepare,
> .buf_queue = cal_buffer_queue,
> diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c
> index 55a1458..0189f7f 100644
> --- a/drivers/media/platform/ti-vpe/vpe.c
> +++ b/drivers/media/platform/ti-vpe/vpe.c
> @@ -1878,7 +1878,7 @@ static void vpe_stop_streaming(struct vb2_queue *q)
> vpdma_dump_regs(ctx->dev->vpdma);
> }
>
> -static struct vb2_ops vpe_qops = {
> +static const struct vb2_ops vpe_qops = {
> .queue_setup = vpe_queue_setup,
> .buf_prepare = vpe_buf_prepare,
> .buf_queue = vpe_buf_queue,
> diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c
> index 9c13752..0009fc5 100644
> --- a/drivers/media/platform/soc_camera/rcar_vin.c
> +++ b/drivers/media/platform/soc_camera/rcar_vin.c
> @@ -856,7 +856,7 @@ static void rcar_vin_stop_streaming(struct vb2_queue *vq)
> spin_unlock_irq(&priv->lock);
> }
>
> -static struct vb2_ops rcar_vin_vb2_ops = {
> +static const struct vb2_ops rcar_vin_vb2_ops = {
> .queue_setup = rcar_vin_videobuf_setup,
> .buf_queue = rcar_vin_videobuf_queue,
> .stop_streaming = rcar_vin_stop_streaming,
> diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
> index 02b519d..02c8dc5 100644
> --- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
> +++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
> @@ -470,7 +470,7 @@ static void sh_mobile_ceu_stop_streaming(struct vb2_queue *q)
> sh_mobile_ceu_soft_reset(pcdev);
> }
>
> -static struct vb2_ops sh_mobile_ceu_videobuf_ops = {
> +static const struct vb2_ops sh_mobile_ceu_videobuf_ops = {
> .queue_setup = sh_mobile_ceu_videobuf_setup,
> .buf_prepare = sh_mobile_ceu_videobuf_prepare,
> .buf_queue = sh_mobile_ceu_videobuf_queue,
> diff --git a/drivers/media/platform/s5p-g2d/g2d.c b/drivers/media/platform/s5p-g2d/g2d.c
> index 391dd7a..62c0dec 100644
> --- a/drivers/media/platform/s5p-g2d/g2d.c
> +++ b/drivers/media/platform/s5p-g2d/g2d.c
> @@ -138,7 +138,7 @@ static void g2d_buf_queue(struct vb2_buffer *vb)
> v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
> }
>
> -static struct vb2_ops g2d_qops = {
> +static const struct vb2_ops g2d_qops = {
> .queue_setup = g2d_queue_setup,
> .buf_prepare = g2d_buf_prepare,
> .buf_queue = g2d_buf_queue,
> diff --git a/drivers/media/platform/rcar_jpu.c b/drivers/media/platform/rcar_jpu.c
> index 16782ce..d1746ec 100644
> --- a/drivers/media/platform/rcar_jpu.c
> +++ b/drivers/media/platform/rcar_jpu.c
> @@ -1183,7 +1183,7 @@ static void jpu_stop_streaming(struct vb2_queue *vq)
> }
> }
>
> -static struct vb2_ops jpu_qops = {
> +static const struct vb2_ops jpu_qops = {
> .queue_setup = jpu_queue_setup,
> .buf_prepare = jpu_buf_prepare,
> .buf_queue = jpu_buf_queue,
> diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c b/drivers/media/platform/exynos-gsc/gsc-m2m.c
> index ec6494c..a341a7f 100644
> --- a/drivers/media/platform/exynos-gsc/gsc-m2m.c
> +++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c
> @@ -261,7 +261,7 @@ static void gsc_m2m_buf_queue(struct vb2_buffer *vb)
> v4l2_m2m_buf_queue(ctx->m2m_ctx, vbuf);
> }
>
> -static struct vb2_ops gsc_m2m_qops = {
> +static const struct vb2_ops gsc_m2m_qops = {
> .queue_setup = gsc_m2m_queue_setup,
> .buf_prepare = gsc_m2m_buf_prepare,
> .buf_queue = gsc_m2m_buf_queue,
> diff --git a/drivers/media/platform/sh_vou.c b/drivers/media/platform/sh_vou.c
> index e1f39b4..1ec9a2e 100644
> --- a/drivers/media/platform/sh_vou.c
> +++ b/drivers/media/platform/sh_vou.c
> @@ -362,7 +362,7 @@ static void sh_vou_stop_streaming(struct vb2_queue *vq)
> spin_unlock_irqrestore(&vou_dev->lock, flags);
> }
>
> -static struct vb2_ops sh_vou_qops = {
> +static const struct vb2_ops sh_vou_qops = {
> .queue_setup = sh_vou_queue_setup,
> .buf_prepare = sh_vou_buf_prepare,
> .buf_queue = sh_vou_buf_queue,
> diff --git a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
> index 3b1ac68..45f82b5 100644
> --- a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
> +++ b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
> @@ -527,7 +527,7 @@ static void bdisp_stop_streaming(struct vb2_queue *q)
> pm_runtime_put(ctx->bdisp_dev->dev);
> }
>
> -static struct vb2_ops bdisp_qops = {
> +static const struct vb2_ops bdisp_qops = {
> .queue_setup = bdisp_queue_setup,
> .buf_prepare = bdisp_buf_prepare,
> .buf_queue = bdisp_buf_queue,
> diff --git a/drivers/media/platform/m2m-deinterlace.c b/drivers/media/platform/m2m-deinterlace.c
> index 0fcb5c78..0870fad 100644
> --- a/drivers/media/platform/m2m-deinterlace.c
> +++ b/drivers/media/platform/m2m-deinterlace.c
> @@ -852,7 +852,7 @@ static void deinterlace_buf_queue(struct vb2_buffer *vb)
> v4l2_m2m_buf_queue(ctx->m2m_ctx, vbuf);
> }
>
> -static struct vb2_ops deinterlace_qops = {
> +static const struct vb2_ops deinterlace_qops = {
> .queue_setup = deinterlace_queue_setup,
> .buf_prepare = deinterlace_buf_prepare,
> .buf_queue = deinterlace_buf_queue,
> diff --git a/drivers/media/platform/mx2_emmaprp.c b/drivers/media/platform/mx2_emmaprp.c
> index c639406..e68d271 100644
> --- a/drivers/media/platform/mx2_emmaprp.c
> +++ b/drivers/media/platform/mx2_emmaprp.c
> @@ -743,7 +743,7 @@ static void emmaprp_buf_queue(struct vb2_buffer *vb)
> v4l2_m2m_buf_queue(ctx->m2m_ctx, vbuf);
> }
>
> -static struct vb2_ops emmaprp_qops = {
> +static const struct vb2_ops emmaprp_qops = {
> .queue_setup = emmaprp_queue_setup,
> .buf_prepare = emmaprp_buf_prepare,
> .buf_queue = emmaprp_buf_queue,
> diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
> index 496aa97..07c07c1 100644
> --- a/drivers/media/platform/rcar-vin/rcar-dma.c
> +++ b/drivers/media/platform/rcar-vin/rcar-dma.c
> @@ -1116,7 +1116,7 @@ static void rvin_stop_streaming(struct vb2_queue *vq)
> rvin_disable_interrupts(vin);
> }
>
> -static struct vb2_ops rvin_qops = {
> +static const struct vb2_ops rvin_qops = {
> .queue_setup = rvin_queue_setup,
> .buf_prepare = rvin_buffer_prepare,
> .buf_queue = rvin_buffer_queue,
> diff --git a/drivers/media/platform/vim2m.c b/drivers/media/platform/vim2m.c
> index cd0ff4a..a98f679 100644
> --- a/drivers/media/platform/vim2m.c
> +++ b/drivers/media/platform/vim2m.c
> @@ -815,7 +815,7 @@ static void vim2m_stop_streaming(struct vb2_queue *q)
> }
> }
>
> -static struct vb2_ops vim2m_qops = {
> +static const struct vb2_ops vim2m_qops = {
> .queue_setup = vim2m_queue_setup,
> .buf_prepare = vim2m_buf_prepare,
> .buf_queue = vim2m_buf_queue,
> diff --git a/drivers/media/platform/exynos4-is/fimc-capture.c b/drivers/media/platform/exynos4-is/fimc-capture.c
> index fdec499..344028e 100644
> --- a/drivers/media/platform/exynos4-is/fimc-capture.c
> +++ b/drivers/media/platform/exynos4-is/fimc-capture.c
> @@ -452,7 +452,7 @@ static void buffer_queue(struct vb2_buffer *vb)
> spin_unlock_irqrestore(&fimc->slock, flags);
> }
>
> -static struct vb2_ops fimc_capture_qops = {
> +static const struct vb2_ops fimc_capture_qops = {
> .queue_setup = queue_setup,
> .buf_prepare = buffer_prepare,
> .buf_queue = buffer_queue,
> diff --git a/drivers/media/platform/exynos4-is/fimc-m2m.c b/drivers/media/platform/exynos4-is/fimc-m2m.c
> index b1309e1..6028e4f 100644
> --- a/drivers/media/platform/exynos4-is/fimc-m2m.c
> +++ b/drivers/media/platform/exynos4-is/fimc-m2m.c
> @@ -219,7 +219,7 @@ static void fimc_buf_queue(struct vb2_buffer *vb)
> v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
> }
>
> -static struct vb2_ops fimc_qops = {
> +static const struct vb2_ops fimc_qops = {
> .queue_setup = fimc_queue_setup,
> .buf_prepare = fimc_buf_prepare,
> .buf_queue = fimc_buf_queue,
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> index 3ed3f2d..f8e4611 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> @@ -864,7 +864,7 @@ static void vb2ops_venc_stop_streaming(struct vb2_queue *q)
> ctx->state = MTK_STATE_FREE;
> }
>
> -static struct vb2_ops mtk_venc_vb2_ops = {
> +static const struct vb2_ops mtk_venc_vb2_ops = {
> .queue_setup = vb2ops_venc_queue_setup,
> .buf_prepare = vb2ops_venc_buf_prepare,
> .buf_queue = vb2ops_venc_buf_queue,
>
^ permalink raw reply
* Re: [PATCH] [media] platform: constify vb2_ops structures
From: Laurent Pinchart @ 2016-09-09 8:42 UTC (permalink / raw)
To: Julia Lawall
Cc: Sylwester Nawrocki, kernel-janitors, Fabien Dessenne,
linux-samsung-soc, Krzysztof Kozlowski, Kukjin Kim, Andrzej Hajda,
Kamil Debski, Kyungmin Park, Benoit Parrot, Guennadi Liakhovetski,
Ludovic Desroches, Hyun Kwon, Mauro Carvalho Chehab, Michal Simek,
Sören Brinkmann, linux-media, linux-arm-kernel, linux-kernel
In-Reply-To: <1473379150-17315-1-git-send-email-Julia.Lawall@lip6.fr>
Hi Julia,
Thank you for the patch.
On Friday 09 Sep 2016 01:59:10 Julia Lawall wrote:
> Check for vb2_ops structures that are only stored in the ops field of a
> vb2_queue structure. That field is declared const, so vb2_ops structures
> that have this property can be declared as const also.
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @r disable optional_qualifier@
> identifier i;
> position p;
> @@
> static struct vb2_ops i@p = { ... };
>
> @ok@
> identifier r.i;
> struct vb2_queue e;
> position p;
> @@
> e.ops = &i@p;
>
> @bad@
> position p != {r.p,ok.p};
> identifier r.i;
> struct vb2_ops e;
> @@
> e@i@p
>
> @depends on !bad disable optional_qualifier@
> identifier r.i;
> @@
> static
> +const
> struct vb2_ops i = { ... };
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
For the drivers below,
> drivers/media/platform/m2m-deinterlace.c | 2 +-
> drivers/media/platform/rcar-vin/rcar-dma.c | 2 +-
> drivers/media/platform/rcar_jpu.c | 2 +-
> drivers/media/platform/sh_vou.c | 2 +-
> drivers/media/platform/soc_camera/atmel-isi.c | 2 +-
> drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 2 +-
> drivers/media/platform/vim2m.c | 2 +-
> drivers/media/platform/xilinx/xilinx-dma.c | 2 +-
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
For
> drivers/media/platform/soc_camera/rcar_vin.c | 2 +-
you can also add my
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
tag, but the driver will be scheduled for removal very soon.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH] [media] VPU: mediatek: fix null pointer dereference on pdev
From: andrew-ct chen @ 2016-09-09 1:25 UTC (permalink / raw)
To: Colin King
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Wei Yongjun, Tiffany Lin, linux-media, linux-arm-kernel,
linux-mediatek, linux-kernel
In-Reply-To: <20160907171027.16424-1-colin.king@canonical.com>
On Wed, 2016-09-07 at 18:10 +0100, Colin King wrote:
> From: Colin Ian King <colin.king@canonical.com>
>
> pdev is being null checked, however, prior to that it is being
> dereferenced by platform_get_drvdata. Move the assignments of
> vpu and run to after the pdev null check to avoid a potential
> null pointer dereference.
>
Reviewed-by:Andrew-CT Chen <andrew-ct.chen@mediatek.com>
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> ---
> drivers/media/platform/mtk-vpu/mtk_vpu.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-vpu/mtk_vpu.c b/drivers/media/platform/mtk-vpu/mtk_vpu.c
> index c9bf58c..43907a3 100644
> --- a/drivers/media/platform/mtk-vpu/mtk_vpu.c
> +++ b/drivers/media/platform/mtk-vpu/mtk_vpu.c
> @@ -523,9 +523,9 @@ static int load_requested_vpu(struct mtk_vpu *vpu,
>
> int vpu_load_firmware(struct platform_device *pdev)
> {
> - struct mtk_vpu *vpu = platform_get_drvdata(pdev);
> + struct mtk_vpu *vpu;
> struct device *dev = &pdev->dev;
> - struct vpu_run *run = &vpu->run;
> + struct vpu_run *run;
> const struct firmware *vpu_fw = NULL;
> int ret;
>
> @@ -534,6 +534,9 @@ int vpu_load_firmware(struct platform_device *pdev)
> return -EINVAL;
> }
>
> + vpu = platform_get_drvdata(pdev);
> + run = &vpu->run;
> +
> mutex_lock(&vpu->vpu_mutex);
> if (vpu->fw_loaded) {
> mutex_unlock(&vpu->vpu_mutex);
^ permalink raw reply
* [PATCH] [media] platform: constify vb2_ops structures
From: Julia Lawall @ 2016-09-08 23:59 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: kernel-janitors, Fabien Dessenne, linux-samsung-soc,
Krzysztof Kozlowski, Kukjin Kim, Andrzej Hajda, Kamil Debski,
Kyungmin Park, Benoit Parrot, Guennadi Liakhovetski,
Ludovic Desroches, Hyun Kwon, Laurent Pinchart,
Mauro Carvalho Chehab, Michal Simek, Sören Brinkmann,
linux-media, linux-arm-kernel, linux-kernel
Check for vb2_ops structures that are only stored in the ops field of a
vb2_queue structure. That field is declared const, so vb2_ops structures
that have this property can be declared as const also.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct vb2_ops i@p = { ... };
@ok@
identifier r.i;
struct vb2_queue e;
position p;
@@
e.ops = &i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct vb2_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct vb2_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
---
drivers/media/platform/exynos-gsc/gsc-m2m.c | 2 +-
drivers/media/platform/exynos4-is/fimc-capture.c | 2 +-
drivers/media/platform/exynos4-is/fimc-m2m.c | 2 +-
drivers/media/platform/m2m-deinterlace.c | 2 +-
drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c | 2 +-
drivers/media/platform/mx2_emmaprp.c | 2 +-
drivers/media/platform/rcar-vin/rcar-dma.c | 2 +-
drivers/media/platform/rcar_jpu.c | 2 +-
drivers/media/platform/s5p-g2d/g2d.c | 2 +-
drivers/media/platform/s5p-jpeg/jpeg-core.c | 2 +-
drivers/media/platform/sh_vou.c | 2 +-
drivers/media/platform/soc_camera/atmel-isi.c | 2 +-
drivers/media/platform/soc_camera/rcar_vin.c | 2 +-
drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 2 +-
drivers/media/platform/sti/bdisp/bdisp-v4l2.c | 2 +-
drivers/media/platform/ti-vpe/cal.c | 2 +-
drivers/media/platform/ti-vpe/vpe.c | 2 +-
drivers/media/platform/vim2m.c | 2 +-
drivers/media/platform/xilinx/xilinx-dma.c | 2 +-
19 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/media/platform/xilinx/xilinx-dma.c b/drivers/media/platform/xilinx/xilinx-dma.c
index 7ae1a13..1d5836c 100644
--- a/drivers/media/platform/xilinx/xilinx-dma.c
+++ b/drivers/media/platform/xilinx/xilinx-dma.c
@@ -474,7 +474,7 @@ static void xvip_dma_stop_streaming(struct vb2_queue *vq)
spin_unlock_irq(&dma->queued_lock);
}
-static struct vb2_ops xvip_dma_queue_qops = {
+static const struct vb2_ops xvip_dma_queue_qops = {
.queue_setup = xvip_dma_queue_setup,
.buf_prepare = xvip_dma_buffer_prepare,
.buf_queue = xvip_dma_buffer_queue,
diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c
index 30211f6..46de657 100644
--- a/drivers/media/platform/soc_camera/atmel-isi.c
+++ b/drivers/media/platform/soc_camera/atmel-isi.c
@@ -536,7 +536,7 @@ static void stop_streaming(struct vb2_queue *vq)
pm_runtime_put(ici->v4l2_dev.dev);
}
-static struct vb2_ops isi_video_qops = {
+static const struct vb2_ops isi_video_qops = {
.queue_setup = queue_setup,
.buf_init = buffer_init,
.buf_prepare = buffer_prepare,
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index 785e693..d9c07b8 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -2538,7 +2538,7 @@ static void s5p_jpeg_stop_streaming(struct vb2_queue *q)
pm_runtime_put(ctx->jpeg->dev);
}
-static struct vb2_ops s5p_jpeg_qops = {
+static const struct vb2_ops s5p_jpeg_qops = {
.queue_setup = s5p_jpeg_queue_setup,
.buf_prepare = s5p_jpeg_buf_prepare,
.buf_queue = s5p_jpeg_buf_queue,
diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
index e967fcf..44323cb 100644
--- a/drivers/media/platform/ti-vpe/cal.c
+++ b/drivers/media/platform/ti-vpe/cal.c
@@ -1379,7 +1379,7 @@ static void cal_stop_streaming(struct vb2_queue *vq)
cal_runtime_put(ctx->dev);
}
-static struct vb2_ops cal_video_qops = {
+static const struct vb2_ops cal_video_qops = {
.queue_setup = cal_queue_setup,
.buf_prepare = cal_buffer_prepare,
.buf_queue = cal_buffer_queue,
diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c
index 55a1458..0189f7f 100644
--- a/drivers/media/platform/ti-vpe/vpe.c
+++ b/drivers/media/platform/ti-vpe/vpe.c
@@ -1878,7 +1878,7 @@ static void vpe_stop_streaming(struct vb2_queue *q)
vpdma_dump_regs(ctx->dev->vpdma);
}
-static struct vb2_ops vpe_qops = {
+static const struct vb2_ops vpe_qops = {
.queue_setup = vpe_queue_setup,
.buf_prepare = vpe_buf_prepare,
.buf_queue = vpe_buf_queue,
diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c
index 9c13752..0009fc5 100644
--- a/drivers/media/platform/soc_camera/rcar_vin.c
+++ b/drivers/media/platform/soc_camera/rcar_vin.c
@@ -856,7 +856,7 @@ static void rcar_vin_stop_streaming(struct vb2_queue *vq)
spin_unlock_irq(&priv->lock);
}
-static struct vb2_ops rcar_vin_vb2_ops = {
+static const struct vb2_ops rcar_vin_vb2_ops = {
.queue_setup = rcar_vin_videobuf_setup,
.buf_queue = rcar_vin_videobuf_queue,
.stop_streaming = rcar_vin_stop_streaming,
diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
index 02b519d..02c8dc5 100644
--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
+++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
@@ -470,7 +470,7 @@ static void sh_mobile_ceu_stop_streaming(struct vb2_queue *q)
sh_mobile_ceu_soft_reset(pcdev);
}
-static struct vb2_ops sh_mobile_ceu_videobuf_ops = {
+static const struct vb2_ops sh_mobile_ceu_videobuf_ops = {
.queue_setup = sh_mobile_ceu_videobuf_setup,
.buf_prepare = sh_mobile_ceu_videobuf_prepare,
.buf_queue = sh_mobile_ceu_videobuf_queue,
diff --git a/drivers/media/platform/s5p-g2d/g2d.c b/drivers/media/platform/s5p-g2d/g2d.c
index 391dd7a..62c0dec 100644
--- a/drivers/media/platform/s5p-g2d/g2d.c
+++ b/drivers/media/platform/s5p-g2d/g2d.c
@@ -138,7 +138,7 @@ static void g2d_buf_queue(struct vb2_buffer *vb)
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
-static struct vb2_ops g2d_qops = {
+static const struct vb2_ops g2d_qops = {
.queue_setup = g2d_queue_setup,
.buf_prepare = g2d_buf_prepare,
.buf_queue = g2d_buf_queue,
diff --git a/drivers/media/platform/rcar_jpu.c b/drivers/media/platform/rcar_jpu.c
index 16782ce..d1746ec 100644
--- a/drivers/media/platform/rcar_jpu.c
+++ b/drivers/media/platform/rcar_jpu.c
@@ -1183,7 +1183,7 @@ static void jpu_stop_streaming(struct vb2_queue *vq)
}
}
-static struct vb2_ops jpu_qops = {
+static const struct vb2_ops jpu_qops = {
.queue_setup = jpu_queue_setup,
.buf_prepare = jpu_buf_prepare,
.buf_queue = jpu_buf_queue,
diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c b/drivers/media/platform/exynos-gsc/gsc-m2m.c
index ec6494c..a341a7f 100644
--- a/drivers/media/platform/exynos-gsc/gsc-m2m.c
+++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c
@@ -261,7 +261,7 @@ static void gsc_m2m_buf_queue(struct vb2_buffer *vb)
v4l2_m2m_buf_queue(ctx->m2m_ctx, vbuf);
}
-static struct vb2_ops gsc_m2m_qops = {
+static const struct vb2_ops gsc_m2m_qops = {
.queue_setup = gsc_m2m_queue_setup,
.buf_prepare = gsc_m2m_buf_prepare,
.buf_queue = gsc_m2m_buf_queue,
diff --git a/drivers/media/platform/sh_vou.c b/drivers/media/platform/sh_vou.c
index e1f39b4..1ec9a2e 100644
--- a/drivers/media/platform/sh_vou.c
+++ b/drivers/media/platform/sh_vou.c
@@ -362,7 +362,7 @@ static void sh_vou_stop_streaming(struct vb2_queue *vq)
spin_unlock_irqrestore(&vou_dev->lock, flags);
}
-static struct vb2_ops sh_vou_qops = {
+static const struct vb2_ops sh_vou_qops = {
.queue_setup = sh_vou_queue_setup,
.buf_prepare = sh_vou_buf_prepare,
.buf_queue = sh_vou_buf_queue,
diff --git a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
index 3b1ac68..45f82b5 100644
--- a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
+++ b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
@@ -527,7 +527,7 @@ static void bdisp_stop_streaming(struct vb2_queue *q)
pm_runtime_put(ctx->bdisp_dev->dev);
}
-static struct vb2_ops bdisp_qops = {
+static const struct vb2_ops bdisp_qops = {
.queue_setup = bdisp_queue_setup,
.buf_prepare = bdisp_buf_prepare,
.buf_queue = bdisp_buf_queue,
diff --git a/drivers/media/platform/m2m-deinterlace.c b/drivers/media/platform/m2m-deinterlace.c
index 0fcb5c78..0870fad 100644
--- a/drivers/media/platform/m2m-deinterlace.c
+++ b/drivers/media/platform/m2m-deinterlace.c
@@ -852,7 +852,7 @@ static void deinterlace_buf_queue(struct vb2_buffer *vb)
v4l2_m2m_buf_queue(ctx->m2m_ctx, vbuf);
}
-static struct vb2_ops deinterlace_qops = {
+static const struct vb2_ops deinterlace_qops = {
.queue_setup = deinterlace_queue_setup,
.buf_prepare = deinterlace_buf_prepare,
.buf_queue = deinterlace_buf_queue,
diff --git a/drivers/media/platform/mx2_emmaprp.c b/drivers/media/platform/mx2_emmaprp.c
index c639406..e68d271 100644
--- a/drivers/media/platform/mx2_emmaprp.c
+++ b/drivers/media/platform/mx2_emmaprp.c
@@ -743,7 +743,7 @@ static void emmaprp_buf_queue(struct vb2_buffer *vb)
v4l2_m2m_buf_queue(ctx->m2m_ctx, vbuf);
}
-static struct vb2_ops emmaprp_qops = {
+static const struct vb2_ops emmaprp_qops = {
.queue_setup = emmaprp_queue_setup,
.buf_prepare = emmaprp_buf_prepare,
.buf_queue = emmaprp_buf_queue,
diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
index 496aa97..07c07c1 100644
--- a/drivers/media/platform/rcar-vin/rcar-dma.c
+++ b/drivers/media/platform/rcar-vin/rcar-dma.c
@@ -1116,7 +1116,7 @@ static void rvin_stop_streaming(struct vb2_queue *vq)
rvin_disable_interrupts(vin);
}
-static struct vb2_ops rvin_qops = {
+static const struct vb2_ops rvin_qops = {
.queue_setup = rvin_queue_setup,
.buf_prepare = rvin_buffer_prepare,
.buf_queue = rvin_buffer_queue,
diff --git a/drivers/media/platform/vim2m.c b/drivers/media/platform/vim2m.c
index cd0ff4a..a98f679 100644
--- a/drivers/media/platform/vim2m.c
+++ b/drivers/media/platform/vim2m.c
@@ -815,7 +815,7 @@ static void vim2m_stop_streaming(struct vb2_queue *q)
}
}
-static struct vb2_ops vim2m_qops = {
+static const struct vb2_ops vim2m_qops = {
.queue_setup = vim2m_queue_setup,
.buf_prepare = vim2m_buf_prepare,
.buf_queue = vim2m_buf_queue,
diff --git a/drivers/media/platform/exynos4-is/fimc-capture.c b/drivers/media/platform/exynos4-is/fimc-capture.c
index fdec499..344028e 100644
--- a/drivers/media/platform/exynos4-is/fimc-capture.c
+++ b/drivers/media/platform/exynos4-is/fimc-capture.c
@@ -452,7 +452,7 @@ static void buffer_queue(struct vb2_buffer *vb)
spin_unlock_irqrestore(&fimc->slock, flags);
}
-static struct vb2_ops fimc_capture_qops = {
+static const struct vb2_ops fimc_capture_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_queue = buffer_queue,
diff --git a/drivers/media/platform/exynos4-is/fimc-m2m.c b/drivers/media/platform/exynos4-is/fimc-m2m.c
index b1309e1..6028e4f 100644
--- a/drivers/media/platform/exynos4-is/fimc-m2m.c
+++ b/drivers/media/platform/exynos4-is/fimc-m2m.c
@@ -219,7 +219,7 @@ static void fimc_buf_queue(struct vb2_buffer *vb)
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
}
-static struct vb2_ops fimc_qops = {
+static const struct vb2_ops fimc_qops = {
.queue_setup = fimc_queue_setup,
.buf_prepare = fimc_buf_prepare,
.buf_queue = fimc_buf_queue,
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
index 3ed3f2d..f8e4611 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
@@ -864,7 +864,7 @@ static void vb2ops_venc_stop_streaming(struct vb2_queue *q)
ctx->state = MTK_STATE_FREE;
}
-static struct vb2_ops mtk_venc_vb2_ops = {
+static const struct vb2_ops mtk_venc_vb2_ops = {
.queue_setup = vb2ops_venc_queue_setup,
.buf_prepare = vb2ops_venc_buf_prepare,
.buf_queue = vb2ops_venc_buf_queue,
^ permalink raw reply related
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