* RE: [PATCH v2 1/5] scsi: ufs-mediatek: Fix imprecise waiting time for ref-clk control
From: Stanley Chu @ 2020-05-31 13:45 UTC (permalink / raw)
To: Avri Altman
Cc: pengshun.zhao@mediatek.com, linux-scsi@vger.kernel.org,
martin.petersen@oracle.com, andy.teng@mediatek.com,
jejb@linux.ibm.com, chun-hung.wu@mediatek.com,
kuohong.wang@mediatek.com, linux-kernel@vger.kernel.org,
cc.chou@mediatek.com, cang@codeaurora.org,
linux-mediatek@lists.infradead.org, peter.wang@mediatek.com,
alim.akhtar@samsung.com, matthias.bgg@gmail.com,
beanhuo@micron.com, chaotian.jing@mediatek.com,
bvanassche@acm.org, linux-arm-kernel@lists.infradead.org,
asutoshd@codeaurora.org
In-Reply-To: <SN6PR04MB464015BDF84DF7A9779BEB41FC8D0@SN6PR04MB4640.namprd04.prod.outlook.com>
Hi Avri,
On Sun, 2020-05-31 at 07:10 +0000, Avri Altman wrote:
> >
> > Currently ref-clk control timeout is implemented by Jiffies. However
> > jiffies is not accurate enough thus "false timeout" may happen.
> >
> > Use more accurate delay mechanism instead, for example, ktime.
> >
> > Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> > Reviewed-by: Andy Teng <andy.teng@mediatek.com>
> Reviewed-by: Avri Altman <avri.altman@wdc.com>
>
Thanks for your review.
> >
> > /* Wait for ack */
> > - timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS);
> > + timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
> > do {
> > + time_checked = ktime_get();
> > value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
> >
> > /* Wait until ack bit equals to req bit */
> > @@ -144,7 +145,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba,
> > bool on)
> > goto out;
> >
> > usleep_range(100, 200);
> > - } while (time_before(jiffies, timeout));
> > + } while (ktime_before(time_checked, timeout));
> Nit: you could get rid of time_checked if you would use ktime_compare(ktime_get(), timeout) > 0
>
> Thanks,
> Avri
If this context is preempted and scheduled out between ufshcd_readl()
and ktime_compare(ktime_get(), timeout), then the ktime_get() may get a
"timed-out" time even though the last ufshcd_readl() is actually
executed before the "timed-out" time. In this case, false alarm will
show up. Using "time_checked" here could solve above issue.
Thanks,
Stanley Chu
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^ permalink raw reply
* Re: [PATCH] MIPS: ralink: drop ralink_clk_init for mt7621
From: Thomas Bogendoerfer @ 2020-05-31 12:32 UTC (permalink / raw)
To: Chuanhong Guo; +Cc: linux-kernel, linux-mediatek, linux-mips, John Crispin
In-Reply-To: <20200328041523.81229-1-gch981213@gmail.com>
On Sat, Mar 28, 2020 at 12:14:57PM +0800, Chuanhong Guo wrote:
> ralink_clk_init is only called in arch/mips/ralink/clk.c which isn't
> compiled for mt7621. And it doesn't export a proper cpu clock.
> Drop this unused function.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> ---
> arch/mips/ralink/mt7621.c | 43 ---------------------------------------
> 1 file changed, 43 deletions(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
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^ permalink raw reply
* RE: [PATCH v2 1/5] scsi: ufs-mediatek: Fix imprecise waiting time for ref-clk control
From: Avri Altman @ 2020-05-31 7:10 UTC (permalink / raw)
To: Stanley Chu, linux-scsi@vger.kernel.org,
martin.petersen@oracle.com, alim.akhtar@samsung.com,
jejb@linux.ibm.com
Cc: pengshun.zhao@mediatek.com, bvanassche@acm.org,
andy.teng@mediatek.com, cc.chou@mediatek.com,
chun-hung.wu@mediatek.com, kuohong.wang@mediatek.com,
linux-kernel@vger.kernel.org, cang@codeaurora.org,
linux-mediatek@lists.infradead.org, peter.wang@mediatek.com,
matthias.bgg@gmail.com, beanhuo@micron.com,
chaotian.jing@mediatek.com, linux-arm-kernel@lists.infradead.org,
asutoshd@codeaurora.org
In-Reply-To: <20200529092310.1106-2-stanley.chu@mediatek.com>
>
> Currently ref-clk control timeout is implemented by Jiffies. However
> jiffies is not accurate enough thus "false timeout" may happen.
>
> Use more accurate delay mechanism instead, for example, ktime.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> Reviewed-by: Andy Teng <andy.teng@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
> ---
> drivers/scsi/ufs/ufs-mediatek.c | 7 ++++---
> drivers/scsi/ufs/ufs-mediatek.h | 2 +-
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
> index d56ce8d97d4e..523ee5573921 100644
> --- a/drivers/scsi/ufs/ufs-mediatek.c
> +++ b/drivers/scsi/ufs/ufs-mediatek.c
> @@ -120,7 +120,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba,
> bool on)
> {
> struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> struct arm_smccc_res res;
> - unsigned long timeout;
> + ktime_t timeout, time_checked;
> u32 value;
>
> if (host->ref_clk_enabled == on)
> @@ -135,8 +135,9 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba,
> bool on)
> }
>
> /* Wait for ack */
> - timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS);
> + timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
> do {
> + time_checked = ktime_get();
> value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
>
> /* Wait until ack bit equals to req bit */
> @@ -144,7 +145,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba,
> bool on)
> goto out;
>
> usleep_range(100, 200);
> - } while (time_before(jiffies, timeout));
> + } while (ktime_before(time_checked, timeout));
Nit: you could get rid of time_checked if you would use ktime_compare(ktime_get(), timeout) > 0
Thanks,
Avri
>
> dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
>
> diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h
> index 5bbd3e9cbae2..fc42dcbfd800 100644
> --- a/drivers/scsi/ufs/ufs-mediatek.h
> +++ b/drivers/scsi/ufs/ufs-mediatek.h
> @@ -28,7 +28,7 @@
> #define REFCLK_REQUEST BIT(0)
> #define REFCLK_ACK BIT(1)
>
> -#define REFCLK_REQ_TIMEOUT_MS 3
> +#define REFCLK_REQ_TIMEOUT_US 3000
>
> /*
> * Vendor specific pre-defined parameters
> --
> 2.18.0
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^ permalink raw reply
* RE: [PATCH] scsi: ufs: Remove redundant urgent_bkop_lvl initialization
From: Avri Altman @ 2020-05-30 20:43 UTC (permalink / raw)
To: Stanley Chu, linux-scsi@vger.kernel.org,
martin.petersen@oracle.com, alim.akhtar@samsung.com,
jejb@linux.ibm.com
Cc: bvanassche@acm.org, andy.teng@mediatek.com, cc.chou@mediatek.com,
chun-hung.wu@mediatek.com, kuohong.wang@mediatek.com,
linux-kernel@vger.kernel.org, cang@codeaurora.org,
linux-mediatek@lists.infradead.org, peter.wang@mediatek.com,
matthias.bgg@gmail.com, beanhuo@micron.com,
chaotian.jing@mediatek.com, linux-arm-kernel@lists.infradead.org,
asutoshd@codeaurora.org
In-Reply-To: <20200530141200.4616-1-stanley.chu@mediatek.com>
>
> In ufshcd_probe_hba(), all BKOP SW tracking variables can be reset
> together in ufshcd_force_reset_auto_bkops(), thus urgent_bkop_lvl
> initialization in the beginning of ufshcd_probe_hba() can be merged
> into ufshcd_force_reset_auto_bkops().
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
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^ permalink raw reply
* RE: [PATCH v1 1/2] scsi: ufs: Support WriteBooster on Samsung UFS devices
From: Avri Altman @ 2020-05-30 20:37 UTC (permalink / raw)
To: Stanley Chu, linux-scsi@vger.kernel.org,
martin.petersen@oracle.com, alim.akhtar@samsung.com,
jejb@linux.ibm.com
Cc: bvanassche@acm.org, andy.teng@mediatek.com, cc.chou@mediatek.com,
chun-hung.wu@mediatek.com, kuohong.wang@mediatek.com,
linux-kernel@vger.kernel.org, cang@codeaurora.org,
linux-mediatek@lists.infradead.org, peter.wang@mediatek.com,
matthias.bgg@gmail.com, beanhuo@micron.com,
chaotian.jing@mediatek.com, linux-arm-kernel@lists.infradead.org,
asutoshd@codeaurora.org
In-Reply-To: <20200530151337.6182-2-stanley.chu@mediatek.com>
> @@ -2801,11 +2801,17 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum
> query_opcode opcode,
> {
> struct ufs_query_req *request = NULL;
> struct ufs_query_res *response = NULL;
> - int err, selector = 0;
> + int err;
> int timeout = QUERY_REQ_TIMEOUT;
> + u8 selector = 0;
>
> BUG_ON(!hba);
>
> + if (hba->dev_quirks & UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR) {
> + if (ufshcd_is_wb_flags(idn))
> + selector = 1;
> + }
> +
Why not make the caller set the applicable selector,
Instead of checking this for every flag?
> ufshcd_hold(hba, false);
> mutex_lock(&hba->dev_cmd.lock);
> ufshcd_init_query(hba, &request, &response, opcode, idn, index,
> @@ -2882,6 +2888,11 @@ int ufshcd_query_attr(struct ufs_hba *hba, enum
> query_opcode opcode,
> goto out;
> }
>
> + if (hba->dev_quirks & UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR) {
> + if (ufshcd_is_wb_attrs(idn))
> + selector = 1;
> + }
> +
Same here
> mutex_lock(&hba->dev_cmd.lock);
> ufshcd_init_query(hba, &request, &response, opcode, idn, index,
> selector);
> @@ -3042,6 +3053,11 @@ int ufshcd_query_descriptor_retry(struct ufs_hba
> *hba,
> int err;
> int retries;
>
> + if (hba->dev_quirks & UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR) {
> + if (ufshcd_is_wb_desc(idn, index))
> + selector = 1;
> + }
> +
And here.
But this can't be true -
Are you setting the selector = 1 for reading any field for those descriptors?
Shouldn't it be for the wb specific fields?
> for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
> err = __ufshcd_query_descriptor(hba, opcode, idn, index,
> selector, desc_buf, buf_len);
> @@ -6907,8 +6923,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
> size_t buff_len;
> u8 model_index;
> u8 *desc_buf;
> + u8 retry_cnt = 0;
> struct ufs_dev_info *dev_info = &hba->dev_info;
>
> +retry:
> buff_len = max_t(size_t, hba->desc_size.dev_desc,
> QUERY_DESC_MAX_SIZE + 1);
> desc_buf = kmalloc(buff_len, GFP_KERNEL);
> @@ -6948,6 +6966,29 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
>
> ufs_fixup_device_setup(hba);
>
> + if (!retry_cnt && (hba->dev_quirks &
> + UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR)) {
If you only want to enter this clause once - you should use something other than retry_cnt,
Which the reader expects to performs retries....
Also, this is becoming too wired -
From your commit log I get that for specific Samsung devices,
You need to query wb descriptor fields/attributes/flags using selectore = 1.
But what it has to do with descriptor sizes?
> + /*
> + * Update WriteBooster related descriptor length with specific
> + * seletor used.
> + */
> + ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
> + &hba->desc_size.dev_desc);
> + ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION,
> 0,
> + &hba->desc_size.conf_desc);
> + ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
> + &hba->desc_size.unit_desc);
> + ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
> + &hba->desc_size.geom_desc);
> + /*
> + * Read device descriptor again with specific selector used to
> + * get WriteBooster related fileds.
> + */
> + kfree(desc_buf);
> + retry_cnt++;
> + goto retry;
> + }
> +
> /*
> * Probe WB only for UFS-3.1 devices or UFS devices with quirk
> * UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES enabled
> diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
> index bf97d616e597..d850c47e8ae0 100644
> --- a/drivers/scsi/ufs/ufshcd.h
> +++ b/drivers/scsi/ufs/ufshcd.h
> @@ -876,6 +876,26 @@ static inline u8 ufshcd_wb_get_query_index(struct
> ufs_hba *hba)
> return 0;
> }
>
> +static inline bool ufshcd_is_wb_attrs(enum attr_idn idn)
> +{
> + return ((idn >= QUERY_ATTR_IDN_WB_FLUSH_STATUS) &&
> + (idn <= QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE));
> +}
> +
> +static inline bool ufshcd_is_wb_desc(enum desc_idn idn, u8 index)
> +{
> + return (idn <= QUERY_DESC_IDN_CONFIGURATION) ||
> + ((idn == QUERY_DESC_IDN_UNIT) &&
> + (index != UFS_UPIU_RPMB_QUERY_INDEX)) ||
> + (idn == QUERY_DESC_IDN_GEOMETRY);
> +}
> +
> +static inline bool ufshcd_is_wb_flags(enum flag_idn idn)
> +{
> + return ((idn >= QUERY_FLAG_IDN_WB_EN) &&
> + (idn <= QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8));
> +}
> +
> extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
> extern int ufshcd_runtime_resume(struct ufs_hba *hba);
> extern int ufshcd_runtime_idle(struct ufs_hba *hba);
> --
> 2.18.0
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^ permalink raw reply
* Re: [PATCH v6] support gce on mt6779 platform
From: Jassi Brar @ 2020-05-30 20:34 UTC (permalink / raw)
To: Dennis YC Hsieh
Cc: Mark Rutland, Devicetree List, Philipp Zabel, wsd_upstream,
David Airlie, Linux Kernel Mailing List, dri-devel, HS Liao,
CK Hu, Rob Herring, linux-mediatek, Houlong Wei, Daniel Vetter,
Matthias Brugger, Bibby Hsieh, linux-arm-kernel
In-Reply-To: <1590685491-17107-1-git-send-email-dennis-yc.hsieh@mediatek.com>
On Thu, May 28, 2020 at 12:05 PM Dennis YC Hsieh
<dennis-yc.hsieh@mediatek.com> wrote:
>
> This patch support gce on mt6779 platform.
>
> Change since v5:
> - spearate address shift code in client helper and mailbox controller
> - separate write_s/write_s_mask and write_s_value/write_s_mask_value so that
> client can decide use mask or not
> - fix typo in header
>
> Change since v4:
> - do not clear disp event again in drm driver
> - symbolize value 1 to jump relative
>
> [... snip ...]
>
>
>
> Dennis YC Hsieh (16):
> dt-binding: gce: add gce header file for mt6779
> mailbox: cmdq: variablize address shift in platform
> mailbox: cmdq: support mt6779 gce platform definition
> mailbox: mediatek: cmdq: clear task in channel before shutdown
> soc: mediatek: cmdq: return send msg error code
> soc: mediatek: cmdq: add address shift in jump
> soc: mediatek: cmdq: add assign function
> soc: mediatek: cmdq: add write_s function
> soc: mediatek: cmdq: add write_s_mask function
> soc: mediatek: cmdq: add read_s function
> soc: mediatek: cmdq: add write_s value function
> soc: mediatek: cmdq: add write_s_mask value function
> soc: mediatek: cmdq: export finalize function
> soc: mediatek: cmdq: add jump function
> soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api
> soc: mediatek: cmdq: add set event function
>
> .../devicetree/bindings/mailbox/mtk-gce.txt | 8 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +-
> drivers/mailbox/mtk-cmdq-mailbox.c | 101 ++++++--
> drivers/soc/mediatek/mtk-cmdq-helper.c | 163 ++++++++++++-
> include/dt-bindings/gce/mt6779-gce.h | 222 ++++++++++++++++++
> include/linux/mailbox/mtk-cmdq-mailbox.h | 10 +-
> include/linux/soc/mediatek/mtk-cmdq.h | 125 +++++++++-
>
Please break the patchset into two. The lower mailbox related changes
with soc changes on top.
thanks
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* RE: [PATCH v1 0/2] scsi: ufs: Support WriteBooster on Samsung UFS devices
From: Avri Altman @ 2020-05-30 20:03 UTC (permalink / raw)
To: Stanley Chu, linux-scsi@vger.kernel.org,
martin.petersen@oracle.com, alim.akhtar@samsung.com,
jejb@linux.ibm.com
Cc: bvanassche@acm.org, andy.teng@mediatek.com, cc.chou@mediatek.com,
chun-hung.wu@mediatek.com, kuohong.wang@mediatek.com,
linux-kernel@vger.kernel.org, cang@codeaurora.org,
linux-mediatek@lists.infradead.org, peter.wang@mediatek.com,
matthias.bgg@gmail.com, beanhuo@micron.com,
chaotian.jing@mediatek.com, linux-arm-kernel@lists.infradead.org,
asutoshd@codeaurora.org
In-Reply-To: <20200530151337.6182-1-stanley.chu@mediatek.com>
>
> Hi,
> Samsung UFS devices are widely used in the market, however these devices
> need some special handling to support WriteBooster. Introduce a device quirk
> to handle this special requirement.
>
> Currently Bean Huo is doing some nice cleanup work for device descriptor
> length so our series will have merge conflict. I would like to submit this series
> first for review and then resend with conflict fix after Bean's series gets
> accepted.
Maybe better to wait few days for that series to be accepted ?
Thanks,
Avri
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* Re: [PATCH v9 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D
From: Tudor.Ambarus @ 2020-05-30 18:50 UTC (permalink / raw)
To: p.yadav
Cc: alexandre.belloni, masonccyang, vigneshr, richard, nsekhar,
Nicolas.Ferre, boris.brezillon, michal.simek, Ludovic.Desroches,
broonie, linux-mtd, linux-arm-kernel, miquel.raynal, matthias.bgg,
linux-mediatek, linux-spi, linux-kernel
In-Reply-To: <20200525091544.17270-8-p.yadav@ti.com>
On Monday, May 25, 2020 12:15:32 PM EEST Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to
> reflect that.
>
> The check for rev A or later compared the BFPT header length with the
> maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so
> was the BFPT length for both rev A and B, this check worked fine. But
> now, since BFPT_DWORD_MAX is 20, it means this check will also stop BFPT
> parsing for rev A or B, since their length is 16.
>
> So, instead check for BFPT_DWORD_MAX_JESD216 to stop BFPT parsing for
> the first JESD216 version, and check for BFPT_DWORD_MAX_JESD216B for the
> next two versions.
>
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> drivers/mtd/spi-nor/sfdp.c | 7 ++++++-
> drivers/mtd/spi-nor/sfdp.h | 5 +++--
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 5cecc4ba2141..96960f2f3d7a 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -549,7 +549,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> SNOR_ERASE_TYPE_MASK;
>
> /* Stop here if not JESD216 rev A or later. */
> - if (bfpt_header->length < BFPT_DWORD_MAX)
> + if (bfpt_header->length == BFPT_DWORD_MAX_JESD216)
> return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
> params);
>
> @@ -605,6 +605,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> return -EINVAL;
> }
>
> + /* Stop here if JESD216 rev B. */
Applies for both rev A and rev B. Used the following comment instead:
/* Stop here if not JESD216 rev C or later. */
> + if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B)
> + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
> + params);
> +
> return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
> }
>
> diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
> index e0a8ded04890..f8198af43a63 100644
> --- a/drivers/mtd/spi-nor/sfdp.h
> +++ b/drivers/mtd/spi-nor/sfdp.h
> @@ -10,11 +10,11 @@
> /* Basic Flash Parameter Table */
>
> /*
> - * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
> + * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs.
> * They are indexed from 1 but C arrays are indexed from 0.
> */
> #define BFPT_DWORD(i) ((i) - 1)
> -#define BFPT_DWORD_MAX 16
> +#define BFPT_DWORD_MAX 20
>
> struct sfdp_bfpt {
> u32 dwords[BFPT_DWORD_MAX];
> @@ -22,6 +22,7 @@ struct sfdp_bfpt {
>
> /* The first version of JESD216 defined only 9 DWORDs. */
> #define BFPT_DWORD_MAX_JESD216 9
> +#define BFPT_DWORD_MAX_JESD216B 16
>
> /* 1st DWORD. */
> #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
> --
> 2.26.2
Applied, thanks.
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^ permalink raw reply
* Re: [PATCH v9 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths
From: Tudor.Ambarus @ 2020-05-30 18:49 UTC (permalink / raw)
To: p.yadav
Cc: alexandre.belloni, masonccyang, vigneshr, richard, nsekhar,
Nicolas.Ferre, boris.brezillon, michal.simek, Ludovic.Desroches,
broonie, linux-mtd, linux-arm-kernel, miquel.raynal, matthias.bgg,
linux-mediatek, linux-spi, linux-kernel
In-Reply-To: <20200525091544.17270-7-p.yadav@ti.com>
On Monday, May 25, 2020 12:15:31 PM EEST Pratyush Yadav wrote:
> JESD216D.01 says that when the address width can be 3 or 4, it defaults
> to 3 and enters 4-byte mode when given the appropriate command. So, when
> we see a configurable width, default to 3 and let flash that default to
> 4 change it in a post-bfpt fixup.
>
> This fixes SMPT parsing for flashes with configurable address width. If
> the SMPT descriptor advertises variable address width, we use
> nor->addr_width as the address width. But since it was not set to any
> value from the SFDP table, the read command uses an address width of 0,
> resulting in an incorrect read being issued.
>
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> drivers/mtd/spi-nor/sfdp.c | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
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^ permalink raw reply
* Re: [PATCH v9 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal
From: Tudor.Ambarus @ 2020-05-30 18:42 UTC (permalink / raw)
To: p.yadav
Cc: alexandre.belloni, masonccyang, vigneshr, richard, nsekhar,
Nicolas.Ferre, boris.brezillon, michal.simek, Ludovic.Desroches,
broonie, linux-mtd, linux-arm-kernel, miquel.raynal, matthias.bgg,
linux-mediatek, linux-spi, linux-kernel
In-Reply-To: <20200525091544.17270-14-p.yadav@ti.com>
On Monday, May 25, 2020 12:15:38 PM EEST Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The Micron MT35XU512ABA flash does not support the quad enable bit. But
> instead of programming the Quad Enable Require field to 000b ("Device
> does not have a QE bit"), it is programmed to 111b ("Reserved").
>
> While this is technically incorrect, it is not reason enough to abort
> BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
> enable bit present.
>
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> drivers/mtd/spi-nor/sfdp.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 052cabb52df9..9fd3d8d9a127 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -576,10 +576,6 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
>
> /* Quad Enable Requirements. */
> switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
> - case BFPT_DWORD15_QER_NONE:
> - params->quad_enable = NULL;
> - break;
> -
> case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
> /*
> * Writing only one byte to the Status Register has the
> @@ -616,8 +612,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> break;
>
> + case BFPT_DWORD15_QER_NONE:
> default:
> - return -EINVAL;
> + params->quad_enable = NULL;
> + break;
I would just add a dev_dbg message and break the switch.
dev_dbg(nor->dev, "BFPT QER reserved value used.\n");
break;
You will then have to set params->quad_enable = NULL; in a post_bfpt hook.
Cheers,
ta
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^ permalink raw reply
* [PATCH v1 0/2] scsi: ufs: Support WriteBooster on Samsung UFS devices
From: Stanley Chu @ 2020-05-30 15:13 UTC (permalink / raw)
To: linux-scsi, martin.petersen, avri.altman, alim.akhtar, jejb
Cc: Stanley Chu, bvanassche, andy.teng, cc.chou, chun-hung.wu,
kuohong.wang, linux-kernel, cang, linux-mediatek, peter.wang,
matthias.bgg, beanhuo, chaotian.jing, linux-arm-kernel, asutoshd
Hi,
Samsung UFS devices are widely used in the market, however these devices need some special handling to support WriteBooster. Introduce a device quirk to handle this special requirement.
Currently Bean Huo is doing some nice cleanup work for device descriptor length so our series will have merge conflict. I would like to submit this series first for review and then resend with conflict fix after Bean's series gets accepted.
Stanley Chu (2):
scsi: ufs: Support WriteBooster on Samsung UFS devices
scsi: ufs-mediatek: Support WriteBooster on Samsung UFS devices
drivers/scsi/ufs/ufs-mediatek.c | 3 +++
drivers/scsi/ufs/ufs-sysfs.c | 12 ---------
drivers/scsi/ufs/ufs.h | 1 +
drivers/scsi/ufs/ufs_quirks.h | 7 +++++
drivers/scsi/ufs/ufshcd.c | 45 ++++++++++++++++++++++++++++++++-
drivers/scsi/ufs/ufshcd.h | 20 +++++++++++++++
6 files changed, 75 insertions(+), 13 deletions(-)
--
2.18.0
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^ permalink raw reply
* [PATCH v1 2/2] scsi: ufs-mediatek: Support WriteBooster on Samsung UFS devices
From: Stanley Chu @ 2020-05-30 15:13 UTC (permalink / raw)
To: linux-scsi, martin.petersen, avri.altman, alim.akhtar, jejb
Cc: Stanley Chu, bvanassche, andy.teng, cc.chou, chun-hung.wu,
kuohong.wang, linux-kernel, cang, linux-mediatek, peter.wang,
matthias.bgg, beanhuo, chaotian.jing, linux-arm-kernel, asutoshd
In-Reply-To: <20200530151337.6182-1-stanley.chu@mediatek.com>
Add device quirk "UFS_DEVICE_QUIRK_WB_USING_SPECIAL_SELECTOR"
on all Samsung UFS devices to enable WriteBooster on those
devices.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
drivers/scsi/ufs/ufs-mediatek.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
index d587b3276aa8..078a1e3d05d3 100644
--- a/drivers/scsi/ufs/ufs-mediatek.c
+++ b/drivers/scsi/ufs/ufs-mediatek.c
@@ -32,6 +32,9 @@
ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res)
static struct ufs_dev_fix ufs_mtk_dev_fixups[] = {
+ UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
+ UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES |
+ UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR),
UFS_FIX(UFS_VENDOR_SKHYNIX, "H9HQ21AFAMZDAR",
UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES),
END_FIX
--
2.18.0
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^ permalink raw reply related
* [PATCH v1 1/2] scsi: ufs: Support WriteBooster on Samsung UFS devices
From: Stanley Chu @ 2020-05-30 15:13 UTC (permalink / raw)
To: linux-scsi, martin.petersen, avri.altman, alim.akhtar, jejb
Cc: Stanley Chu, bvanassche, andy.teng, cc.chou, chun-hung.wu,
kuohong.wang, linux-kernel, cang, linux-mediatek, peter.wang,
matthias.bgg, beanhuo, chaotian.jing, linux-arm-kernel, asutoshd
In-Reply-To: <20200530151337.6182-1-stanley.chu@mediatek.com>
Samsung UFS devices are widely used in the market, however these
devices need some special handling to support WriteBooster.
The major part is that Samsung UFS devices need to use specific
"selector" value for WriteBooster related query operations. Therefore,
introduce a device quirk to handle the special requirement and then
WriteBooster can be enabled on these devices.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
drivers/scsi/ufs/ufs-sysfs.c | 12 ----------
drivers/scsi/ufs/ufs.h | 1 +
drivers/scsi/ufs/ufs_quirks.h | 7 ++++++
drivers/scsi/ufs/ufshcd.c | 43 ++++++++++++++++++++++++++++++++++-
drivers/scsi/ufs/ufshcd.h | 20 ++++++++++++++++
5 files changed, 70 insertions(+), 13 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-sysfs.c b/drivers/scsi/ufs/ufs-sysfs.c
index 2d71d232a69d..fa5fdfcd2611 100644
--- a/drivers/scsi/ufs/ufs-sysfs.c
+++ b/drivers/scsi/ufs/ufs-sysfs.c
@@ -622,12 +622,6 @@ static const struct attribute_group ufs_sysfs_string_descriptors_group = {
.attrs = ufs_sysfs_string_descriptors,
};
-static inline bool ufshcd_is_wb_flags(enum flag_idn idn)
-{
- return ((idn >= QUERY_FLAG_IDN_WB_EN) &&
- (idn <= QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8));
-}
-
#define UFS_FLAG(_name, _uname) \
static ssize_t _name##_show(struct device *dev, \
struct device_attribute *attr, char *buf) \
@@ -680,12 +674,6 @@ static const struct attribute_group ufs_sysfs_flags_group = {
.attrs = ufs_sysfs_device_flags,
};
-static inline bool ufshcd_is_wb_attrs(enum attr_idn idn)
-{
- return ((idn >= QUERY_ATTR_IDN_WB_FLUSH_STATUS) &&
- (idn <= QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE));
-}
-
#define UFS_ATTRIBUTE(_name, _uname) \
static ssize_t _name##_show(struct device *dev, \
struct device_attribute *attr, char *buf) \
diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
index c70845d41449..88ec87e2811c 100644
--- a/drivers/scsi/ufs/ufs.h
+++ b/drivers/scsi/ufs/ufs.h
@@ -61,6 +61,7 @@
* This means max. LUN number reported from UFS device could be 0xC17F.
*/
#define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
+#define UFS_UPIU_RPMB_QUERY_INDEX 0xC4
#define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
#define UFS_UPIU_WLUN_ID (1 << 7)
diff --git a/drivers/scsi/ufs/ufs_quirks.h b/drivers/scsi/ufs/ufs_quirks.h
index e3175a63c676..f9ed868cf330 100644
--- a/drivers/scsi/ufs/ufs_quirks.h
+++ b/drivers/scsi/ufs/ufs_quirks.h
@@ -108,4 +108,11 @@ struct ufs_dev_fix {
*/
#define UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES (1 << 10)
+/*
+ * Some UFS devices need to use special selector to operate WriteBooster
+ * related flags and attributes. Enable this quirk to make these devices
+ * work normally.
+ */
+#define UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR (1 << 11)
+
#endif /* UFS_QUIRKS_H_ */
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index f11be69e50e9..5e38c471877c 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2801,11 +2801,17 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
{
struct ufs_query_req *request = NULL;
struct ufs_query_res *response = NULL;
- int err, selector = 0;
+ int err;
int timeout = QUERY_REQ_TIMEOUT;
+ u8 selector = 0;
BUG_ON(!hba);
+ if (hba->dev_quirks & UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR) {
+ if (ufshcd_is_wb_flags(idn))
+ selector = 1;
+ }
+
ufshcd_hold(hba, false);
mutex_lock(&hba->dev_cmd.lock);
ufshcd_init_query(hba, &request, &response, opcode, idn, index,
@@ -2882,6 +2888,11 @@ int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
goto out;
}
+ if (hba->dev_quirks & UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR) {
+ if (ufshcd_is_wb_attrs(idn))
+ selector = 1;
+ }
+
mutex_lock(&hba->dev_cmd.lock);
ufshcd_init_query(hba, &request, &response, opcode, idn, index,
selector);
@@ -3042,6 +3053,11 @@ int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
int err;
int retries;
+ if (hba->dev_quirks & UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR) {
+ if (ufshcd_is_wb_desc(idn, index))
+ selector = 1;
+ }
+
for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
err = __ufshcd_query_descriptor(hba, opcode, idn, index,
selector, desc_buf, buf_len);
@@ -6907,8 +6923,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
size_t buff_len;
u8 model_index;
u8 *desc_buf;
+ u8 retry_cnt = 0;
struct ufs_dev_info *dev_info = &hba->dev_info;
+retry:
buff_len = max_t(size_t, hba->desc_size.dev_desc,
QUERY_DESC_MAX_SIZE + 1);
desc_buf = kmalloc(buff_len, GFP_KERNEL);
@@ -6948,6 +6966,29 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
ufs_fixup_device_setup(hba);
+ if (!retry_cnt && (hba->dev_quirks &
+ UFS_DEVICE_QUIRK_WB_SPECIAL_SELECTOR)) {
+ /*
+ * Update WriteBooster related descriptor length with specific
+ * seletor used.
+ */
+ ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
+ &hba->desc_size.dev_desc);
+ ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
+ &hba->desc_size.conf_desc);
+ ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
+ &hba->desc_size.unit_desc);
+ ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
+ &hba->desc_size.geom_desc);
+ /*
+ * Read device descriptor again with specific selector used to
+ * get WriteBooster related fileds.
+ */
+ kfree(desc_buf);
+ retry_cnt++;
+ goto retry;
+ }
+
/*
* Probe WB only for UFS-3.1 devices or UFS devices with quirk
* UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES enabled
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index bf97d616e597..d850c47e8ae0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -876,6 +876,26 @@ static inline u8 ufshcd_wb_get_query_index(struct ufs_hba *hba)
return 0;
}
+static inline bool ufshcd_is_wb_attrs(enum attr_idn idn)
+{
+ return ((idn >= QUERY_ATTR_IDN_WB_FLUSH_STATUS) &&
+ (idn <= QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE));
+}
+
+static inline bool ufshcd_is_wb_desc(enum desc_idn idn, u8 index)
+{
+ return (idn <= QUERY_DESC_IDN_CONFIGURATION) ||
+ ((idn == QUERY_DESC_IDN_UNIT) &&
+ (index != UFS_UPIU_RPMB_QUERY_INDEX)) ||
+ (idn == QUERY_DESC_IDN_GEOMETRY);
+}
+
+static inline bool ufshcd_is_wb_flags(enum flag_idn idn)
+{
+ return ((idn >= QUERY_FLAG_IDN_WB_EN) &&
+ (idn <= QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8));
+}
+
extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
extern int ufshcd_runtime_resume(struct ufs_hba *hba);
extern int ufshcd_runtime_idle(struct ufs_hba *hba);
--
2.18.0
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^ permalink raw reply related
* [PATCH] scsi: ufs: Remove redundant urgent_bkop_lvl initialization
From: Stanley Chu @ 2020-05-30 14:12 UTC (permalink / raw)
To: linux-scsi, martin.petersen, avri.altman, alim.akhtar, jejb
Cc: Stanley Chu, bvanassche, andy.teng, cc.chou, chun-hung.wu,
kuohong.wang, linux-kernel, cang, linux-mediatek, peter.wang,
matthias.bgg, beanhuo, chaotian.jing, linux-arm-kernel, asutoshd
In ufshcd_probe_hba(), all BKOP SW tracking variables can be reset
together in ufshcd_force_reset_auto_bkops(), thus urgent_bkop_lvl
initialization in the beginning of ufshcd_probe_hba() can be merged
into ufshcd_force_reset_auto_bkops().
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
drivers/scsi/ufs/ufshcd.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 5db18f444ea9..f11be69e50e9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -5076,6 +5076,7 @@ static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
ufshcd_disable_auto_bkops(hba);
}
+ hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
hba->is_urgent_bkops_lvl_checked = false;
}
@@ -7373,10 +7374,6 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
if (ret)
goto out;
- /* set the default level for urgent bkops */
- hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
- hba->is_urgent_bkops_lvl_checked = false;
-
/* Debug counters initialization */
ufshcd_clear_dbg_ufs_stats(hba);
--
2.18.0
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* Re: [PATCH v4 11/17] drm/mediatek: Get rid of mtk_smi_larb_get/put
From: Chun-Kuang Hu @ 2020-05-30 11:08 UTC (permalink / raw)
To: Yong Wu
Cc: Will Deacon, youlin.pei, Nicolas Boichat, Joerg Roedel,
Evan Green, eizan, Matthias Kaehlcke, CK Hu, devicetree,
cui.zhang, Tomasz Figa, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
ming-fan.chen, Linux ARM, anan.sun, acourbot, srv_heupstream,
linux-kernel, chao.hao, iommu, Philipp Zabel, Robin Murphy
In-Reply-To: <1590826218-23653-12-git-send-email-yong.wu@mediatek.com>
Hi, Yong:
Yong Wu <yong.wu@mediatek.com> 於 2020年5月30日 週六 下午4:27寫道：
>
> MediaTek IOMMU has already added the device_link between the consumer
> and smi-larb device. If the drm device call the pm_runtime_get_sync,
> the smi-larb's pm_runtime_get_sync also be called automatically.
>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> CC: CK Hu <ck.hu@mediatek.com>
> CC: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> Reviewed-by: Evan Green <evgreen@chromium.org>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 9 ---------
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 21 ---------------------
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 -
> 3 files changed, 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index c9bc844..d4c4078 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -8,7 +8,6 @@
> #include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include <asm/barrier.h>
> -#include <soc/mediatek/smi.h>
>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_plane_helper.h>
> @@ -532,12 +531,6 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
>
> DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
>
> - ret = mtk_smi_larb_get(comp->larb_dev);
> - if (ret) {
> - DRM_ERROR("Failed to get larb: %d\n", ret);
> - return;
> - }
> -
> ret = pm_runtime_get_sync(comp->dev);
> if (ret < 0)
> DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n",
> @@ -545,7 +538,6 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
>
> ret = mtk_crtc_ddp_hw_init(mtk_crtc);
> if (ret) {
> - mtk_smi_larb_put(comp->larb_dev);
> pm_runtime_put(comp->dev);
> return;
> }
> @@ -582,7 +574,6 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
>
> drm_crtc_vblank_off(crtc);
> mtk_crtc_ddp_hw_fini(mtk_crtc);
> - mtk_smi_larb_put(comp->larb_dev);
> ret = pm_runtime_put(comp->dev);
> if (ret < 0)
> DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n",
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 593027a..a6e7f3a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -432,8 +432,6 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
> const struct mtk_ddp_comp_funcs *funcs)
> {
> enum mtk_ddp_comp_type type;
> - struct device_node *larb_node;
> - struct platform_device *larb_pdev;
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> struct resource res;
> struct cmdq_client_reg cmdq_reg;
> @@ -468,31 +466,12 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
> if (IS_ERR(comp->clk))
> return PTR_ERR(comp->clk);
>
> - /* Only DMA capable components need the LARB property */
> - comp->larb_dev = NULL;
> if (type != MTK_DISP_OVL &&
> type != MTK_DISP_OVL_2L &&
> type != MTK_DISP_RDMA &&
> type != MTK_DISP_WDMA)
> return 0;
>
> - larb_node = of_parse_phandle(node, "mediatek,larb", 0);
> - if (!larb_node) {
> - dev_err(dev,
> - "Missing mediadek,larb phandle in %pOF node\n", node);
> - return -EINVAL;
> - }
> -
> - larb_pdev = of_find_device_by_node(larb_node);
> - if (!larb_pdev) {
> - dev_warn(dev, "Waiting for larb device %pOF\n", larb_node);
> - of_node_put(larb_node);
> - return -EPROBE_DEFER;
> - }
> - of_node_put(larb_node);
> -
> - comp->larb_dev = &larb_pdev->dev;
> -
> comp->dev = dev;
>
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 4c063e0..11c7120 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -98,7 +98,6 @@ struct mtk_ddp_comp {
> struct clk *clk;
> void __iomem *regs;
> int irq;
> - struct device *larb_dev;
> struct device *dev;
> enum mtk_ddp_comp_id id;
> const struct mtk_ddp_comp_funcs *funcs;
> --
> 1.9.1
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply
* Re: [PATCH v4 10/17] drm/mediatek: Add pm runtime support for ovl and rdma
From: Chun-Kuang Hu @ 2020-05-30 11:07 UTC (permalink / raw)
To: Yong Wu
Cc: Will Deacon, youlin.pei, Nicolas Boichat, Joerg Roedel,
Evan Green, eizan, Matthias Kaehlcke, Yongqiang Niu, CK Hu,
devicetree, cui.zhang, Tomasz Figa, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
ming-fan.chen, Linux ARM, anan.sun, acourbot, srv_heupstream,
linux-kernel, chao.hao, iommu, Robin Murphy
In-Reply-To: <1590826218-23653-11-git-send-email-yong.wu@mediatek.com>
Hi, Yong:
Yong Wu <yong.wu@mediatek.com> 於 2020年5月30日 週六 下午4:26寫道：
>
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Display use the dispsys device to call pm_rumtime_get_sync before.
> This patch add pm_runtime_xx with ovl and rdma device whose nodes has
> "iommus" property, then display could help pm_runtime_get for smi via
> ovl or rdma device.
>
> This is a preparing patch that smi cleaning up "mediatek,larb".
>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> CC: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 ++++++++-
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 9 ++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 12 +++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 5 files changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 891d80c..17c9baa 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -11,6 +11,7 @@
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_crtc.h"
> @@ -399,9 +400,13 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
> return ret;
> }
>
> + pm_runtime_enable(dev);
> +
> ret = component_add(dev, &mtk_disp_ovl_component_ops);
> - if (ret)
> + if (ret) {
> + pm_runtime_disable(dev);
> dev_err(dev, "Failed to add component: %d\n", ret);
> + }
>
> return ret;
> }
> @@ -410,6 +415,8 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
> {
> component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
>
> + pm_runtime_disable(&pdev->dev);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 0cb848d..5ea8fb6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -9,6 +9,7 @@
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_crtc.h"
> @@ -313,9 +314,13 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, priv);
>
> + pm_runtime_enable(dev);
> +
> ret = component_add(dev, &mtk_disp_rdma_component_ops);
> - if (ret)
> + if (ret) {
> + pm_runtime_disable(dev);
> dev_err(dev, "Failed to add component: %d\n", ret);
> + }
>
> return ret;
> }
> @@ -324,6 +329,8 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
> {
> component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
>
> + pm_runtime_disable(&pdev->dev);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index fe85e48..c9bc844 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -538,9 +538,15 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
> return;
> }
>
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n",
> + ret);
> +
> ret = mtk_crtc_ddp_hw_init(mtk_crtc);
> if (ret) {
> mtk_smi_larb_put(comp->larb_dev);
> + pm_runtime_put(comp->dev);
> return;
> }
>
> @@ -553,7 +559,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
> {
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
> - int i;
> + int i, ret;
>
> DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
> if (!mtk_crtc->enabled)
> @@ -577,6 +583,10 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
> drm_crtc_vblank_off(crtc);
> mtk_crtc_ddp_hw_fini(mtk_crtc);
> mtk_smi_larb_put(comp->larb_dev);
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n",
> + ret);
>
> mtk_crtc->enabled = false;
> }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 57c88de..593027a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -493,6 +493,8 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
>
> comp->larb_dev = &larb_pdev->dev;
>
> + comp->dev = dev;
> +
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> if (of_address_to_resource(node, 0, &res) != 0) {
> dev_err(dev, "Missing reg in %s node\n", node->full_name);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index debe363..4c063e0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -99,6 +99,7 @@ struct mtk_ddp_comp {
> void __iomem *regs;
> int irq;
> struct device *larb_dev;
> + struct device *dev;
> enum mtk_ddp_comp_id id;
> const struct mtk_ddp_comp_funcs *funcs;
> resource_size_t regs_pa;
> --
> 1.9.1
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply
* [PATCH v4 11/17] drm/mediatek: Get rid of mtk_smi_larb_get/put
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: Will Deacon, youlin.pei, Nicolas Boichat, Evan Green, eizan,
Matthias Kaehlcke, linux-arm-kernel, CK Hu, devicetree, cui.zhang,
Tomasz Figa, linux-mediatek, ming-fan.chen, yong.wu, anan.sun,
acourbot, srv_heupstream, linux-kernel, chao.hao, iommu,
Philipp Zabel, Robin Murphy
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
MediaTek IOMMU has already added the device_link between the consumer
and smi-larb device. If the drm device call the pm_runtime_get_sync,
the smi-larb's pm_runtime_get_sync also be called automatically.
CC: CK Hu <ck.hu@mediatek.com>
CC: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 9 ---------
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 21 ---------------------
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 -
3 files changed, 31 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index c9bc844..d4c4078 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -8,7 +8,6 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include <asm/barrier.h>
-#include <soc/mediatek/smi.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_plane_helper.h>
@@ -532,12 +531,6 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
- ret = mtk_smi_larb_get(comp->larb_dev);
- if (ret) {
- DRM_ERROR("Failed to get larb: %d\n", ret);
- return;
- }
-
ret = pm_runtime_get_sync(comp->dev);
if (ret < 0)
DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n",
@@ -545,7 +538,6 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
ret = mtk_crtc_ddp_hw_init(mtk_crtc);
if (ret) {
- mtk_smi_larb_put(comp->larb_dev);
pm_runtime_put(comp->dev);
return;
}
@@ -582,7 +574,6 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
drm_crtc_vblank_off(crtc);
mtk_crtc_ddp_hw_fini(mtk_crtc);
- mtk_smi_larb_put(comp->larb_dev);
ret = pm_runtime_put(comp->dev);
if (ret < 0)
DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n",
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 593027a..a6e7f3a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -432,8 +432,6 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
const struct mtk_ddp_comp_funcs *funcs)
{
enum mtk_ddp_comp_type type;
- struct device_node *larb_node;
- struct platform_device *larb_pdev;
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
struct resource res;
struct cmdq_client_reg cmdq_reg;
@@ -468,31 +466,12 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
if (IS_ERR(comp->clk))
return PTR_ERR(comp->clk);
- /* Only DMA capable components need the LARB property */
- comp->larb_dev = NULL;
if (type != MTK_DISP_OVL &&
type != MTK_DISP_OVL_2L &&
type != MTK_DISP_RDMA &&
type != MTK_DISP_WDMA)
return 0;
- larb_node = of_parse_phandle(node, "mediatek,larb", 0);
- if (!larb_node) {
- dev_err(dev,
- "Missing mediadek,larb phandle in %pOF node\n", node);
- return -EINVAL;
- }
-
- larb_pdev = of_find_device_by_node(larb_node);
- if (!larb_pdev) {
- dev_warn(dev, "Waiting for larb device %pOF\n", larb_node);
- of_node_put(larb_node);
- return -EPROBE_DEFER;
- }
- of_node_put(larb_node);
-
- comp->larb_dev = &larb_pdev->dev;
-
comp->dev = dev;
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 4c063e0..11c7120 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -98,7 +98,6 @@ struct mtk_ddp_comp {
struct clk *clk;
void __iomem *regs;
int irq;
- struct device *larb_dev;
struct device *dev;
enum mtk_ddp_comp_id id;
const struct mtk_ddp_comp_funcs *funcs;
--
1.9.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related
* [PATCH v4 12/17] memory: mtk-smi: Get rid of mtk_smi_larb_get/put
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang, eizan,
srv_heupstream, chao.hao, Will Deacon, linux-kernel, Evan Green,
Tomasz Figa, iommu, Matthias Kaehlcke, linux-mediatek, yong.wu,
ming-fan.chen, anan.sun, Robin Murphy, acourbot, linux-arm-kernel
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
After adding device_link between the iommu consumer and smi-larb,
the pm_runtime_get(_sync) of smi-larb and smi-common will be called
automatically. we can get rid of mtk_smi_larb_get/put.
CC: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
drivers/memory/mtk-smi.c | 14 --------------
include/soc/mediatek/smi.h | 20 --------------------
2 files changed, 34 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 6cdefda..19c3949 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -125,20 +125,6 @@ static void mtk_smi_clk_disable(const struct mtk_smi *smi)
clk_disable_unprepare(smi->clk_apb);
}
-int mtk_smi_larb_get(struct device *larbdev)
-{
- int ret = pm_runtime_get_sync(larbdev);
-
- return (ret < 0) ? ret : 0;
-}
-EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
-
-void mtk_smi_larb_put(struct device *larbdev)
-{
- pm_runtime_put_sync(larbdev);
-}
-EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
-
static int
mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
{
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index 5a34b87..f8bf595 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -20,26 +20,6 @@ struct mtk_smi_larb_iommu {
unsigned int mmu;
};
-/*
- * mtk_smi_larb_get: Enable the power domain and clocks for this local arbiter.
- * It also initialize some basic setting(like iommu).
- * mtk_smi_larb_put: Disable the power domain and clocks for this local arbiter.
- * Both should be called in non-atomic context.
- *
- * Returns 0 if successful, negative on failure.
- */
-int mtk_smi_larb_get(struct device *larbdev);
-void mtk_smi_larb_put(struct device *larbdev);
-
-#else
-
-static inline int mtk_smi_larb_get(struct device *larbdev)
-{
- return 0;
-}
-
-static inline void mtk_smi_larb_put(struct device *larbdev) { }
-
#endif
#endif
--
1.9.1
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^ permalink raw reply related
* [PATCH v4 17/17] arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang, eizan,
srv_heupstream, chao.hao, Will Deacon, linux-kernel, Evan Green,
Tomasz Figa, iommu, Matthias Kaehlcke, linux-mediatek, yong.wu,
ming-fan.chen, anan.sun, Robin Murphy, acourbot, linux-arm-kernel
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
After adding device_link between the IOMMU consumer and smi,
the mediatek,larb is unnecessary now.
CC: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 9fccbec..7eed8c8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -926,7 +926,6 @@
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
};
@@ -937,7 +936,6 @@
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
};
mdp_rsz0: rsz@14003000 {
@@ -967,7 +965,6 @@
clocks = <&mmsys CLK_MM_MDP_WDMA>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
};
mdp_wrot0: wrot@14007000 {
@@ -976,7 +973,6 @@
clocks = <&mmsys CLK_MM_MDP_WROT0>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
};
mdp_wrot1: wrot@14008000 {
@@ -985,7 +981,6 @@
clocks = <&mmsys CLK_MM_MDP_WROT1>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
};
ovl0: ovl@1400c000 {
@@ -995,7 +990,6 @@
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
};
ovl1: ovl@1400d000 {
@@ -1005,7 +999,6 @@
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
};
rdma0: rdma@1400e000 {
@@ -1015,7 +1008,6 @@
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
};
rdma1: rdma@1400f000 {
@@ -1025,7 +1017,6 @@
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
};
rdma2: rdma@14010000 {
@@ -1035,7 +1026,6 @@
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
};
wdma0: wdma@14011000 {
@@ -1045,7 +1035,6 @@
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
};
wdma1: wdma@14012000 {
@@ -1055,7 +1044,6 @@
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
};
color0: color@14013000 {
@@ -1299,7 +1287,6 @@
<0 0x16027800 0 0x800>, /* VDEC_HWB */
<0 0x16028400 0 0x400>; /* VDEC_HWG */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb1>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
@@ -1367,7 +1354,6 @@
compatible = "mediatek,mt8173-vcodec-avc-enc";
reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1395,7 +1381,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
<&iommu M4U_PORT_JPGDEC_BSDMA>;
};
@@ -1429,7 +1414,6 @@
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
- mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
--
1.9.1
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^ permalink raw reply related
* [PATCH v4 10/17] drm/mediatek: Add pm runtime support for ovl and rdma
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: Will Deacon, youlin.pei, Nicolas Boichat, Evan Green, eizan,
Matthias Kaehlcke, linux-arm-kernel, Yongqiang Niu, CK Hu,
devicetree, cui.zhang, Tomasz Figa, linux-mediatek, ming-fan.chen,
yong.wu, anan.sun, acourbot, srv_heupstream, linux-kernel,
chao.hao, iommu, Robin Murphy
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
Display use the dispsys device to call pm_rumtime_get_sync before.
This patch add pm_runtime_xx with ovl and rdma device whose nodes has
"iommus" property, then display could help pm_runtime_get for smi via
ovl or rdma device.
This is a preparing patch that smi cleaning up "mediatek,larb".
CC: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 ++++++++-
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 9 ++++++++-
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 12 +++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
5 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 891d80c..17c9baa 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -11,6 +11,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h"
@@ -399,9 +400,13 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
return ret;
}
+ pm_runtime_enable(dev);
+
ret = component_add(dev, &mtk_disp_ovl_component_ops);
- if (ret)
+ if (ret) {
+ pm_runtime_disable(dev);
dev_err(dev, "Failed to add component: %d\n", ret);
+ }
return ret;
}
@@ -410,6 +415,8 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
+ pm_runtime_disable(&pdev->dev);
+
return 0;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 0cb848d..5ea8fb6 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -9,6 +9,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h"
@@ -313,9 +314,13 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, priv);
+ pm_runtime_enable(dev);
+
ret = component_add(dev, &mtk_disp_rdma_component_ops);
- if (ret)
+ if (ret) {
+ pm_runtime_disable(dev);
dev_err(dev, "Failed to add component: %d\n", ret);
+ }
return ret;
}
@@ -324,6 +329,8 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
+ pm_runtime_disable(&pdev->dev);
+
return 0;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index fe85e48..c9bc844 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -538,9 +538,15 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
return;
}
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n",
+ ret);
+
ret = mtk_crtc_ddp_hw_init(mtk_crtc);
if (ret) {
mtk_smi_larb_put(comp->larb_dev);
+ pm_runtime_put(comp->dev);
return;
}
@@ -553,7 +559,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
- int i;
+ int i, ret;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
if (!mtk_crtc->enabled)
@@ -577,6 +583,10 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
drm_crtc_vblank_off(crtc);
mtk_crtc_ddp_hw_fini(mtk_crtc);
mtk_smi_larb_put(comp->larb_dev);
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n",
+ ret);
mtk_crtc->enabled = false;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 57c88de..593027a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -493,6 +493,8 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
comp->larb_dev = &larb_pdev->dev;
+ comp->dev = dev;
+
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (of_address_to_resource(node, 0, &res) != 0) {
dev_err(dev, "Missing reg in %s node\n", node->full_name);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index debe363..4c063e0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -99,6 +99,7 @@ struct mtk_ddp_comp {
void __iomem *regs;
int irq;
struct device *larb_dev;
+ struct device *dev;
enum mtk_ddp_comp_id id;
const struct mtk_ddp_comp_funcs *funcs;
resource_size_t regs_pa;
--
1.9.1
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^ permalink raw reply related
* [PATCH v4 15/17] arm: dts: mediatek: Get rid of mediatek, larb for MM nodes
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang, eizan,
srv_heupstream, chao.hao, Will Deacon, linux-kernel, Evan Green,
Tomasz Figa, iommu, Matthias Kaehlcke, linux-mediatek, yong.wu,
ming-fan.chen, anan.sun, Robin Murphy, acourbot, linux-arm-kernel
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
After adding device_link between the IOMMU consumer and smi,
the mediatek,larb is unnecessary now.
CC: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
arch/arm/boot/dts/mt2701.dtsi | 1 -
arch/arm/boot/dts/mt7623.dtsi | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 2093b38..79da94c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -564,7 +564,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index f76b4a3..f334039 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -783,7 +783,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
--
1.9.1
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^ permalink raw reply related
* [PATCH v4 16/17] arm64: dts: mt8173: Separate mtk-vcodec-enc node
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: Will Deacon, youlin.pei, Irui Wang, Nicolas Boichat, Evan Green,
eizan, Matthias Kaehlcke, linux-arm-kernel, devicetree, cui.zhang,
Tomasz Figa, linux-mediatek, Hsin-Yi Wang, ming-fan.chen, yong.wu,
anan.sun, acourbot, srv_heupstream, linux-kernel, chao.hao, iommu,
Robin Murphy
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
From: Irui Wang <irui.wang@mediatek.com>
There are two separate hardware encoder blocks inside MT8173. Split
the current mtk-vcodec-enc node to match the hardware architecture.
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60 +++++++++++++++++---------------
1 file changed, 31 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index fb21a6b..9fccbec 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1364,13 +1364,10 @@
};
vcodec_enc: vcodec@18002000 {
- compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
- <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
+ compatible = "mediatek,mt8173-vcodec-avc-enc";
+ reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1381,29 +1378,12 @@
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
- <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
- <&iommu M4U_PORT_VENC_BSDMA_SET2>,
- <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
- <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
- <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ <&iommu M4U_PORT_VENC_NBM_WDMA>;
mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
};
jpegdec: jpegdec@18004000 {
@@ -1435,6 +1415,28 @@
<&vencltsys CLK_VENCLT_CKE0>;
clock-names = "apb", "smi";
};
+
+ vcodec_enc_lt: vcodec@19002000 {
+ compatible = "mediatek,mt8173-vcodec-vp8-enc";
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+ <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+ <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,larb = <&larb5>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_lt_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ assigned-clock-parents = <&topckgen
+ CLK_TOP_VCODECPLL_370P5>;
+ };
};
};
--
1.9.1
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^ permalink raw reply related
* [PATCH v4 08/17] media: mtk-vcodec: separate mtk-vcodec-enc node.
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: Maoguang Meng, Will Deacon, youlin.pei, Irui Wang,
Nicolas Boichat, Evan Green, eizan, Matthias Kaehlcke,
linux-arm-kernel, devicetree, cui.zhang, Tomasz Figa,
linux-mediatek, Hsin-Yi Wang, ming-fan.chen, yong.wu, anan.sun,
acourbot, srv_heupstream, linux-kernel, chao.hao, iommu,
Robin Murphy
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
From: Maoguang Meng <maoguang.meng@mediatek.com>
MTK H264 Encoder(VENC_SYS) and VP8 Encoder(VENC_LT_SYS) are two
independent hardware instance. They have their owner interrupt,
register mapping, and special clocks.
This patch seperates the two instance. This is a preparing patch for
adding device_link between the larbs and venc-device. It's mainly for
fixing the problem:
https://lkml.org/lkml/2019/9/3/316
User Call "VIDIOC_QUERYCAP":
H264 Encoder return driver name "mtk-vcodec-enc";
VP8 Encoder return driver name "mtk-venc-vp8.
Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 10 +-
drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c | 23 +++-
.../media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c | 127 +++++++++------------
.../media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c | 31 +----
.../media/platform/mtk-vcodec/mtk_vcodec_enc_pm.h | 1 -
.../media/platform/mtk-vcodec/venc/venc_vp8_if.c | 4 +-
6 files changed, 80 insertions(+), 116 deletions(-)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
index a2716117..52d1ce1 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
@@ -19,6 +19,7 @@
#define MTK_VCODEC_DRV_NAME "mtk_vcodec_drv"
#define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
#define MTK_VCODEC_ENC_NAME "mtk-vcodec-enc"
+#define MTK_VENC_VP8_NAME "mtk-venc-vp8"
#define MTK_PLATFORM_STR "platform:mt8173"
#define MTK_VCODEC_MAX_PLANES 3
@@ -193,7 +194,6 @@ struct mtk_vcodec_pm {
struct mtk_vcodec_clk venc_clk;
struct device *larbvenc;
- struct device *larbvenclt;
struct device *dev;
struct mtk_vcodec_dev *mtkdev;
};
@@ -311,25 +311,27 @@ enum mtk_chip {
* @chip: chip this encoder is compatible with
*
* @uses_ext: whether the encoder uses the extended firmware messaging format
- * @has_lt_irq: whether the encoder uses the LT irq
+ * @name: whether the encoder core is vp8
* @min_birate: minimum supported encoding bitrate
* @max_bitrate: maximum supported encoding bitrate
* @capture_formats: array of supported capture formats
* @num_capture_formats: number of entries in capture_formats
* @output_formats: array of supported output formats
* @num_output_formats: number of entries in output_formats
+ * @core_id: stand for h264 or vp8 encode index
*/
struct mtk_vcodec_enc_pdata {
enum mtk_chip chip;
bool uses_ext;
- bool has_lt_irq;
+ const char *name;
unsigned long min_bitrate;
unsigned long max_bitrate;
const struct mtk_video_fmt *capture_formats;
size_t num_capture_formats;
const struct mtk_video_fmt *output_formats;
size_t num_output_formats;
+ int core_id;
};
/**
@@ -359,7 +361,6 @@ struct mtk_vcodec_enc_pdata {
*
* @dec_irq: decoder irq resource
* @enc_irq: h264 encoder irq resource
- * @enc_lt_irq: vp8 encoder irq resource
*
* @dec_mutex: decoder hardware lock
* @enc_mutex: encoder hardware lock.
@@ -395,7 +396,6 @@ struct mtk_vcodec_dev {
int dec_irq;
int enc_irq;
- int enc_lt_irq;
struct mutex dec_mutex;
struct mutex enc_mutex;
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
index f0af78f..5301dca 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
@@ -9,6 +9,7 @@
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-dma-contig.h>
#include <soc/mediatek/smi.h>
+#include <linux/pm_runtime.h>
#include "mtk_vcodec_drv.h"
#include "mtk_vcodec_enc.h"
@@ -174,7 +175,10 @@ static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
static int vidioc_venc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
- strscpy(cap->driver, MTK_VCODEC_ENC_NAME, sizeof(cap->driver));
+ const struct mtk_vcodec_enc_pdata *pdata =
+ fh_to_ctx(priv)->dev->venc_pdata;
+
+ strscpy(cap->driver, pdata->name, sizeof(cap->driver));
strscpy(cap->bus_info, MTK_PLATFORM_STR, sizeof(cap->bus_info));
strscpy(cap->card, MTK_PLATFORM_STR, sizeof(cap->card));
@@ -788,7 +792,7 @@ static int vb2ops_venc_start_streaming(struct vb2_queue *q, unsigned int count)
*/
if ((ctx->state == MTK_STATE_ABORT) || (ctx->state == MTK_STATE_FREE)) {
ret = -EIO;
- goto err_set_param;
+ goto err_start_stream;
}
/* Do the initialization when both start_streaming have been called */
@@ -800,6 +804,12 @@ static int vb2ops_venc_start_streaming(struct vb2_queue *q, unsigned int count)
return 0;
}
+ ret = pm_runtime_get_sync(&ctx->dev->plat_dev->dev);
+ if (ret < 0) {
+ mtk_v4l2_err("pm_runtime_get_sync fail %d", ret);
+ goto err_start_stream;
+ }
+
mtk_venc_set_param(ctx, ¶m);
ret = venc_if_set_param(ctx, VENC_SET_PARAM_ENC, ¶m);
if (ret) {
@@ -826,6 +836,11 @@ static int vb2ops_venc_start_streaming(struct vb2_queue *q, unsigned int count)
return 0;
err_set_param:
+ ret = pm_runtime_put(&ctx->dev->plat_dev->dev);
+ if (ret < 0)
+ mtk_v4l2_err("pm_runtime_put fail %d", ret);
+
+err_start_stream:
for (i = 0; i < q->num_buffers; ++i) {
struct vb2_buffer *buf = vb2_get_buffer(q, i);
@@ -879,6 +894,10 @@ static void vb2ops_venc_stop_streaming(struct vb2_queue *q)
if (ret)
mtk_v4l2_err("venc_if_deinit failed=%d", ret);
+ ret = pm_runtime_put(&ctx->dev->plat_dev->dev);
+ if (ret < 0)
+ mtk_v4l2_err("pm_runtime_put fail %d", ret);
+
ctx->state = MTK_STATE_FREE;
}
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
index b8fe408..fe17f0c 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
@@ -49,12 +49,15 @@
},
};
-static const struct mtk_video_fmt mtk_video_formats_capture_mt8173[] = {
+static const struct mtk_video_fmt mtk_video_formats_capture_mt8173_h264[] = {
{
.fourcc = V4L2_PIX_FMT_H264,
.type = MTK_FMT_ENC,
.num_planes = 1,
},
+};
+
+static const struct mtk_video_fmt mtk_video_formats_capture_mt8173_vp8[] = {
{
.fourcc = V4L2_PIX_FMT_VP8,
.type = MTK_FMT_ENC,
@@ -110,35 +113,13 @@ static irqreturn_t mtk_vcodec_enc_irq_handler(int irq, void *priv)
ctx = dev->curr_ctx;
spin_unlock_irqrestore(&dev->irqlock, flags);
- mtk_v4l2_debug(1, "id=%d", ctx->id);
- addr = dev->reg_base[VENC_SYS] + MTK_VENC_IRQ_ACK_OFFSET;
-
- ctx->irq_status = readl(dev->reg_base[VENC_SYS] +
- (MTK_VENC_IRQ_STATUS_OFFSET));
-
- clean_irq_status(ctx->irq_status, addr);
-
- wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t mtk_vcodec_enc_lt_irq_handler(int irq, void *priv)
-{
- struct mtk_vcodec_dev *dev = priv;
- struct mtk_vcodec_ctx *ctx;
- unsigned long flags;
- void __iomem *addr;
-
- spin_lock_irqsave(&dev->irqlock, flags);
- ctx = dev->curr_ctx;
- spin_unlock_irqrestore(&dev->irqlock, flags);
+ mtk_v4l2_debug(1, "id=%d coreid:%d", ctx->id, dev->venc_pdata->core_id);
+ addr = dev->reg_base[dev->venc_pdata->core_id] +
+ MTK_VENC_IRQ_ACK_OFFSET;
- mtk_v4l2_debug(1, "id=%d", ctx->id);
- ctx->irq_status = readl(dev->reg_base[VENC_LT_SYS] +
+ ctx->irq_status = readl(dev->reg_base[dev->venc_pdata->core_id] +
(MTK_VENC_IRQ_STATUS_OFFSET));
- addr = dev->reg_base[VENC_LT_SYS] + MTK_VENC_IRQ_ACK_OFFSET;
-
clean_irq_status(ctx->irq_status, addr);
wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED);
@@ -265,7 +246,8 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
struct resource *res;
phandle rproc_phandle;
enum mtk_vcodec_fw_type fw_type;
- int i, j, ret;
+ int ret;
+ void __iomem *reg_base;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
@@ -291,63 +273,39 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
dev->venc_pdata = of_device_get_match_data(&pdev->dev);
ret = mtk_vcodec_init_enc_pm(dev);
if (ret < 0) {
- dev_err(&pdev->dev, "Failed to get mt vcodec clock source!");
+ dev_err(&pdev->dev, "Failed to get mtk vcodec clock source!");
goto err_enc_pm;
}
- for (i = VENC_SYS, j = 0; i < NUM_MAX_VCODEC_REG_BASE; i++, j++) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, j);
- dev->reg_base[i] = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR((__force void *)dev->reg_base[i])) {
- ret = PTR_ERR((__force void *)dev->reg_base[i]);
- goto err_res;
- }
- mtk_v4l2_debug(2, "reg[%d] base=0x%p", i, dev->reg_base[i]);
- }
+ pm_runtime_enable(&pdev->dev);
+
+ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s",
+ dev->venc_pdata->name);
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "failed to get irq resource");
- ret = -ENOENT;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR((__force void *)reg_base)) {
+ ret = PTR_ERR((__force void *)reg_base);
goto err_res;
}
+ dev->reg_base[dev->venc_pdata->core_id] = reg_base;
dev->enc_irq = platform_get_irq(pdev, 0);
ret = devm_request_irq(&pdev->dev, dev->enc_irq,
mtk_vcodec_enc_irq_handler,
0, pdev->name, dev);
if (ret) {
- dev_err(&pdev->dev, "Failed to install dev->enc_irq %d (%d)",
- dev->enc_irq,
- ret);
+ dev_err(&pdev->dev,
+ "Failed to install dev->enc_irq %d (%d) core_id:%d",
+ dev->enc_irq, ret, dev->venc_pdata->core_id);
ret = -EINVAL;
goto err_res;
}
disable_irq(dev->enc_irq);
- if (dev->venc_pdata->has_lt_irq) {
- dev->enc_lt_irq = platform_get_irq(pdev, 1);
- ret = devm_request_irq(&pdev->dev,
- dev->enc_lt_irq,
- mtk_vcodec_enc_lt_irq_handler,
- 0, pdev->name, dev);
- if (ret) {
- dev_err(&pdev->dev,
- "Failed to install dev->enc_lt_irq %d (%d)",
- dev->enc_lt_irq, ret);
- ret = -EINVAL;
- goto err_res;
- }
- disable_irq(dev->enc_lt_irq); /* VENC_LT */
- }
-
mutex_init(&dev->enc_mutex);
mutex_init(&dev->dev_mutex);
spin_lock_init(&dev->irqlock);
-
- snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s",
- "[MTK_V4L2_VENC]");
-
ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
if (ret) {
mtk_v4l2_err("v4l2_device_register err=%d", ret);
@@ -373,7 +331,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
V4L2_CAP_STREAMING;
snprintf(vfd_enc->name, sizeof(vfd_enc->name), "%s",
- MTK_VCODEC_ENC_NAME);
+ dev->venc_pdata->name);
video_set_drvdata(vfd_enc, dev);
dev->vfd_enc = vfd_enc;
platform_set_drvdata(pdev, dev);
@@ -401,8 +359,8 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
goto err_enc_reg;
}
- mtk_v4l2_debug(0, "encoder registered as /dev/video%d",
- vfd_enc->num);
+ mtk_v4l2_debug(0, "encoder %d registered as /dev/video%d",
+ dev->venc_pdata->core_id, vfd_enc->num);
return 0;
@@ -415,26 +373,39 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
err_enc_alloc:
v4l2_device_unregister(&dev->v4l2_dev);
err_res:
- mtk_vcodec_release_enc_pm(dev);
+ pm_runtime_disable(&pdev->dev);
err_enc_pm:
mtk_vcodec_fw_release(dev->fw_handler);
return ret;
}
-static const struct mtk_vcodec_enc_pdata mt8173_pdata = {
+static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
+ .chip = MTK_MT8173,
+ .name = MTK_VCODEC_ENC_NAME,
+ .capture_formats = mtk_video_formats_capture_mt8173_h264,
+ .num_capture_formats = 1,
+ .output_formats = mtk_video_formats_output_mt8173,
+ .num_output_formats = ARRAY_SIZE(mtk_video_formats_output_mt8173),
+ .min_bitrate = 1,
+ .max_bitrate = 4000000,
+ .core_id = VENC_SYS,
+};
+
+static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
.chip = MTK_MT8173,
- .has_lt_irq = true,
- .capture_formats = mtk_video_formats_capture_mt8173,
- .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_mt8173),
+ .name = MTK_VENC_VP8_NAME,
+ .capture_formats = mtk_video_formats_capture_mt8173_vp8,
+ .num_capture_formats = 1,
.output_formats = mtk_video_formats_output_mt8173,
.num_output_formats = ARRAY_SIZE(mtk_video_formats_output_mt8173),
.min_bitrate = 1,
.max_bitrate = 4000000,
+ .core_id = VENC_LT_SYS,
};
static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
.chip = MTK_MT8183,
- .has_lt_irq = false,
+ .name = MTK_VCODEC_ENC_NAME,
.uses_ext = true,
.capture_formats = mtk_video_formats_capture_mt8183,
.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_mt8183),
@@ -443,10 +414,14 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
.num_output_formats = ARRAY_SIZE(mtk_video_formats_output_mt8173),
.min_bitrate = 64,
.max_bitrate = 40000000,
+ .core_id = VENC_SYS,
};
static const struct of_device_id mtk_vcodec_enc_match[] = {
- {.compatible = "mediatek,mt8173-vcodec-enc", .data = &mt8173_pdata},
+ {.compatible = "mediatek,mt8173-vcodec-avc-enc",
+ .data = &mt8173_avc_pdata},
+ {.compatible = "mediatek,mt8173-vcodec-vp8-enc",
+ .data = &mt8173_vp8_pdata},
{.compatible = "mediatek,mt8183-vcodec-enc", .data = &mt8183_pdata},
{},
};
@@ -466,7 +441,7 @@ static int mtk_vcodec_enc_remove(struct platform_device *pdev)
video_unregister_device(dev->vfd_enc);
v4l2_device_unregister(&dev->v4l2_dev);
- mtk_vcodec_release_enc_pm(dev);
+ pm_runtime_disable(&pdev->dev);
mtk_vcodec_fw_release(dev->fw_handler);
return 0;
}
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
index ee22902..01c6a55 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
@@ -43,21 +43,6 @@ int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev)
return -ENODEV;
}
pm->larbvenc = &pdev->dev;
-
- node = of_parse_phandle(dev->of_node, "mediatek,larb", 1);
- if (!node) {
- mtk_v4l2_err("no mediatek,larb found");
- return -ENODEV;
- }
-
- pdev = of_find_device_by_node(node);
- of_node_put(node);
- if (!pdev) {
- mtk_v4l2_err("no mediatek,larb device found");
- return -ENODEV;
- }
-
- pm->larbvenclt = &pdev->dev;
pdev = mtkdev->plat_dev;
pm->dev = &pdev->dev;
@@ -94,11 +79,6 @@ int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev)
return ret;
}
-void mtk_vcodec_release_enc_pm(struct mtk_vcodec_dev *mtkdev)
-{
-}
-
-
void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm)
{
struct mtk_vcodec_clk *enc_clk = &pm->venc_clk;
@@ -116,18 +96,10 @@ void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm)
ret = mtk_smi_larb_get(pm->larbvenc);
if (ret) {
mtk_v4l2_err("mtk_smi_larb_get larb3 fail %d", ret);
- goto larbvencerr;
- }
- ret = mtk_smi_larb_get(pm->larbvenclt);
- if (ret) {
- mtk_v4l2_err("mtk_smi_larb_get larb4 fail %d", ret);
- goto larbvenclterr;
+ goto clkerr;
}
return;
-larbvenclterr:
- mtk_smi_larb_put(pm->larbvenc);
-larbvencerr:
clkerr:
for (i -= 1; i >= 0; i--)
clk_disable_unprepare(enc_clk->clk_info[i].vcodec_clk);
@@ -139,7 +111,6 @@ void mtk_vcodec_enc_clock_off(struct mtk_vcodec_pm *pm)
int i = 0;
mtk_smi_larb_put(pm->larbvenc);
- mtk_smi_larb_put(pm->larbvenclt);
for (i = enc_clk->clk_num - 1; i >= 0; i--)
clk_disable_unprepare(enc_clk->clk_info[i].vcodec_clk);
}
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.h
index b7ecdfd..c1b5986 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.h
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.h
@@ -10,7 +10,6 @@
#include "mtk_vcodec_drv.h"
int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *dev);
-void mtk_vcodec_release_enc_pm(struct mtk_vcodec_dev *dev);
void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm);
void mtk_vcodec_enc_clock_off(struct mtk_vcodec_pm *pm);
diff --git a/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c b/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c
index 11abb19..8267a9c 100644
--- a/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c
+++ b/drivers/media/platform/mtk-vcodec/venc/venc_vp8_if.c
@@ -367,7 +367,7 @@ static int vp8_enc_encode(void *handle,
mtk_vcodec_debug_enter(inst);
- enable_irq(ctx->dev->enc_lt_irq);
+ enable_irq(ctx->dev->enc_irq);
switch (opt) {
case VENC_START_OPT_ENCODE_FRAME:
@@ -386,7 +386,7 @@ static int vp8_enc_encode(void *handle,
encode_err:
- disable_irq(ctx->dev->enc_lt_irq);
+ disable_irq(ctx->dev->enc_irq);
mtk_vcodec_debug_leave(inst);
return ret;
--
1.9.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related
* [PATCH v4 02/17] dt-binding: mediatek: Get rid of mediatek, larb for multimedia HW
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang, eizan,
srv_heupstream, chao.hao, Will Deacon, linux-kernel, Evan Green,
Tomasz Figa, iommu, Matthias Kaehlcke, linux-mediatek, yong.wu,
ming-fan.chen, anan.sun, Robin Murphy, acourbot, linux-arm-kernel
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
After adding device_link between the consumer with the smi-larbs,
if the consumer call its owner pm_runtime_get(_sync), the
pm_runtime_get(_sync) of smi-larb and smi-common will be called
automatically. Thus, the consumer don't need the property.
And IOMMU also know which larb this consumer connects with from
iommu id in the "iommus=" property.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 9 ---------
.../devicetree/bindings/media/mediatek-jpeg-decoder.txt | 4 ----
Documentation/devicetree/bindings/media/mediatek-mdp.txt | 8 --------
Documentation/devicetree/bindings/media/mediatek-vcodec.txt | 4 ----
4 files changed, 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index b91e709..c7e2eb8 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -60,8 +60,6 @@ Required properties (DMA function blocks):
"mediatek,<chip>-disp-rdma"
"mediatek,<chip>-disp-wdma"
the supported chips are mt2701 and mt8173.
-- larb: Should contain a phandle pointing to the local arbiter device as defined
- in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- iommus: Should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
@@ -82,7 +80,6 @@ ovl0: ovl@1400c000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
};
ovl1: ovl@1400d000 {
@@ -92,7 +89,6 @@ ovl1: ovl@1400d000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
};
rdma0: rdma@1400e000 {
@@ -102,7 +98,6 @@ rdma0: rdma@1400e000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
};
rdma1: rdma@1400f000 {
@@ -112,7 +107,6 @@ rdma1: rdma@1400f000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
};
rdma2: rdma@14010000 {
@@ -122,7 +116,6 @@ rdma2: rdma@14010000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
};
wdma0: wdma@14011000 {
@@ -132,7 +125,6 @@ wdma0: wdma@14011000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
};
wdma1: wdma@14012000 {
@@ -142,7 +134,6 @@ wdma1: wdma@14012000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
};
color0: color@14013000 {
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
index 044b119..7978f21 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
@@ -15,9 +15,6 @@ Required properties:
- clock-names: must contain "jpgdec-smi" and "jpgdec".
- power-domains: a phandle to the power domain, see
Documentation/devicetree/bindings/power/power_domain.txt for details.
-- mediatek,larb: must contain the local arbiters in the current Socs, see
- Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- for details.
- iommus: should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
@@ -32,7 +29,6 @@ Example:
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt
index 0d03e3a..df69c5a 100644
--- a/Documentation/devicetree/bindings/media/mediatek-mdp.txt
+++ b/Documentation/devicetree/bindings/media/mediatek-mdp.txt
@@ -27,9 +27,6 @@ Required properties (DMA function blocks, child node):
- iommus: should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
-- mediatek,larb: must contain the local arbiters in the current Socs, see
- Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- for details.
Example:
mdp_rdma0: rdma@14001000 {
@@ -40,7 +37,6 @@ Example:
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
};
@@ -51,7 +47,6 @@ Example:
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
};
mdp_rsz0: rsz@14003000 {
@@ -81,7 +76,6 @@ Example:
clocks = <&mmsys CLK_MM_MDP_WDMA>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
};
mdp_wrot0: wrot@14007000 {
@@ -90,7 +84,6 @@ Example:
clocks = <&mmsys CLK_MM_MDP_WROT0>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
};
mdp_wrot1: wrot@14008000 {
@@ -99,5 +92,4 @@ Example:
clocks = <&mmsys CLK_MM_MDP_WROT1>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
};
diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
index 1023740..50a27f2 100644
--- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
+++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
@@ -12,7 +12,6 @@ Required properties:
- reg : Physical base address of the video codec registers and length of
memory mapped region.
- interrupts : interrupt number to the cpu.
-- mediatek,larb : must contain the local arbiters in the current Socs.
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property.
- clock-names:
@@ -45,7 +44,6 @@ vcodec_dec: vcodec@16000000 {
<0 0x16027800 0 0x800>, /*VP8_VL*/
<0 0x16028400 0 0x400>; /*VP9_VD*/
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb1>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
@@ -98,7 +96,6 @@ vcodec_enc: vcodec@18002000 {
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
<&iommu M4U_PORT_VENC_NBM_WDMA>;
- mediatek,larb = <&larb3>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_SEL>;
clock-names = "venc_sel";
@@ -119,7 +116,6 @@ vcodec_enc_lt: vcodec@19002000 {
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
- mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
--
1.9.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related
* [PATCH v4 01/17] media: dt-binding: mtk-vcodec: Separating mtk-vcodec encode node.
From: Yong Wu @ 2020-05-30 8:10 UTC (permalink / raw)
To: Matthias Brugger, Joerg Roedel, Rob Herring
Cc: Maoguang Meng, Will Deacon, youlin.pei, Irui Wang,
Nicolas Boichat, Evan Green, eizan, Matthias Kaehlcke,
linux-arm-kernel, devicetree, cui.zhang, Tomasz Figa,
linux-mediatek, Hsin-Yi Wang, ming-fan.chen, yong.wu, anan.sun,
acourbot, srv_heupstream, linux-kernel, chao.hao, iommu,
Robin Murphy
In-Reply-To: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com>
From: Maoguang Meng <maoguang.meng@mediatek.com>
Update binding document since the avc and vp8 hardware encoder in
mt8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to
"mediatek,mt8173-vcodec-vp8-enc" and "mediatek,mt8173-vcodec-avc-enc".
This is a preparing patch for smi cleaning up "mediatek,larb".
Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
.../devicetree/bindings/media/mediatek-vcodec.txt | 58 ++++++++++++----------
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
index 8093335..1023740 100644
--- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
+++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
@@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
supports high resolution encoding and decoding functionalities.
Required properties:
-- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
+- compatible : must be one of the following string:
+ "mediatek,mt8173-vcodec-vp8-enc" for mt8173 vp8 encoder.
+ "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder.
"mediatek,mt8183-vcodec-enc" for MT8183 encoder.
"mediatek,mt8173-vcodec-dec" for MT8173 decoder.
- reg : Physical base address of the video codec registers and length of
@@ -13,10 +15,11 @@ Required properties:
- mediatek,larb : must contain the local arbiters in the current Socs.
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property.
-- clock-names: encoder must contain "venc_sel_src", "venc_sel",,
- "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
- "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
- "venc_lt_sel", "vdec_bus_clk_src".
+- clock-names:
+ avc venc must contain "venc_sel";
+ vp8 venc must contain "venc_lt_sel";
+ decoder must contain "vcodecpll", "univpll_d2", "clk_cci400_sel",
+ "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", "vdec_bus_clk_src".
- iommus : should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
@@ -80,14 +83,10 @@ vcodec_dec: vcodec@16000000 {
assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
};
- vcodec_enc: vcodec@18002000 {
- compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
- <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
+vcodec_enc: vcodec@18002000 {
+ compatible = "mediatek,mt8173-vcodec-avc-enc";
+ reg = <0 0x18002000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -98,8 +97,20 @@ vcodec_dec: vcodec@16000000 {
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_NBM_WDMA>;
+ mediatek,larb = <&larb3>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ };
+
+vcodec_enc_lt: vcodec@19002000 {
+ compatible = "mediatek,mt8173-vcodec-vp8-enc";
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
@@ -108,17 +119,10 @@ vcodec_dec: vcodec@16000000 {
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>;
+ clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_lt_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
};
--
1.9.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
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