* [PATCH v3 13/22] pinctrl: core: Embed struct pingroup into struct group_desc
From: Andy Shevchenko @ 2023-11-28 19:57 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
struct group_desc is a particular version of the struct pingroup
with associated opaque data. Start switching pin control core and
drivers to use it explicitly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/core.c | 15 ++++++++++++---
drivers/pinctrl/core.h | 5 +++++
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 3f1fd50fbb10..e08d4b3b0a56 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -559,7 +559,10 @@ const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev,
if (!group)
return NULL;
- return group->name;
+ if (group->name)
+ return group->name;
+
+ return group->grp.name;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_name);
@@ -585,8 +588,14 @@ int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- *pins = group->pins;
- *num_pins = group->num_pins;
+ if (group->pins) {
+ *pins = group->pins;
+ *num_pins = group->num_pins;
+ return 0;
+ }
+
+ *pins = group->grp.pins;
+ *num_pins = group->grp.npins;
return 0;
}
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 276a631fd49c..863b4956a41e 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -194,14 +194,18 @@ struct pinctrl_maps {
#ifdef CONFIG_GENERIC_PINCTRL_GROUPS
+#include <linux/pinctrl/pinctrl.h>
+
/**
* struct group_desc - generic pin group descriptor
+ * @grp: generic data of the pin group (name and pins)
* @name: name of the pin group
* @pins: array of pins that belong to the group
* @num_pins: number of pins in the group
* @data: pin controller driver specific data
*/
struct group_desc {
+ struct pingroup grp;
const char *name;
const int *pins;
int num_pins;
@@ -211,6 +215,7 @@ struct group_desc {
/* Convenience macro to define a generic pin group descriptor */
#define PINCTRL_GROUP_DESC(_name, _pins, _num_pins, _data) \
(struct group_desc) { \
+ .grp = PINCTRL_PINGROUP(_name, _pins, _num_pins), \
.name = _name, \
.pins = _pins, \
.num_pins = _num_pins, \
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 18/22] pinctrl: keembay: Convert to use grp member
From: Andy Shevchenko @ 2023-11-28 19:57 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
Convert drivers to use grp member embedded in struct group_desc.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/pinctrl-keembay.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-keembay.c b/drivers/pinctrl/pinctrl-keembay.c
index 87d328853ae4..b1349ee22799 100644
--- a/drivers/pinctrl/pinctrl-keembay.c
+++ b/drivers/pinctrl/pinctrl-keembay.c
@@ -945,7 +945,7 @@ static int keembay_set_mux(struct pinctrl_dev *pctldev, unsigned int fun_sel,
return -EINVAL;
/* Change modes for pins in the selected group */
- pin = *grp->pins;
+ pin = *grp->grp.pins;
pin_mode = *(u8 *)(func->data);
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 21/22] pinctrl: starfive: Convert to use grp member
From: Andy Shevchenko @ 2023-11-28 19:57 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng,
Emil Renner Berthing
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
Convert drivers to use grp member embedded in struct group_desc.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c | 8 ++++----
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
index ea70b8c61679..21bfbbaede72 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
@@ -654,7 +654,7 @@ static int starfive_set_mux(struct pinctrl_dev *pctldev,
return -EINVAL;
pinmux = group->data;
- for (i = 0; i < group->num_pins; i++) {
+ for (i = 0; i < group->grp.npins; i++) {
u32 v = pinmux[i];
unsigned int gpio = starfive_pinmux_to_gpio(v);
u32 dout = starfive_pinmux_to_dout(v);
@@ -797,7 +797,7 @@ static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
if (!group)
return -EINVAL;
- return starfive_pinconf_get(pctldev, group->pins[0], config);
+ return starfive_pinconf_get(pctldev, group->grp.pins[0], config);
}
static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
@@ -876,8 +876,8 @@ static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
}
}
- for (i = 0; i < group->num_pins; i++)
- starfive_padctl_rmw(sfp, group->pins[i], mask, value);
+ for (i = 0; i < group->grp.npins; i++)
+ starfive_padctl_rmw(sfp, group->grp.pins[i], mask, value);
return 0;
}
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
index 9d71e8c13310..60160965cd29 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
@@ -307,7 +307,7 @@ static int jh7110_set_mux(struct pinctrl_dev *pctldev,
return -EINVAL;
pinmux = group->data;
- for (i = 0; i < group->num_pins; i++) {
+ for (i = 0; i < group->grp.npins; i++) {
u32 v = pinmux[i];
if (info->jh7110_set_one_pin_mux)
@@ -437,7 +437,7 @@ static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev,
if (!group)
return -EINVAL;
- return jh7110_pinconf_get(pctldev, group->pins[0], config);
+ return jh7110_pinconf_get(pctldev, group->grp.pins[0], config);
}
static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
@@ -508,8 +508,8 @@ static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
}
}
- for (i = 0; i < group->num_pins; i++)
- jh7110_padcfg_rmw(sfp, group->pins[i], mask, value);
+ for (i = 0; i < group->grp.npins; i++)
+ jh7110_padcfg_rmw(sfp, group->grp.pins[i], mask, value);
return 0;
}
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 09/22] pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP()
From: Andy Shevchenko @ 2023-11-28 19:56 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro.
Utilize them instead of open coded variants in the driver.
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
index 0cff44b07b29..4589900244c7 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
@@ -474,9 +474,8 @@ enum {
#undef WPCM450_GRP
};
-static struct group_desc wpcm450_groups[] = {
-#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \
- .num_pins = ARRAY_SIZE(x ## _pins) }
+static struct pingroup wpcm450_groups[] = {
+#define WPCM450_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins))
WPCM450_GRPS
#undef WPCM450_GRP
};
@@ -852,7 +851,7 @@ static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev,
const unsigned int **pins,
unsigned int *npins)
{
- *npins = wpcm450_groups[selector].num_pins;
+ *npins = wpcm450_groups[selector].npins;
*pins = wpcm450_groups[selector].pins;
return 0;
@@ -901,7 +900,7 @@ static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev,
struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
- wpcm450_groups[group].num_pins, function);
+ wpcm450_groups[group].npins, function);
return 0;
}
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 15/22] pinctrl: equilibrium: Convert to use grp member
From: Andy Shevchenko @ 2023-11-28 19:57 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
Convert drivers to use grp member embedded in struct group_desc.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/pinctrl-equilibrium.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c
index 4ebae516d1b1..6e1be38865c3 100644
--- a/drivers/pinctrl/pinctrl-equilibrium.c
+++ b/drivers/pinctrl/pinctrl-equilibrium.c
@@ -331,8 +331,8 @@ static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev,
return -EINVAL;
pinmux = grp->data;
- for (i = 0; i < grp->num_pins; i++)
- eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);
+ for (i = 0; i < grp->grp.npins; i++)
+ eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]);
return 0;
}
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 19/22] pinctrl: mediatek: Convert to use grp member
From: Andy Shevchenko @ 2023-11-28 19:57 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
Convert drivers to use grp member embedded in struct group_desc.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/mediatek/pinctrl-moore.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
index c3d59eddd994..d972584c0519 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -56,12 +56,12 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
return -EINVAL;
dev_dbg(pctldev->dev, "enable function %s group %s\n",
- func->name, grp->name);
+ func->name, grp->grp.name);
- for (i = 0; i < grp->num_pins; i++) {
+ for (i = 0; i < grp->grp.npins; i++) {
const struct mtk_pin_desc *desc;
int *pin_modes = grp->data;
- int pin = grp->pins[i];
+ int pin = grp->grp.pins[i];
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
@@ -602,13 +602,12 @@ static int mtk_build_groups(struct mtk_pinctrl *hw)
for (i = 0; i < hw->soc->ngrps; i++) {
const struct group_desc *group = hw->soc->grps + i;
+ const struct pingroup *grp = &group->grp;
- err = pinctrl_generic_add_group(hw->pctrl, group->name,
- group->pins, group->num_pins,
+ err = pinctrl_generic_add_group(hw->pctrl, grp->name, grp->pins, grp->npins,
group->data);
if (err < 0) {
- dev_err(hw->dev, "Failed to register group %s\n",
- group->name);
+ dev_err(hw->dev, "Failed to register group %s\n", grp->name);
return err;
}
}
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 05/22] pinctrl: imx: Use temporary variable to hold pins
From: Andy Shevchenko @ 2023-11-28 19:56 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
The pins are allocated from the heap, but in order to pass
them as constant object, we need to use non-constant pointer.
Achieve this by using a temporary variable.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 9bc16943014f..9099a7c81d4a 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -513,6 +513,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
+ int *pins;
int i;
dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
@@ -557,20 +558,20 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
grp->data = devm_kcalloc(ipctl->dev,
grp->num_pins, sizeof(struct imx_pin),
GFP_KERNEL);
- grp->pins = devm_kcalloc(ipctl->dev,
- grp->num_pins, sizeof(unsigned int),
- GFP_KERNEL);
- if (!grp->pins || !grp->data)
+ if (!grp->data)
return -ENOMEM;
+ pins = devm_kcalloc(ipctl->dev, grp->num_pins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+ grp->pins = pins;
+
for (i = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
if (info->flags & IMX_USE_SCU)
- info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
- pin, &list);
+ info->imx_pinctrl_parse_pin(ipctl, &pins[i], pin, &list);
else
- imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
- pin, &list, np);
+ imx_pinctrl_parse_pin_mmio(ipctl, &pins[i], pin, &list, np);
}
return 0;
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 04/22] pinctrl: equilibrium: Use temporary variable to hold pins
From: Andy Shevchenko @ 2023-11-28 19:56 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
The pins are allocated from the heap, but in order to pass
them as constant object, we need to use non-constant pointer.
Achieve this by using a temporary variable.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/pinctrl-equilibrium.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c
index 54755b583d3f..fd59cfdeefac 100644
--- a/drivers/pinctrl/pinctrl-equilibrium.c
+++ b/drivers/pinctrl/pinctrl-equilibrium.c
@@ -704,7 +704,7 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
{
struct device *dev = drvdata->dev;
struct device_node *node = dev->of_node;
- unsigned int *pinmux, pin_id, pinmux_id;
+ unsigned int *pins, *pinmux, pin_id, pinmux_id;
struct group_desc group;
struct device_node *np;
struct property *prop;
@@ -723,15 +723,14 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
}
group.num_pins = err;
group.name = prop->value;
- group.pins = devm_kcalloc(dev, group.num_pins,
- sizeof(*(group.pins)), GFP_KERNEL);
- if (!group.pins) {
+ pins = devm_kcalloc(dev, group.num_pins, sizeof(*pins), GFP_KERNEL);
+ if (!pins) {
of_node_put(np);
return -ENOMEM;
}
+ group.pins = pins;
- pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
- GFP_KERNEL);
+ pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux), GFP_KERNEL);
if (!pinmux) {
of_node_put(np);
return -ENOMEM;
@@ -750,7 +749,7 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
of_node_put(np);
return -EINVAL;
}
- group.pins[j] = pin_id;
+ pins[j] = pin_id;
if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
dev_err(dev, "Group %s: Read intel pinmux id failed\n",
group.name);
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 07/22] pinctrl: equilibrium: Convert to use struct pingroup
From: Andy Shevchenko @ 2023-11-28 19:56 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
The pin control header provides struct pingroup.
Utilize it instead of open coded variants in the driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/pinctrl-equilibrium.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c
index fd59cfdeefac..4ebae516d1b1 100644
--- a/drivers/pinctrl/pinctrl-equilibrium.c
+++ b/drivers/pinctrl/pinctrl-equilibrium.c
@@ -705,7 +705,7 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
struct device *dev = drvdata->dev;
struct device_node *node = dev->of_node;
unsigned int *pins, *pinmux, pin_id, pinmux_id;
- struct group_desc group;
+ struct pingroup group, *grp = &group;
struct device_node *np;
struct property *prop;
int j, err;
@@ -721,49 +721,49 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
of_node_put(np);
return err;
}
- group.num_pins = err;
- group.name = prop->value;
- pins = devm_kcalloc(dev, group.num_pins, sizeof(*pins), GFP_KERNEL);
+ grp->npins = err;
+ grp->name = prop->value;
+ pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL);
if (!pins) {
of_node_put(np);
return -ENOMEM;
}
- group.pins = pins;
+ grp->pins = pins;
- pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux), GFP_KERNEL);
+ pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL);
if (!pinmux) {
of_node_put(np);
return -ENOMEM;
}
- for (j = 0; j < group.num_pins; j++) {
+ for (j = 0; j < grp->npins; j++) {
if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
dev_err(dev, "Group %s: Read intel pins id failed\n",
- group.name);
+ grp->name);
of_node_put(np);
return -EINVAL;
}
if (pin_id >= drvdata->pctl_desc.npins) {
dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
- group.name, j, pin_id);
+ grp->name, j, pin_id);
of_node_put(np);
return -EINVAL;
}
pins[j] = pin_id;
if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
dev_err(dev, "Group %s: Read intel pinmux id failed\n",
- group.name);
+ grp->name);
of_node_put(np);
return -EINVAL;
}
pinmux[j] = pinmux_id;
}
- err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,
- group.pins, group.num_pins,
+ err = pinctrl_generic_add_group(drvdata->pctl_dev,
+ grp->name, grp->pins, grp->npins,
pinmux);
if (err < 0) {
- dev_err(dev, "Failed to register group %s\n", group.name);
+ dev_err(dev, "Failed to register group %s\n", grp->name);
of_node_put(np);
return err;
}
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 01/22] pinctrl: qcom: lpass-lpi: Replace kernel.h with what is being used
From: Andy Shevchenko @ 2023-11-28 19:56 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
Replace kernel.h with what exactly is being used, i.e. array_size.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index 206b2c0ca828..2017bc80314d 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -6,8 +6,8 @@
#ifndef __PINCTRL_LPASS_LPI_H__
#define __PINCTRL_LPASS_LPI_H__
+#include <linux/array_size.h>
#include <linux/bits.h>
-#include <linux/kernel.h>
#include "../core.h"
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH v3 02/22] pinctrl: qcom: lpass-lpi: Remove unused member in struct lpi_pingroup
From: Andy Shevchenko @ 2023-11-28 19:56 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Andy Shevchenko,
Rasmus Villemoes, Jonathan Neuschäfer, Krzysztof Kozlowski,
Uwe Kleine-König, Geert Uytterhoeven, Biju Das,
Claudiu Beznea, Jianlong Huang, linux-arm-kernel, linux-gpio,
linux-kernel, linux-mediatek, openbmc, linux-mips, linux-arm-msm,
linux-renesas-soc
Cc: Ray Jui, Scott Branden, Broadcom internal kernel review list,
Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai,
Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Sean Wang,
Paul Cercueil, Lakshmi Sowjanya D, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Emil Renner Berthing, Hal Feng
In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com>
The group is not used anywhere, remove it. And if needed, it should be
struct pingroup anyway.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 4 ----
.../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 16 -------------
.../pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 20 ----------------
.../pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 20 ----------------
.../pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 15 ------------
.../pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c | 16 -------------
.../pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 24 -------------------
.../pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 24 -------------------
.../pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 24 -------------------
9 files changed, 163 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index 2017bc80314d..a9b2f65c1ebe 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -45,11 +45,8 @@ struct pinctrl_pin_desc;
#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
{ \
- .group.name = "gpio" #id, \
- .group.pins = gpio##id##_pins, \
.pin = id, \
.slew_offset = soff, \
- .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
@@ -67,7 +64,6 @@ struct pinctrl_pin_desc;
#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0)
struct lpi_pingroup {
- struct group_desc group;
unsigned int pin;
/* Bit offset in slew register for SoundWire pins only */
int slew_offset;
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
index 99156217c6a5..6bb39812e1d8 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -36,22 +36,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static int gpio14_pins[] = { 14 };
-
static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
index b33483056f42..c0369baf3398 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
@@ -45,26 +45,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static int gpio14_pins[] = { 14 };
-static int gpio15_pins[] = { 15 };
-static int gpio16_pins[] = { 16 };
-static int gpio17_pins[] = { 17 };
-static int gpio18_pins[] = { 18 };
-
static const struct pinctrl_pin_desc sc8280xp_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
index e8a6f6f6af54..316d6fc69131 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
@@ -36,26 +36,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static int gpio14_pins[] = { 14 };
-static int gpio15_pins[] = { 15 };
-static int gpio16_pins[] = { 16 };
-static int gpio17_pins[] = { 17 };
-static int gpio18_pins[] = { 18 };
-
static const struct pinctrl_pin_desc sm6115_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
index cb10ce8d5d28..9791d9ba5087 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
@@ -36,21 +36,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-
static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
index 297cc95ac3c0..5b9a2cb216bd 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
@@ -36,22 +36,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static int gpio14_pins[] = { 14 };
-
static const struct pinctrl_pin_desc sm8350_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
index 2e7896791fc0..a028cbb49947 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
@@ -52,30 +52,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static int gpio14_pins[] = { 14 };
-static int gpio15_pins[] = { 15 };
-static int gpio16_pins[] = { 16 };
-static int gpio17_pins[] = { 17 };
-static int gpio18_pins[] = { 18 };
-static int gpio19_pins[] = { 19 };
-static int gpio20_pins[] = { 20 };
-static int gpio21_pins[] = { 21 };
-static int gpio22_pins[] = { 22 };
-
static const struct pinctrl_pin_desc sm8450_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
index 64458c3fbe5e..852192b044e1 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
@@ -52,30 +52,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static int gpio14_pins[] = { 14 };
-static int gpio15_pins[] = { 15 };
-static int gpio16_pins[] = { 16 };
-static int gpio17_pins[] = { 17 };
-static int gpio18_pins[] = { 18 };
-static int gpio19_pins[] = { 19 };
-static int gpio20_pins[] = { 20 };
-static int gpio21_pins[] = { 21 };
-static int gpio22_pins[] = { 22 };
-
static const struct pinctrl_pin_desc sm8550_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
index 6e4be91ff085..04400c832327 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
@@ -54,30 +54,6 @@ enum lpass_lpi_functions {
LPI_MUX__,
};
-static int gpio0_pins[] = { 0 };
-static int gpio1_pins[] = { 1 };
-static int gpio2_pins[] = { 2 };
-static int gpio3_pins[] = { 3 };
-static int gpio4_pins[] = { 4 };
-static int gpio5_pins[] = { 5 };
-static int gpio6_pins[] = { 6 };
-static int gpio7_pins[] = { 7 };
-static int gpio8_pins[] = { 8 };
-static int gpio9_pins[] = { 9 };
-static int gpio10_pins[] = { 10 };
-static int gpio11_pins[] = { 11 };
-static int gpio12_pins[] = { 12 };
-static int gpio13_pins[] = { 13 };
-static int gpio14_pins[] = { 14 };
-static int gpio15_pins[] = { 15 };
-static int gpio16_pins[] = { 16 };
-static int gpio17_pins[] = { 17 };
-static int gpio18_pins[] = { 18 };
-static int gpio19_pins[] = { 19 };
-static int gpio20_pins[] = { 20 };
-static int gpio21_pins[] = { 21 };
-static int gpio22_pins[] = { 22 };
-
static const struct pinctrl_pin_desc sm8650_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
--
2.43.0.rc1.1.gbec44491f096
^ permalink raw reply related
* [PATCH] dt-bindings: input: mediatek,pmic-keys: Drop incomplete example
From: Rob Herring @ 2023-11-28 21:48 UTC (permalink / raw)
To: Dmitry Torokhov, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Chen Zhong
Cc: linux-input, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
The example for the Mediatek PMIC keys is incomplete as the binding is
the full PMIC, not just the sub-functions. It is preferred for MFD
examples to be complete in the top-level MFD device binding rather than
piecemeal in each sub-function binding.
This also fixes an undocumented (by schema) compatible warning for
"mediatek,mt6397".
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../bindings/input/mediatek,pmic-keys.yaml | 24 +------------------
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml
index e34c9e78d38d..70567d92c746 100644
--- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml
+++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml
@@ -90,26 +90,4 @@ required:
unevaluatedProperties: false
-examples:
- - |
- #include <dt-bindings/input/input.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-
- pmic {
- compatible = "mediatek,mt6397";
-
- keys {
- compatible = "mediatek,mt6397-keys";
- mediatek,long-press-mode = <1>;
- power-off-time-sec = <0>;
-
- key-power {
- linux,keycodes = <KEY_POWER>;
- wakeup-source;
- };
-
- key-home {
- linux,keycodes = <KEY_VOLUMEDOWN>;
- };
- };
- };
+...
--
2.42.0
^ permalink raw reply related
* Re: [PATCH] fix comparison of unsigned expression < 0
From: Andrew Morton @ 2023-11-29 1:22 UTC (permalink / raw)
To: Haibo Li
Cc: linux-kernel, Andrey Ryabinin, Alexander Potapenko,
Andrey Konovalov, Dmitry Vyukov, Vincenzo Frascino,
Matthias Brugger, AngeloGioacchino Del Regno, kasan-dev, linux-mm,
linux-arm-kernel, linux-mediatek, xiaoming.yu, kernel test robot
In-Reply-To: <20231128075532.110251-1-haibo.li@mediatek.com>
On Tue, 28 Nov 2023 15:55:32 +0800 Haibo Li <haibo.li@mediatek.com> wrote:
> Kernel test robot reported:
>
> '''
> mm/kasan/report.c:637 kasan_non_canonical_hook() warn:
> unsigned 'addr' is never less than zero.
> '''
> The KASAN_SHADOW_OFFSET is 0 on loongarch64.
>
> To fix it,check the KASAN_SHADOW_OFFSET before do comparison.
>
> --- a/mm/kasan/report.c
> +++ b/mm/kasan/report.c
> @@ -634,10 +634,10 @@ void kasan_non_canonical_hook(unsigned long addr)
> {
> unsigned long orig_addr;
> const char *bug_type;
> -
> +#if KASAN_SHADOW_OFFSET > 0
> if (addr < KASAN_SHADOW_OFFSET)
> return;
> -
> +#endif
We'd rather not add ugly ifdefs for a simple test like this. If we
replace "<" with "<=", does it fix? I suspect that's wrong.
But really, some hardwired comparison with an absolute address seems
lazy. If KASAN_SHADOW_OFFSET is variable on a per-architecture basis
then the expression which checks the validity of an arbitrary address
should also be per-architecture.
^ permalink raw reply
* Re: [PATCH v1 1/2] mmc: mediatek: add support for 64-steps tuning
From: Chaotian Jing (井朝天) @ 2023-11-29 1:39 UTC (permalink / raw)
To: robh+dt@kernel.org, Wenbin Mei (梅文彬),
conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
matthias.bgg@gmail.com, ulf.hansson@linaro.org,
Axe Yang (杨磊),
angelogioacchino.delregno@collabora.com
Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, Project_Global_Chrome_Upstream_Group
In-Reply-To: <20231124070839.12484-2-axe.yang@mediatek.com>
On Fri, 2023-11-24 at 15:08 +0800, Axe Yang wrote:
> Previously, during the MSDC calibration process, a full clock cycle
> actually not be covered, which in some cases didn't yield the best
> results and could cause CRC errors. This problem is particularly
> evident when MSDC is used as an SDIO host. To solve this issue, the
> tuning step should be extended from 32 to 64. By using 64-steps
> tuning, a complete clock cycle can be covered.
>
> To illustrate, when tuning 32-steps, if the obtained window has a
> hole
> near the middle, like this: 0xffc07ff (hex), then the selected delay
> will be the 6 (counting from right to left).
>
> (32 <- 1)
> 1111 1111 1100 0000 0000 0111 11(1)1 1111
>
> However, if we tune 64-steps, the window obtained may look like this:
> 0xfffffffffffc07ff. The final selected delay will be 44, which is
> safer as it is further away from the hole:
>
> (64 <- 1)
> 1111 ... (1)111 1111 1111 1111 1111 1100 0000 0000 0111 1111 1111
>
> In this case, delay 6 selected through 32-steps tuning is obviously
> not optimal, and this delay is closer to the hole, using it would
> easily cause CRC problems.
>
> You will need to add property "mediatek,tune-64-steps" in MSDC dts
> node to enable the feature.
>
> Signed-off-by: Axe Yang <axe.yang@mediatek.com>
> ---
> drivers/mmc/host/mtk-sd.c | 133 +++++++++++++++++++++++++++---------
> --
> 1 file changed, 97 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 97f7c3d4be6e..aa955240e441 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -252,12 +252,16 @@
>
> #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW
> */
> #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */
> +#define MSDC_PAD_TUNE_DATRRDLY2 GENMASK(12, 8) /* RW */
> #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */
> +#define MSDC_PAD_TUNE_CMDRDLY2 GENMASK(20, 16) /* RW */
> #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */
> #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */
> #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */
> #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */
> #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */
> +#define MSDC_PAD_TUNE_RD2_SEL BIT(13) /* RW */
> +#define MSDC_PAD_TUNE_CMD2_SEL BIT(21) /* RW */
>
> #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */
> #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */
> @@ -325,7 +329,8 @@
>
> #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
>
> -#define PAD_DELAY_MAX 32 /* PAD delay cells */
> +#define PAD_DELAY_HALF 32 /* PAD delay cells */
> +#define PAD_DELAY_FULL 64
> /*----------------------------------------------------------------
> ----------*/
> /* Descriptor
> Structure */
> /*----------------------------------------------------------------
> ----------*/
> @@ -465,6 +470,7 @@ struct msdc_host {
> /* cmd response sample selection for
> HS400 */
> bool hs400_mode; /* current eMMC will run at hs400 mode */
> bool hs400_tuning; /* hs400 mode online tuning */
> + bool tune_64steps;
> bool internal_cd; /* Use internal card-detect logic */
> bool cqhci; /* support eMMC hw cmdq */
> struct msdc_save_para save_para; /* used when gate HCLK */
> @@ -1615,7 +1621,7 @@ static irqreturn_t msdc_cmdq_irq(struct
> msdc_host *host, u32 intsts)
> }
>
> if (cmd_err || dat_err) {
> - dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts =
> 0x%x",
> + dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts
> = 0x%x",
> cmd_err, dat_err, intsts);
> }
>
> @@ -1780,10 +1786,20 @@ static void msdc_init_hw(struct msdc_host
> *host)
> DATA_K_VALUE_SEL);
> sdr_set_bits(host->top_base + EMMC_TOP_CMD,
> PAD_CMD_RD_RXDLY_SEL);
> + if (host->tune_64steps) {
> + sdr_set_bits(host->top_base +
> EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY2_SEL);
> + sdr_set_bits(host->top_base +
> EMMC_TOP_CMD,
> + PAD_CMD_RD_RXDLY2_SEL);
> + }
> } else {
> sdr_set_bits(host->base + tune_reg,
> MSDC_PAD_TUNE_RD_SEL |
> MSDC_PAD_TUNE_CMD_SEL);
> + if (host->tune_64steps)
> + sdr_set_bits(host->base + tune_reg + 4,
> + MSDC_PAD_TUNE_RD2_SEL |
> + MSDC_PAD_TUNE_CMD2_SEL);
> }
> } else {
> /* choose clock tune */
> @@ -1925,24 +1941,24 @@ static void msdc_ops_set_ios(struct mmc_host
> *mmc, struct mmc_ios *ios)
> msdc_set_mclk(host, ios->timing, ios->clock);
> }
>
> -static u32 test_delay_bit(u32 delay, u32 bit)
> +static u64 test_delay_bit(u64 delay, u32 bit)
> {
> - bit %= PAD_DELAY_MAX;
> + bit %= PAD_DELAY_FULL;
> return delay & BIT(bit);
Since you are testing > 32 bits, you should use BIT_ULL() to instead of
BIT().
> }
>
> -static int get_delay_len(u32 delay, u32 start_bit)
> +static int get_delay_len(u64 delay, u32 start_bit)
> {
> int i;
>
> - for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
> + for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
> if (test_delay_bit(delay, start_bit + i) == 0)
> return i;
> }
> - return PAD_DELAY_MAX - start_bit;
> + return PAD_DELAY_FULL - start_bit;
> }
>
> -static struct msdc_delay_phase get_best_delay(struct msdc_host
> *host, u32 delay)
> +static struct msdc_delay_phase get_best_delay(struct msdc_host
> *host, u64 delay)
> {
> int start = 0, len = 0;
> int start_final = 0, len_final = 0;
> @@ -1950,28 +1966,28 @@ static struct msdc_delay_phase
> get_best_delay(struct msdc_host *host, u32 delay)
> struct msdc_delay_phase delay_phase = { 0, };
>
> if (delay == 0) {
> - dev_err(host->dev, "phase error: [map:%x]\n", delay);
> + dev_err(host->dev, "phase error: [map:%llx]\n", delay);
> delay_phase.final_phase = final_phase;
> return delay_phase;
> }
>
> - while (start < PAD_DELAY_MAX) {
> + while (start < PAD_DELAY_FULL) {
> len = get_delay_len(delay, start);
> if (len_final < len) {
> start_final = start;
> len_final = len;
> }
> start += len ? len : 1;
> - if (len >= 12 && start_final < 4)
> + if (!upper_32_bits(delay) && len >= 12 && start_final <
> 4)
> break;
> }
>
> /* The rule is that to find the smallest delay cell */
> if (start_final == 0)
> - final_phase = (start_final + len_final / 3) %
> PAD_DELAY_MAX;
> + final_phase = (start_final + len_final / 3) %
> PAD_DELAY_FULL;
> else
> - final_phase = (start_final + len_final / 2) %
> PAD_DELAY_MAX;
> - dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
> + final_phase = (start_final + len_final / 2) %
> PAD_DELAY_FULL;
> + dev_dbg(host->dev, "phase: [map:%llx] [maxlen:%d]
> [final:%d]\n",
> delay, len_final, final_phase);
>
> delay_phase.maxlen = len_final;
> @@ -1984,24 +2000,62 @@ static inline void msdc_set_cmd_delay(struct
> msdc_host *host, u32 value)
> {
> u32 tune_reg = host->dev_comp->pad_tune_reg;
>
> - if (host->top_base)
> - sdr_set_field(host->top_base + EMMC_TOP_CMD,
> PAD_CMD_RXDLY,
> - value);
> - else
> - sdr_set_field(host->base + tune_reg,
> MSDC_PAD_TUNE_CMDRDLY,
> - value);
> + if (host->top_base) {
> + if (value < PAD_DELAY_HALF) {
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> PAD_CMD_RXDLY,
> + value);
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> PAD_CMD_RXDLY2,
> + 0);
> + } else {
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> PAD_CMD_RXDLY,
> + PAD_DELAY_HALF - 1);
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> PAD_CMD_RXDLY2,
> + value - PAD_DELAY_HALF);
> + }
> + } else {
> + if (value < PAD_DELAY_HALF) {
> + sdr_set_field(host->base + tune_reg,
> MSDC_PAD_TUNE_CMDRDLY,
> + value);
> + sdr_set_field(host->base + tune_reg + 4,
> MSDC_PAD_TUNE_CMDRDLY2,
> + 0);
> + } else {
> + sdr_set_field(host->base + tune_reg,
> MSDC_PAD_TUNE_CMDRDLY,
> + PAD_DELAY_HALF - 1);
> + sdr_set_field(host->base + tune_reg + 4,
> MSDC_PAD_TUNE_CMDRDLY2,
> + value - PAD_DELAY_HALF);
> + }
> + }
> }
>
> static inline void msdc_set_data_delay(struct msdc_host *host, u32
> value)
> {
> u32 tune_reg = host->dev_comp->pad_tune_reg;
>
> - if (host->top_base)
> - sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> - PAD_DAT_RD_RXDLY, value);
> - else
> - sdr_set_field(host->base + tune_reg,
> MSDC_PAD_TUNE_DATRRDLY,
> - value);
> + if (host->top_base) {
> + if (value < PAD_DELAY_HALF) {
> + sdr_set_field(host->top_base +
> EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, value);
> + sdr_set_field(host->top_base +
> EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY2, 0);
> + } else {
> + sdr_set_field(host->top_base +
> EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, PAD_DELAY_HALF
> - 1);
> + sdr_set_field(host->top_base +
> EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY2, value -
> PAD_DELAY_HALF);
> + }
> + } else {
> + if (value < PAD_DELAY_HALF) {
> + sdr_set_field(host->base + tune_reg,
> MSDC_PAD_TUNE_DATRRDLY,
> + value);
> + sdr_set_field(host->base + tune_reg + 4,
> MSDC_PAD_TUNE_DATRRDLY2,
> + 0);
> + } else {
> + sdr_set_field(host->base + tune_reg,
> MSDC_PAD_TUNE_DATRRDLY,
> + PAD_DELAY_HALF - 1);
> + sdr_set_field(host->base + tune_reg + 4,
> MSDC_PAD_TUNE_DATRRDLY2,
> + value - PAD_DELAY_HALF);
> + }
> + }
> }
>
> static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
> @@ -2023,7 +2077,7 @@ static int msdc_tune_response(struct mmc_host
> *mmc, u32 opcode)
> host->hs200_cmd_int_delay);
>
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> - for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> + for (i = 0 ; i < PAD_DELAY_HALF; i++) {
> msdc_set_cmd_delay(host, i);
> /*
> * Using the same parameters, it may sometimes pass the
> test,
> @@ -2047,7 +2101,7 @@ static int msdc_tune_response(struct mmc_host
> *mmc, u32 opcode)
> goto skip_fall;
>
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> - for (i = 0; i < PAD_DELAY_MAX; i++) {
> + for (i = 0; i < PAD_DELAY_HALF; i++) {
> msdc_set_cmd_delay(host, i);
> /*
> * Using the same parameters, it may sometimes pass the
> test,
> @@ -2082,7 +2136,7 @@ static int msdc_tune_response(struct mmc_host
> *mmc, u32 opcode)
> if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
> goto skip_internal;
>
> - for (i = 0; i < PAD_DELAY_MAX; i++) {
> + for (i = 0; i < PAD_DELAY_HALF; i++) {
> sdr_set_field(host->base + tune_reg,
> MSDC_PAD_TUNE_CMDRRDLY, i);
> mmc_send_tuning(mmc, opcode, &cmd_err);
> @@ -2121,7 +2175,7 @@ static int hs400_tune_response(struct mmc_host
> *mmc, u32 opcode)
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> else
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> - for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> + for (i = 0 ; i < PAD_DELAY_HALF; i++) {
> sdr_set_field(host->base + PAD_CMD_TUNE,
> PAD_CMD_TUNE_RX_DLY3, i);
> /*
> @@ -2160,7 +2214,7 @@ static int msdc_tune_data(struct mmc_host *mmc,
> u32 opcode)
> host->latch_ck);
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
> - for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> + for (i = 0 ; i < PAD_DELAY_HALF; i++) {
> msdc_set_data_delay(host, i);
> ret = mmc_send_tuning(mmc, opcode, NULL);
> if (!ret)
> @@ -2174,7 +2228,7 @@ static int msdc_tune_data(struct mmc_host *mmc,
> u32 opcode)
>
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
> - for (i = 0; i < PAD_DELAY_MAX; i++) {
> + for (i = 0; i < PAD_DELAY_HALF; i++) {
> msdc_set_data_delay(host, i);
> ret = mmc_send_tuning(mmc, opcode, NULL);
> if (!ret)
> @@ -2206,10 +2260,11 @@ static int msdc_tune_data(struct mmc_host
> *mmc, u32 opcode)
> static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
> {
> struct msdc_host *host = mmc_priv(mmc);
> - u32 rise_delay = 0, fall_delay = 0;
> + u64 rise_delay = 0, fall_delay = 0;
> struct msdc_delay_phase final_rise_delay, final_fall_delay = {
> 0,};
> u8 final_delay, final_maxlen;
> int i, ret;
> + int tune_steps = host->tune_64steps ? PAD_DELAY_FULL :
> PAD_DELAY_HALF;
>
> sdr_set_field(host->base + MSDC_PATCH_BIT,
> MSDC_INT_DAT_LATCH_CK_SEL,
> host->latch_ck);
> @@ -2217,7 +2272,7 @@ static int msdc_tune_together(struct mmc_host
> *mmc, u32 opcode)
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> sdr_clr_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> - for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> + for (i = 0 ; i < tune_steps; i++) {
> msdc_set_cmd_delay(host, i);
> msdc_set_data_delay(host, i);
> ret = mmc_send_tuning(mmc, opcode, NULL);
> @@ -2233,7 +2288,7 @@ static int msdc_tune_together(struct mmc_host
> *mmc, u32 opcode)
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> sdr_set_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> - for (i = 0; i < PAD_DELAY_MAX; i++) {
> + for (i = 0; i < tune_steps; i++) {
> msdc_set_cmd_delay(host, i);
> msdc_set_data_delay(host, i);
> ret = mmc_send_tuning(mmc, opcode, NULL);
> @@ -2346,7 +2401,7 @@ static int msdc_execute_hs400_tuning(struct
> mmc_host *mmc, struct mmc_card *card
> }
>
> host->hs400_tuning = true;
> - for (i = 0; i < PAD_DELAY_MAX; i++) {
> + for (i = 0; i < PAD_DELAY_HALF; i++) {
> if (host->top_base)
> sdr_set_field(host->top_base +
> EMMC50_PAD_DS_TUNE,
> PAD_DS_DLY1, i);
> @@ -2601,6 +2656,12 @@ static void msdc_of_property_parse(struct
> platform_device *pdev,
> else
> host->hs400_cmd_resp_sel_rising = false;
>
> + if (of_property_read_bool(pdev->dev.of_node,
> + "mediatek,tune-64-steps"))
> + host->tune_64steps = true;
> + else
> + host->tune_64steps = false;
> +
> if (of_property_read_bool(pdev->dev.of_node,
> "supports-cqe"))
> host->cqhci = true;
^ permalink raw reply
* [PATCH v2] mmc: mtk-sd: Increase the verbosity of msdc_track_cmd_data
From: Pin-yen Lin @ 2023-11-29 2:59 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: linux-arm-kernel, linux-kernel, ot_shunxi.zhang, Chen-Yu Tsai,
linux-mmc, linux-mediatek, Pin-yen Lin
This log message is necessary for debugging, so enable it by default to
debug issues that are hard to reproduce locally.
Signed-off-by: Pin-yen Lin <treapking@chromium.org>
---
Changes in v2:
- Use dev_warn() instead of dev_err()
drivers/mmc/host/mtk-sd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 97f7c3d4be6e..907c13d746c1 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1150,8 +1150,8 @@ static void msdc_recheck_sdio_irq(struct msdc_host *host)
static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
{
if (host->error)
- dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
- __func__, cmd->opcode, cmd->arg, host->error);
+ dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
+ __func__, cmd->opcode, cmd->arg, host->error);
}
static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
--
2.43.0.rc1.413.gea7ed67945-goog
^ permalink raw reply related
* Re: [PATCH] fix comparison of unsigned expression < 0
From: Andrey Konovalov @ 2023-11-29 3:01 UTC (permalink / raw)
To: Andrew Morton, kernel test robot, Haibo Li
Cc: linux-kernel, Andrey Ryabinin, Alexander Potapenko, Dmitry Vyukov,
Vincenzo Frascino, Matthias Brugger, AngeloGioacchino Del Regno,
kasan-dev, linux-mm, linux-arm-kernel, linux-mediatek,
xiaoming.yu
In-Reply-To: <20231128172238.f80ed8dd74ab2a13eba33091@linux-foundation.org>
On Wed, Nov 29, 2023 at 2:22 AM Andrew Morton <akpm@linux-foundation.org> wrote:
>
> On Tue, 28 Nov 2023 15:55:32 +0800 Haibo Li <haibo.li@mediatek.com> wrote:
>
> > Kernel test robot reported:
> >
> > '''
> > mm/kasan/report.c:637 kasan_non_canonical_hook() warn:
> > unsigned 'addr' is never less than zero.
> > '''
> > The KASAN_SHADOW_OFFSET is 0 on loongarch64.
> >
> > To fix it,check the KASAN_SHADOW_OFFSET before do comparison.
> >
> > --- a/mm/kasan/report.c
> > +++ b/mm/kasan/report.c
> > @@ -634,10 +634,10 @@ void kasan_non_canonical_hook(unsigned long addr)
> > {
> > unsigned long orig_addr;
> > const char *bug_type;
> > -
> > +#if KASAN_SHADOW_OFFSET > 0
> > if (addr < KASAN_SHADOW_OFFSET)
> > return;
> > -
> > +#endif
>
> We'd rather not add ugly ifdefs for a simple test like this. If we
> replace "<" with "<=", does it fix? I suspect that's wrong.
Changing the comparison into "<=" would be wrong.
But I actually don't think we need to fix anything here.
This issue looks quite close to a similar comparison with 0 issue
Linus shared his opinion on here:
https://lore.kernel.org/all/Pine.LNX.4.58.0411230958260.20993@ppc970.osdl.org/
I don't know if the common consensus with the regard to issues like
that changed since then. But if not, perhaps we can treat this kernel
test robot report as a false positive.
Thanks!
^ permalink raw reply
* Re: [PATCH v2 2/2] mmc: mediatek: extend number of tuning steps
From: Axe Yang (杨磊) @ 2023-11-29 3:16 UTC (permalink / raw)
To: robh+dt@kernel.org, Wenbin Mei (梅文彬),
Chaotian Jing (井朝天), conor+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
ulf.hansson@linaro.org, angelogioacchino.delregno@collabora.com
Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, Project_Global_Chrome_Upstream_Group
In-Reply-To: <36ba3f89-2bd0-45f0-8b61-59f5c6691427@collabora.com>
On Tue, 2023-11-28 at 11:20 +0100, AngeloGioacchino Del Regno wrote:
> Il 28/11/23 10:38, Axe Yang (杨磊) ha scritto:
> > > On Tue, 2023-11-28 at 09:53 +0100, AngeloGioacchino Del Regno
> > > wrote:
> > > Il 28/11/23 08:01, Axe Yang ha scritto:
> > > > Previously, during the MSDC calibration process, a full clock
> > > > cycle
> > > > actually not be covered, which in some cases didn't yield the
> > > > best
> > > > results and could cause CRC errors. This problem is
> > > > particularly
> > > > evident when MSDC is used as an SDIO host. In fact, MSDC
> > > > support
> > > > tuning up to a maximum of 64 steps, but by default, the step
> > > > number
> > > > is 32. By increase the tuning step, we are more likely to cover
> > > > more
> > > > parts of a clock cycle, and get better calibration result.
> > > >
> > > > To illustrate, when tuning 32 steps, if the obtained window has
> > > > a
> > > > hole
> > > > near the middle, like this: 0xffc07ff (hex), then the selected
> > > > delay
> > > > will be the 6 (counting from right to left).
> > > >
> > > > (32 <- 1)
> > > > 1111 1111 1100 0000 0000 0111 11(1)1 1111
> > > >
> > > > However, if we tune 64 steps, the window obtained may look like
> > > > this:
> > > > 0xfffffffffffc07ff. The final selected delay will be 44, which
> > > > is
> > > > safer as it is further away from the hole:
> > > >
> > > > (64 <- 1)
> > > > 1111 ... (1)111 1111 1111 1111 1111 1100 0000 0000 0111 1111
> > > > 1111
> > > >
> > > > In this case, delay 6 selected through 32 steps tuning is
> > > > obviously
> > > > not optimal, and this delay is closer to the hole, using it
> > > > would
> > > > easily cause CRC problems.
> > > >
> > > > You will need to configure property "mediatek,tuning-step" in
> > > > MSDC
> > > > dts node to 64 to extend the steps.
> > > >
> > >
> > > If we can run 64 tuning steps, why should we run 32?
> > >
> > > Why isn't it just better to *always* run 64 tuning steps, on SoCs
> > > supporting that?
> > >
> > > Thanks,
> > > Angelo
> >
> > Hi Angelo,
> >
> > That is a good question. The benefit of preserving 32 steps tuning
> > is
> > that it can save time in certain scenarios.
> >
> > On some platforms, when the delay selected through 64 steps tuning
> > is
> > very close to that chosen through 32 steps, we can reduce the
> > tuning
> > step from 64 to 32. This can save time sending the tuning block
> > commands.
> >
> > Thus using 32 steps tuning can save kernel boot up time.
> >
> > Another case where time can be saved is when accessing the RPMB
> > partition of eMMC. Each time switch to RPMB partition, there is a
> > retune action, causing a certain drop in performance. If we are
> > certain
> > that the results of 32 steps tuning are usable and we use it, this
> > can
> > in a sense also guarantee performance when accessing the RPMB
> > partition.
> >
>
> Thanks for this explanation! Though, I have some more questions...
>
> ...regarding boot up time, how much time are we talking about?
Luckily, I have a platform at hand that can be used for experiments/
Below are the results from testing on this platform:
[ 2.431993][T1200180] kworker/2:21: mtk-msdc bootdevice:
[name:mtk_sd&]Start tuning
[ 2.434950][T1200180] kworker/2:21: mtk-msdc bootdevice:
[name:mtk_sd&]Tuning finished
[ 2.435957][T1200180] kworker/2:21: mtk-msdc bootdevice:
[name:mtk_sd&]phase: [map:00000000ffffffc0] [maxlen:26] [final:19]
[ 2.462375][T1200180] kworker/2:21: [name:mmc_core&]mmc0: new HS400
MMC card at address 0001
...
[ 2.519863][T1300069] kworker/3:1: mtk-msdc 11250000.mmc:
[name:mtk_sd&]Start tuning
[ 2.526271][T1300069] kworker/3:1: mtk-msdc 11250000.mmc:
[name:mtk_sd&]Tuning finished
[ 2.527288][T1300069] kworker/3:1: mtk-msdc 11250000.mmc:
[name:mtk_sd&]phase: [map:ffffffffffff003f] [maxlen:48] [final:40]
[ 2.532269][T1300069] kworker/3:1: [name:mmc_core&]mmc2: new ultra
high speed SDR104 SDIO card at address 0001
As the kernel log indicates, it took 3 ms for eMMC to tune 32 steps,
while it took about 7 ms for SDIO to tune 64 steps. I have to admit,
when it comes to saving boot up time, the benefits of reducing step
form 64 to 32 are quite minimal. Just as you said, especially when
async probe is enabled.
>
> I'm asking because while now I see - and agree - on using 32-steps
> tuning
> on eMMC to guarantee performance during RPMB access, as far as I
> know,
> there is no RPMB partition on SD/MicroSD cards (and, of course, SDIO
> devices).
>
> If the boot performance impact isn't big, as in, up to ~100
> milliseconds is
> not big at all (especially with async probe!), we can definitely
> avoid the
> addition of a devicetree property for 32-steps tuning, hence use a
> dynamic
> selection strategy such that:
> - On eMMC devices, always perform 32-steps tuning (hence no boot
> delay)
> - On SD cards and SDIO, always perform 64-steps tuning
eMMC could also potentially have CRC issue if only tune 32-steps,
albeit with a lower likelihood. The precondition for using 32-steps
tuning is that it could provide roughly the same valid results as using
64-steps tuning. So taking everything into account, controlling the
tuning step as needed through the use of dts property seems to be a
more flixible approach.
Regards,
Axe
>
^ permalink raw reply
* Re: [PATCH] fix comparison of unsigned expression < 0
From: Haibo Li @ 2023-11-29 3:42 UTC (permalink / raw)
To: andreyknvl
Cc: akpm, angelogioacchino.delregno, dvyukov, glider, haibo.li,
kasan-dev, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-mm, lkp, matthias.bgg, ryabinin.a.a, vincenzo.frascino,
xiaoming.yu
In-Reply-To: <CA+fCnZcLwXn6crGF1E1cY3TknMaUN=H8-_hp0-cC+s8-wj95PQ@mail.gmail.com>
> On Wed, Nov 29, 2023 at 2:22 AM Andrew Morton <akpm@linux-foundation.org> wrote:
> >
> > On Tue, 28 Nov 2023 15:55:32 +0800 Haibo Li <haibo.li@mediatek.com> wrote:
> >
> > > Kernel test robot reported:
> > >
> > > '''
> > > mm/kasan/report.c:637 kasan_non_canonical_hook() warn:
> > > unsigned 'addr' is never less than zero.
> > > '''
> > > The KASAN_SHADOW_OFFSET is 0 on loongarch64.
> > >
> > > To fix it,check the KASAN_SHADOW_OFFSET before do comparison.
> > >
> > > --- a/mm/kasan/report.c
> > > +++ b/mm/kasan/report.c
> > > @@ -634,10 +634,10 @@ void kasan_non_canonical_hook(unsigned long addr)
> > > {
> > > unsigned long orig_addr;
> > > const char *bug_type;
> > > -
> > > +#if KASAN_SHADOW_OFFSET > 0
> > > if (addr < KASAN_SHADOW_OFFSET)
> > > return;
> > > -
> > > +#endif
> >
> > We'd rather not add ugly ifdefs for a simple test like this. If we
> > replace "<" with "<=", does it fix? I suspect that's wrong.
>
> Changing the comparison into "<=" would be wrong.
>
> But I actually don't think we need to fix anything here.
>
> This issue looks quite close to a similar comparison with 0 issue
> Linus shared his opinion on here:
>
> https://lore.kernel.org/all/Pine.LNX.4.58.0411230958260.20993@ppc970.osdl.org/
>
> I don't know if the common consensus with the regard to issues like
> that changed since then. But if not, perhaps we can treat this kernel
> test robot report as a false positive.
>
> Thanks!
Thanks for the information.Let's keep it as unchanged.
^ permalink raw reply
* [PATCH v3,2/2] wifi: mac80211: refactor STA CSA parsing flows
From: Michael-CY Lee @ 2023-11-29 5:43 UTC (permalink / raw)
To: linux-wireless
Cc: Johannes Berg, Felix Fietkau, Lorenzo Bianconi, Evelyn Tsai,
Money Wang, linux-mediatek, Michael-CY Lee
In-Reply-To: <20231129054321.10199-1-michael-cy.lee@mediatek.com>
The new Wi-Fi Standard (IEEE P80211be D4.1) specifies that the Wide
Bandwidth Channel Switch (WBCS) Element subfields have the same
definitions as VHT operation information if the operating band is not
S1G.
The problem comes when the BSS is in 6 GHz band, the STA parses the WBCS
Element by ieee80211_chandef_vht_oper(), which checks the capabilities for
HT/VHT mode, not HE/EHT mode.
This patch refactors STA CSA parsing flow so that the corresponding
capabilities can be checked. Also, it adds the way to use op_class in ECSA
Element to build a new chandef.
In summary, the new steps for STA to handle CSA event are:
1. build the new chandef from the CSA-related Elements.
(CSA, ECSA, WBCS, etc.)
2. convert the new chandef into operation information according to the
operating band in order to check if the new chandef fits STA's
capabilities.
3. downgrade the bandwidth until current bandwidth is not disabled.
Signed-off-by: Michael-CY Lee <michael-cy.lee@mediatek.com>
Signed-off-by: Money Wang <money.wang@mediatek.com>
---
v3:
Version 2 follows draft 3.2, while version 3 follows draft 4.1.
Also, version 3 simplifies the CSA handling steps.
---
net/mac80211/spectmgmt.c | 349 +++++++++++++++++++++++++++++++++------
1 file changed, 294 insertions(+), 55 deletions(-)
diff --git a/net/mac80211/spectmgmt.c b/net/mac80211/spectmgmt.c
index 55959b0b24c5..9a5f743ee750 100644
--- a/net/mac80211/spectmgmt.c
+++ b/net/mac80211/spectmgmt.c
@@ -19,6 +19,236 @@
#include "sta_info.h"
#include "wme.h"
+static inline void
+wbcs_ie_to_chandef(const struct ieee80211_wide_bw_chansw_ie *wbcs_ie,
+ struct cfg80211_chan_def *chandef)
+{
+ u8 ccfs0 = wbcs_ie->new_center_freq_seg0;
+ u8 ccfs1 = wbcs_ie->new_center_freq_seg1;
+ u32 cf0 = ieee80211_channel_to_frequency(ccfs0, chandef->chan->band);
+ u32 cf1 = ieee80211_channel_to_frequency(ccfs1, chandef->chan->band);
+
+ switch (wbcs_ie->new_channel_width) {
+ case IEEE80211_VHT_CHANWIDTH_160MHZ:
+ chandef->width = NL80211_CHAN_WIDTH_160;
+ chandef->center_freq1 = cf0;
+ break;
+ case IEEE80211_VHT_CHANWIDTH_80P80MHZ:
+ chandef->width = NL80211_CHAN_WIDTH_80P80;
+ chandef->center_freq1 = cf0;
+ chandef->center_freq2 = cf1;
+ break;
+ case IEEE80211_VHT_CHANWIDTH_80MHZ:
+ chandef->width = NL80211_CHAN_WIDTH_80;
+ chandef->center_freq1 = cf0;
+
+ if (ccfs1) {
+ u8 diff = abs(ccfs0 - ccfs1);
+
+ if (diff == 8) {
+ chandef->width = NL80211_CHAN_WIDTH_160;
+ chandef->center_freq1 = cf1;
+ } else if (diff > 8) {
+ chandef->width = NL80211_CHAN_WIDTH_80P80;
+ chandef->center_freq2 = cf1;
+ }
+ }
+ break;
+ case IEEE80211_VHT_CHANWIDTH_USE_HT:
+ default:
+ /* If the WBCS Element is present, new channel bandwidth is
+ * at least 40 MHz.
+ */
+ chandef->width = NL80211_CHAN_WIDTH_40;
+ chandef->center_freq1 = cf0;
+ break;
+ }
+}
+
+static inline int
+validate_chandef_by_ht_vht_oper(struct ieee80211_sub_if_data *sdata,
+ ieee80211_conn_flags_t conn_flags,
+ u32 vht_cap_info,
+ struct cfg80211_chan_def *chandef)
+{
+ u32 control_freq, center_freq1, center_freq2;
+ enum nl80211_chan_width chan_width;
+ struct ieee80211_ht_operation *ht_oper = NULL;
+ struct ieee80211_vht_operation *vht_oper = NULL;
+
+ if (conn_flags & (IEEE80211_CONN_DISABLE_HT |
+ IEEE80211_CONN_DISABLE_40MHZ)) {
+ chandef->chan = NULL;
+ return 0;
+ }
+
+ control_freq = chandef->chan->center_freq;
+ center_freq1 = chandef->center_freq1;
+ center_freq2 = chandef->center_freq2;
+ chan_width = chandef->width;
+
+ ht_oper = kzalloc(sizeof(*ht_oper), GFP_KERNEL);
+ if (!ht_oper)
+ return -ENOMEM;
+
+ ht_oper->primary_chan = ieee80211_frequency_to_channel(control_freq);
+ if (control_freq != center_freq1)
+ ht_oper->ht_param = control_freq > center_freq1 ?
+ IEEE80211_HT_PARAM_CHA_SEC_BELOW :
+ IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
+ else
+ ht_oper->ht_param = IEEE80211_HT_PARAM_CHA_SEC_NONE;
+
+ ieee80211_chandef_ht_oper(ht_oper, chandef);
+
+ if (conn_flags & IEEE80211_CONN_DISABLE_VHT) {
+ kfree(ht_oper);
+ return 0;
+ }
+
+ vht_oper = kzalloc(sizeof(*vht_oper), GFP_KERNEL);
+ if (!vht_oper) {
+ kfree(ht_oper);
+ return -ENOMEM;
+ }
+
+ vht_oper->center_freq_seg0_idx =
+ ieee80211_frequency_to_channel(center_freq1);
+ vht_oper->center_freq_seg1_idx = center_freq2 ?
+ ieee80211_frequency_to_channel(center_freq2) : 0;
+
+ switch (chan_width) {
+ case NL80211_CHAN_WIDTH_320:
+ WARN_ON(1);
+ break;
+ case NL80211_CHAN_WIDTH_160:
+ vht_oper->chan_width = IEEE80211_VHT_CHANWIDTH_80MHZ;
+ vht_oper->center_freq_seg1_idx = vht_oper->center_freq_seg0_idx;
+ vht_oper->center_freq_seg0_idx +=
+ control_freq < center_freq1 ? -8 : 8;
+ break;
+ case NL80211_CHAN_WIDTH_80P80:
+ vht_oper->chan_width = IEEE80211_VHT_CHANWIDTH_80MHZ;
+ break;
+ case NL80211_CHAN_WIDTH_80:
+ vht_oper->chan_width = IEEE80211_VHT_CHANWIDTH_80MHZ;
+ break;
+ default:
+ vht_oper->chan_width = IEEE80211_VHT_CHANWIDTH_USE_HT;
+ break;
+ }
+
+ ht_oper->operation_mode =
+ cpu_to_le16(vht_oper->center_freq_seg1_idx <<
+ IEEE80211_HT_OP_MODE_CCFS2_SHIFT);
+
+ if (!ieee80211_chandef_vht_oper(&sdata->local->hw, vht_cap_info,
+ vht_oper, ht_oper, chandef))
+ chandef->chan = NULL;
+
+ kfree(ht_oper);
+ kfree(vht_oper);
+
+ return 0;
+}
+
+static inline int
+validate_chandef_by_6ghz_he_eht_oper(struct ieee80211_sub_if_data *sdata,
+ ieee80211_conn_flags_t conn_flags,
+ struct cfg80211_chan_def *chandef)
+{
+ u32 size, control_freq, center_freq1, center_freq2;
+ enum nl80211_chan_width chan_width;
+ struct ieee80211_he_operation *he_oper = NULL;
+ struct ieee80211_he_6ghz_oper *he_6ghz_oper;
+ struct ieee80211_eht_operation *eht_oper = NULL;
+ struct ieee80211_eht_operation_info *eht_oper_info;
+
+ if (conn_flags & (IEEE80211_CONN_DISABLE_HE)) {
+ chandef->chan = NULL;
+ return 0;
+ }
+
+ control_freq = chandef->chan->center_freq;
+ center_freq1 = chandef->center_freq1;
+ center_freq2 = chandef->center_freq2;
+ chan_width = chandef->width;
+
+ size = sizeof(struct ieee80211_he_operation) +
+ sizeof(struct ieee80211_he_6ghz_oper);
+
+ he_oper = kzalloc(size, GFP_KERNEL);
+ if (!he_oper)
+ return -ENOMEM;
+
+ if (!(conn_flags & IEEE80211_CONN_DISABLE_EHT)) {
+ size = sizeof(struct ieee80211_eht_operation) +
+ sizeof(struct ieee80211_eht_operation_info);
+
+ eht_oper = kzalloc(size, GFP_KERNEL);
+ if (!eht_oper) {
+ kfree(he_oper);
+ return -ENOMEM;
+ }
+ }
+
+ he_oper->he_oper_params = cpu_to_le32(u32_encode_bits(1,
+ IEEE80211_HE_OPERATION_6GHZ_OP_INFO));
+
+ he_6ghz_oper = (struct ieee80211_he_6ghz_oper *)he_oper->optional;
+ he_6ghz_oper->primary =
+ ieee80211_frequency_to_channel(control_freq);
+ he_6ghz_oper->ccfs0 = ieee80211_frequency_to_channel(center_freq1);
+ he_6ghz_oper->ccfs1 = center_freq2 ?
+ ieee80211_frequency_to_channel(center_freq2) : 0;
+
+ switch (chan_width) {
+ case NL80211_CHAN_WIDTH_320:
+ he_6ghz_oper->ccfs1 = he_6ghz_oper->ccfs0;
+ he_6ghz_oper->ccfs0 += control_freq < center_freq1 ? -16 : 16;
+ he_6ghz_oper->control = IEEE80211_EHT_OPER_CHAN_WIDTH_320MHZ;
+ break;
+ case NL80211_CHAN_WIDTH_160:
+ he_6ghz_oper->ccfs1 = he_6ghz_oper->ccfs0;
+ he_6ghz_oper->ccfs0 += control_freq < center_freq1 ? -8 : 8;
+ fallthrough;
+ case NL80211_CHAN_WIDTH_80P80:
+ he_6ghz_oper->control =
+ IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH_160MHZ;
+ break;
+ case NL80211_CHAN_WIDTH_80:
+ he_6ghz_oper->control =
+ IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH_80MHZ;
+ break;
+ case NL80211_CHAN_WIDTH_40:
+ he_6ghz_oper->control =
+ IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH_40MHZ;
+ break;
+ default:
+ he_6ghz_oper->control =
+ IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH_20MHZ;
+ break;
+ }
+
+ if (eht_oper) {
+ eht_oper->params = IEEE80211_EHT_OPER_INFO_PRESENT;
+
+ eht_oper_info =
+ (struct ieee80211_eht_operation_info *)eht_oper->optional;
+ eht_oper_info->control = he_6ghz_oper->control;
+ eht_oper_info->ccfs0 = he_6ghz_oper->ccfs0;
+ eht_oper_info->ccfs1 = he_6ghz_oper->ccfs1;
+ }
+
+ if (!ieee80211_chandef_he_6ghz_oper(sdata, he_oper, eht_oper, chandef))
+ chandef->chan = NULL;
+
+ kfree(he_oper);
+ kfree(eht_oper);
+
+ return 0;
+}
+
int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata,
struct ieee802_11_elems *elems,
enum nl80211_band current_band,
@@ -27,13 +257,14 @@ int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata,
struct ieee80211_csa_ie *csa_ie)
{
enum nl80211_band new_band = current_band;
- int new_freq;
- u8 new_chan_no;
+ int new_freq, ret;
+ u8 new_chan_no = 0, new_op_class = 0;
struct ieee80211_channel *new_chan;
- struct cfg80211_chan_def new_vht_chandef = {};
+ struct cfg80211_chan_def new_chandef = {};
const struct ieee80211_sec_chan_offs_ie *sec_chan_offs;
const struct ieee80211_wide_bw_chansw_ie *wide_bw_chansw_ie;
const struct ieee80211_bandwidth_indication *bwi;
+ const struct ieee80211_ext_chansw_ie *ext_chansw_ie;
int secondary_channel_offset = -1;
memset(csa_ie, 0, sizeof(*csa_ie));
@@ -41,6 +272,7 @@ int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata,
sec_chan_offs = elems->sec_chan_offs;
wide_bw_chansw_ie = elems->wide_bw_chansw_ie;
bwi = elems->bandwidth_indication;
+ ext_chansw_ie = elems->ext_chansw_ie;
if (conn_flags & (IEEE80211_CONN_DISABLE_HT |
IEEE80211_CONN_DISABLE_40MHZ)) {
@@ -51,26 +283,30 @@ int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata,
if (conn_flags & IEEE80211_CONN_DISABLE_VHT)
wide_bw_chansw_ie = NULL;
- if (elems->ext_chansw_ie) {
- if (!ieee80211_operating_class_to_band(
- elems->ext_chansw_ie->new_operating_class,
- &new_band)) {
- sdata_info(sdata,
- "cannot understand ECSA IE operating class, %d, ignoring\n",
- elems->ext_chansw_ie->new_operating_class);
+ if (ext_chansw_ie) {
+ new_op_class = ext_chansw_ie->new_operating_class;
+ if (!ieee80211_operating_class_to_band(new_op_class, &new_band)) {
+ new_op_class = 0;
+ sdata_info(sdata, "cannot understand ECSA IE "
+ "operating class, %d, ignoring\n",
+ ext_chansw_ie->new_operating_class);
+ } else {
+ new_chan_no = ext_chansw_ie->new_ch_num;
+ csa_ie->count = ext_chansw_ie->count;
+ csa_ie->mode = ext_chansw_ie->mode;
}
- new_chan_no = elems->ext_chansw_ie->new_ch_num;
- csa_ie->count = elems->ext_chansw_ie->count;
- csa_ie->mode = elems->ext_chansw_ie->mode;
- } else if (elems->ch_switch_ie) {
+ }
+
+ if (!new_op_class && elems->ch_switch_ie) {
new_chan_no = elems->ch_switch_ie->new_ch_num;
csa_ie->count = elems->ch_switch_ie->count;
csa_ie->mode = elems->ch_switch_ie->mode;
- } else {
- /* nothing here we understand */
- return 1;
}
+ /* nothing here we understand */
+ if (!new_chan_no)
+ return 1;
+
/* Mesh Channel Switch Parameters Element */
if (elems->mesh_chansw_params_ie) {
csa_ie->ttl = elems->mesh_chansw_params_ie->mesh_ttl;
@@ -134,65 +370,68 @@ int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata,
break;
}
+ /* parse one of the Elements to build a new chandef */
+ memset(&new_chandef, 0, sizeof(new_chandef));
+ new_chandef.chan = new_chan;
if (bwi) {
/* start with the CSA one */
- new_vht_chandef = csa_ie->chandef;
+ new_chandef = csa_ie->chandef;
/* and update the width accordingly */
/* FIXME: support 160/320 */
ieee80211_chandef_eht_oper(&bwi->info, true, true,
- &new_vht_chandef);
- } else if (wide_bw_chansw_ie) {
- u8 new_seg1 = wide_bw_chansw_ie->new_center_freq_seg1;
- struct ieee80211_vht_operation vht_oper = {
- .chan_width =
- wide_bw_chansw_ie->new_channel_width,
- .center_freq_seg0_idx =
- wide_bw_chansw_ie->new_center_freq_seg0,
- .center_freq_seg1_idx = new_seg1,
- /* .basic_mcs_set doesn't matter */
- };
- struct ieee80211_ht_operation ht_oper = {
- .operation_mode =
- cpu_to_le16(new_seg1 <<
- IEEE80211_HT_OP_MODE_CCFS2_SHIFT),
- };
-
- /* default, for the case of IEEE80211_VHT_CHANWIDTH_USE_HT,
- * to the previously parsed chandef
- */
- new_vht_chandef = csa_ie->chandef;
+ &new_chandef);
+ } else if (!ieee80211_operating_class_to_chandef(new_op_class, new_chan,
+ &new_chandef)) {
+ if (wide_bw_chansw_ie)
+ wbcs_ie_to_chandef(wide_bw_chansw_ie, &new_chandef);
+ else
+ new_chandef = csa_ie->chandef;
+ }
+
+ if (!cfg80211_chandef_valid(&new_chandef))
+ new_chandef = csa_ie->chandef;
- /* ignore if parsing fails */
- if (!ieee80211_chandef_vht_oper(&sdata->local->hw,
- vht_cap_info,
- &vht_oper, &ht_oper,
- &new_vht_chandef))
- new_vht_chandef.chan = NULL;
+ /* check if the new chandef fits the capabilities */
+ if (new_band == NL80211_BAND_6GHZ) {
+ ret = validate_chandef_by_6ghz_he_eht_oper(sdata, conn_flags,
+ &new_chandef);
+ if (ret)
+ return ret;
+ } else {
+ ret = validate_chandef_by_ht_vht_oper(sdata, conn_flags,
+ vht_cap_info, &new_chandef);
+ if (ret)
+ return ret;
+ }
+
+ /* if data is there validate the bandwidth & use it */
+ if (new_chandef.chan) {
+ if (conn_flags & IEEE80211_CONN_DISABLE_320MHZ &&
+ new_chandef.width == NL80211_CHAN_WIDTH_320)
+ ieee80211_chandef_downgrade(&new_chandef);
if (conn_flags & IEEE80211_CONN_DISABLE_80P80MHZ &&
- new_vht_chandef.width == NL80211_CHAN_WIDTH_80P80)
- ieee80211_chandef_downgrade(&new_vht_chandef);
+ new_chandef.width == NL80211_CHAN_WIDTH_80P80)
+ ieee80211_chandef_downgrade(&new_chandef);
+
if (conn_flags & IEEE80211_CONN_DISABLE_160MHZ &&
- new_vht_chandef.width == NL80211_CHAN_WIDTH_160)
- ieee80211_chandef_downgrade(&new_vht_chandef);
- }
+ new_chandef.width == NL80211_CHAN_WIDTH_160)
+ ieee80211_chandef_downgrade(&new_chandef);
- /* if VHT data is there validate & use it */
- if (new_vht_chandef.chan) {
- if (!cfg80211_chandef_compatible(&new_vht_chandef,
+ if (!cfg80211_chandef_compatible(&new_chandef,
&csa_ie->chandef)) {
sdata_info(sdata,
"BSS %pM: CSA has inconsistent channel data, disconnecting\n",
bssid);
return -EINVAL;
}
- csa_ie->chandef = new_vht_chandef;
+ csa_ie->chandef = new_chandef;
}
if (elems->max_channel_switch_time)
csa_ie->max_switch_time =
(elems->max_channel_switch_time[0] << 0) |
- (elems->max_channel_switch_time[1] << 8) |
+ (elems->max_channel_switch_time[1] << 8) |
(elems->max_channel_switch_time[2] << 16);
return 0;
--
2.25.1
^ permalink raw reply related
* [PATCH v2 0/3] Fix GDB commands error
From: Kuan-Ying Lee @ 2023-11-29 6:51 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno
Cc: casper.li, chinwen.chang, qun-wei.lin, linux-mm, akpm,
Kuan-Ying Lee, linux-kernel, linux-arm-kernel, linux-mediatek
This patchset fix some issues of gdb command.
Patch 1:
- Fix lx-ps command error
Patch 2:
- Fix stackdepot usage error
Patch 3:
- Remove exception handling
- Refine the printing format
---
V1->V2:
- Remove unnecessary variable. (Thanks Oleg)
- Refine commit message.
Kuan-Ying Lee (3):
scripts/gdb/tasks: Fix lx-ps command error
scripts/gdb/stackdepot: Rename pool_index to pools_num
scripts/gdb: Remove exception handling and refine print format
scripts/gdb/linux/page_owner.py | 58 ++++++++++++++-------------------
scripts/gdb/linux/slab.py | 3 +-
scripts/gdb/linux/stackdepot.py | 6 ++--
scripts/gdb/linux/tasks.py | 18 ++++------
4 files changed, 36 insertions(+), 49 deletions(-)
--
2.18.0
^ permalink raw reply
* [PATCH v2 2/3] scripts/gdb/stackdepot: Rename pool_index to pools_num
From: Kuan-Ying Lee @ 2023-11-29 6:51 UTC (permalink / raw)
To: Jan Kiszka, Kieran Bingham, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: casper.li, chinwen.chang, qun-wei.lin, linux-mm, akpm,
Kuan-Ying Lee, Andrey Konovalov, linux-kernel, linux-arm-kernel,
linux-mediatek
In-Reply-To: <20231129065142.13375-1-Kuan-Ying.Lee@mediatek.com>
After stackdepot evicting support patchset[1], we rename
pool_index to pools_num.
To avoid from the below issue, we rename consistently in
gdb scripts.
Python Exception <class 'gdb.error'>: No symbol "pool_index" in current
context.
Error occurred in Python: No symbol "pool_index" in current context.
[1] https://lore.kernel.org/linux-mm/cover.1700502145.git.andreyknvl@google.com/
Cc: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Kuan-Ying Lee <Kuan-Ying.Lee@mediatek.com>
---
scripts/gdb/linux/stackdepot.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/scripts/gdb/linux/stackdepot.py b/scripts/gdb/linux/stackdepot.py
index 047d329a6a12..0281d9de4b7c 100644
--- a/scripts/gdb/linux/stackdepot.py
+++ b/scripts/gdb/linux/stackdepot.py
@@ -25,10 +25,10 @@ def stack_depot_fetch(handle):
handle_parts_t = gdb.lookup_type("union handle_parts")
parts = handle.cast(handle_parts_t)
offset = parts['offset'] << DEPOT_STACK_ALIGN
- pool_index_cached = gdb.parse_and_eval('pool_index')
+ pools_num = gdb.parse_and_eval('pools_num')
- if parts['pool_index'] > pool_index_cached:
- gdb.write("pool index %d out of bounds (%d) for stack id 0x%08x\n" % (parts['pool_index'], pool_index_cached, handle))
+ if parts['pool_index'] > pools_num:
+ gdb.write("pool index %d out of bounds (%d) for stack id 0x%08x\n" % (parts['pool_index'], pools_num, handle))
return gdb.Value(0), 0
stack_pools = gdb.parse_and_eval('stack_pools')
--
2.18.0
^ permalink raw reply related
* [PATCH v2 1/3] scripts/gdb/tasks: Fix lx-ps command error
From: Kuan-Ying Lee @ 2023-11-29 6:51 UTC (permalink / raw)
To: Jan Kiszka, Kieran Bingham, Matthias Brugger,
AngeloGioacchino Del Regno, Andrew Morton, Oleg Nesterov
Cc: casper.li, chinwen.chang, qun-wei.lin, linux-mm, Kuan-Ying Lee,
stable, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20231129065142.13375-1-Kuan-Ying.Lee@mediatek.com>
Since commit 8e1f385104ac ("kill task_struct->thread_group") remove
the thread_group, we will encounter below issue.
(gdb) lx-ps
TASK PID COMM
0xffff800086503340 0 swapper/0
Python Exception <class 'gdb.error'>: There is no member named thread_group.
Error occurred in Python: There is no member named thread_group.
We use signal->thread_head to iterate all threads instead.
Fixes: 8e1f385104ac ("kill task_struct->thread_group")
Cc: stable@vger.kernel.org
Signed-off-by: Kuan-Ying Lee <Kuan-Ying.Lee@mediatek.com>
---
scripts/gdb/linux/tasks.py | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/scripts/gdb/linux/tasks.py b/scripts/gdb/linux/tasks.py
index 17ec19e9b5bf..aa5ab6251f76 100644
--- a/scripts/gdb/linux/tasks.py
+++ b/scripts/gdb/linux/tasks.py
@@ -13,7 +13,7 @@
import gdb
-from linux import utils
+from linux import utils, lists
task_type = utils.CachedType("struct task_struct")
@@ -22,19 +22,15 @@ task_type = utils.CachedType("struct task_struct")
def task_lists():
task_ptr_type = task_type.get_type().pointer()
init_task = gdb.parse_and_eval("init_task").address
- t = g = init_task
+ t = init_task
while True:
- while True:
- yield t
+ thread_head = t['signal']['thread_head']
+ for thread in lists.list_for_each_entry(thread_head, task_ptr_type, 'thread_node'):
+ yield thread
- t = utils.container_of(t['thread_group']['next'],
- task_ptr_type, "thread_group")
- if t == g:
- break
-
- t = g = utils.container_of(g['tasks']['next'],
- task_ptr_type, "tasks")
+ t = utils.container_of(t['tasks']['next'],
+ task_ptr_type, "tasks")
if t == init_task:
return
--
2.18.0
^ permalink raw reply related
* [PATCH v2 3/3] scripts/gdb: Remove exception handling and refine print format
From: Kuan-Ying Lee @ 2023-11-29 6:51 UTC (permalink / raw)
To: Jan Kiszka, Kieran Bingham, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: casper.li, chinwen.chang, qun-wei.lin, linux-mm, akpm,
Kuan-Ying Lee, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20231129065142.13375-1-Kuan-Ying.Lee@mediatek.com>
1. When we crash on a page, we want to check what
happened on this page instead of skipping this page by
try-catch block. Thus, removing the try-catch block.
2. Remove redundant comma and print the task name properly.
Signed-off-by: Kuan-Ying Lee <Kuan-Ying.Lee@mediatek.com>
---
scripts/gdb/linux/page_owner.py | 58 ++++++++++++++-------------------
scripts/gdb/linux/slab.py | 3 +-
2 files changed, 26 insertions(+), 35 deletions(-)
diff --git a/scripts/gdb/linux/page_owner.py b/scripts/gdb/linux/page_owner.py
index 844fd5d0c912..8e713a09cfe7 100644
--- a/scripts/gdb/linux/page_owner.py
+++ b/scripts/gdb/linux/page_owner.py
@@ -122,27 +122,24 @@ class DumpPageOwner(gdb.Command):
if not (page_ext['flags'] & (1 << PAGE_EXT_OWNER_ALLOCATED)):
gdb.write("page_owner is not allocated\n")
- try:
- page_owner = self.get_page_owner(page_ext)
- gdb.write("Page last allocated via order %d, gfp_mask: 0x%x, pid: %d, tgid: %d (%s), ts %u ns, free_ts %u ns\n" %\
- (page_owner["order"], page_owner["gfp_mask"],\
- page_owner["pid"], page_owner["tgid"], page_owner["comm"],\
- page_owner["ts_nsec"], page_owner["free_ts_nsec"]))
- gdb.write("PFN: %d, Flags: 0x%x\n" % (pfn, page['flags']))
- if page_owner["handle"] == 0:
- gdb.write('page_owner allocation stack trace missing\n')
- else:
- stackdepot.stack_depot_print(page_owner["handle"])
+ page_owner = self.get_page_owner(page_ext)
+ gdb.write("Page last allocated via order %d, gfp_mask: 0x%x, pid: %d, tgid: %d (%s), ts %u ns, free_ts %u ns\n" %\
+ (page_owner["order"], page_owner["gfp_mask"],\
+ page_owner["pid"], page_owner["tgid"], page_owner["comm"].string(),\
+ page_owner["ts_nsec"], page_owner["free_ts_nsec"]))
+ gdb.write("PFN: %d, Flags: 0x%x\n" % (pfn, page['flags']))
+ if page_owner["handle"] == 0:
+ gdb.write('page_owner allocation stack trace missing\n')
+ else:
+ stackdepot.stack_depot_print(page_owner["handle"])
- if page_owner["free_handle"] == 0:
- gdb.write('page_owner free stack trace missing\n')
- else:
- gdb.write('page last free stack trace:\n')
- stackdepot.stack_depot_print(page_owner["free_handle"])
- if page_owner['last_migrate_reason'] != -1:
- gdb.write('page has been migrated, last migrate reason: %s\n' % self.migrate_reason_names[page_owner['last_migrate_reason']])
- except:
- gdb.write("\n")
+ if page_owner["free_handle"] == 0:
+ gdb.write('page_owner free stack trace missing\n')
+ else:
+ gdb.write('page last free stack trace:\n')
+ stackdepot.stack_depot_print(page_owner["free_handle"])
+ if page_owner['last_migrate_reason'] != -1:
+ gdb.write('page has been migrated, last migrate reason: %s\n' % self.migrate_reason_names[page_owner['last_migrate_reason']])
def read_page_owner(self):
pfn = self.min_pfn
@@ -173,18 +170,13 @@ class DumpPageOwner(gdb.Command):
pfn += 1
continue
- try:
- page_owner = self.get_page_owner(page_ext)
- gdb.write("Page allocated via order %d, gfp_mask: 0x%x, pid: %d, tgid: %d (%s), ts %u ns, free_ts %u ns\n" %\
- (page_owner["order"], page_owner["gfp_mask"],\
- page_owner["pid"], page_owner["tgid"], page_owner["comm"],\
- page_owner["ts_nsec"], page_owner["free_ts_nsec"]))
- gdb.write("PFN: %d, Flags: 0x%x\n" % (pfn, page['flags']))
- stackdepot.stack_depot_print(page_owner["handle"])
- pfn += (1 << page_owner["order"])
- continue
- except:
- gdb.write("\n")
- pfn += 1
+ page_owner = self.get_page_owner(page_ext)
+ gdb.write("Page allocated via order %d, gfp_mask: 0x%x, pid: %d, tgid: %d (%s), ts %u ns, free_ts %u ns\n" %\
+ (page_owner["order"], page_owner["gfp_mask"],\
+ page_owner["pid"], page_owner["tgid"], page_owner["comm"].string(),\
+ page_owner["ts_nsec"], page_owner["free_ts_nsec"]))
+ gdb.write("PFN: %d, Flags: 0x%x\n" % (pfn, page['flags']))
+ stackdepot.stack_depot_print(page_owner["handle"])
+ pfn += (1 << page_owner["order"])
DumpPageOwner()
diff --git a/scripts/gdb/linux/slab.py b/scripts/gdb/linux/slab.py
index f012ba38c7d9..0e2d93867fe2 100644
--- a/scripts/gdb/linux/slab.py
+++ b/scripts/gdb/linux/slab.py
@@ -228,8 +228,7 @@ def slabtrace(alloc, cache_name):
nr_cpu = gdb.parse_and_eval('__num_online_cpus')['counter']
if nr_cpu > 1:
gdb.write(" cpus=")
- for i in loc['cpus']:
- gdb.write("%d," % i)
+ gdb.write(','.join(str(cpu) for cpu in loc['cpus']))
gdb.write("\n")
if constants.LX_CONFIG_STACKDEPOT:
if loc['handle']:
--
2.18.0
^ permalink raw reply related
* [PATCH v3,1/2] wifi: mac80211: add utility for converting op_class into chandef
From: Michael-CY Lee @ 2023-11-29 5:43 UTC (permalink / raw)
To: linux-wireless
Cc: Johannes Berg, Felix Fietkau, Lorenzo Bianconi, Evelyn Tsai,
Money Wang, linux-mediatek, Michael-CY Lee
This utility is used in STA CSA handling. The op_class in the ECSA
Element can be converted into chandef.
Signed-off-by: Michael-CY Lee <michael-cy.lee@mediatek.com>
Signed-off-by: Money Wang <money.wang@mediatek.com>
---
v3:
There were two utilities for op_class conversion in version 2.
This version combines them into one.
---
include/net/cfg80211.h | 13 ++++++++
net/wireless/util.c | 76 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 89 insertions(+)
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index b137a33a1b68..0ea1f1a53324 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -8669,6 +8669,19 @@ void cfg80211_ch_switch_started_notify(struct net_device *dev,
bool ieee80211_operating_class_to_band(u8 operating_class,
enum nl80211_band *band);
+/**
+ * ieee80211_operating_class_to_chandef - convert operating class to chandef
+ *
+ * @operating_class: the operating class to convert
+ * @chan: the ieee80211_channel to convert
+ * @chandef: a pointer to the resulting chandef
+ *
+ * Returns %true if the conversion was successful, %false otherwise.
+ */
+bool ieee80211_operating_class_to_chandef(u8 operating_class,
+ struct ieee80211_channel *chan,
+ struct cfg80211_chan_def *chandef);
+
/**
* ieee80211_chandef_to_operating_class - convert chandef to operation class
*
diff --git a/net/wireless/util.c b/net/wireless/util.c
index 626b858b4b35..edcc6f202c19 100644
--- a/net/wireless/util.c
+++ b/net/wireless/util.c
@@ -2017,6 +2017,82 @@ bool ieee80211_operating_class_to_band(u8 operating_class,
}
EXPORT_SYMBOL(ieee80211_operating_class_to_band);
+bool ieee80211_operating_class_to_chandef(u8 operating_class,
+ struct ieee80211_channel *chan,
+ struct cfg80211_chan_def *chandef)
+{
+ u32 control_freq, offset = 0;
+ enum nl80211_band band;
+
+ if (!ieee80211_operating_class_to_band(operating_class, &band) ||
+ !chan || band != chan->band)
+ return false;
+
+ control_freq = chan->center_freq;
+ chandef->chan = chan;
+
+ if (control_freq >= 5955)
+ offset = control_freq - 5955;
+ else if (control_freq >= 5745)
+ offset = control_freq - 5745;
+ else if (control_freq >= 5180)
+ offset = control_freq - 5180;
+ offset /= 20;
+
+ switch (operating_class) {
+ case 81: /* 2 GHz band; 20 MHz; channels 1..13 */
+ case 82: /* 2 GHz band; 20 MHz; channel 14 */
+ case 115: /* 5 GHz band; 20 MHz; channels 36,40,44,48 */
+ case 118: /* 5 GHz band; 20 MHz; channels 52,56,60,64 */
+ case 121: /* 5 GHz band; 20 MHz; channels 100..144 */
+ case 124: /* 5 GHz band; 20 MHz; channels 149,153,157,161 */
+ case 125: /* 5 GHz band; 20 MHz; channels 149..177 */
+ case 131: /* 6 GHz band; 20 MHz; channels 1..233*/
+ case 136: /* 6 GHz band; 20 MHz; channel 2 */
+ chandef->center_freq1 = control_freq;
+ chandef->width = NL80211_CHAN_WIDTH_20;
+ return true;
+ case 83: /* 2 GHz band; 40 MHz; channels 1..9 */
+ case 116: /* 5 GHz band; 40 MHz; channels 36,44 */
+ case 119: /* 5 GHz band; 40 MHz; channels 52,60 */
+ case 122: /* 5 GHz band; 40 MHz; channels 100,108,116,124,132,140 */
+ case 126: /* 5 GHz band; 40 MHz; channels 149,157,165,173 */
+ chandef->center_freq1 = control_freq + 10;
+ chandef->width = NL80211_CHAN_WIDTH_40;
+ return true;
+ case 84: /* 2 GHz band; 40 MHz; channels 5..13 */
+ case 117: /* 5 GHz band; 40 MHz; channels 40,48 */
+ case 120: /* 5 GHz band; 40 MHz; channels 56,64 */
+ case 123: /* 5 GHz band; 40 MHz; channels 104,112,120,128,136,144 */
+ case 127: /* 5 GHz band; 40 MHz; channels 153,161,169,177 */
+ chandef->center_freq1 = control_freq - 10;
+ chandef->width = NL80211_CHAN_WIDTH_40;
+ return true;
+ case 132: /* 6 GHz band; 40 MHz; channels 1,5,..,229*/
+ chandef->center_freq1 = control_freq + 10 - (offset & 1) * 20;
+ chandef->width = NL80211_CHAN_WIDTH_40;
+ return true;
+ case 128: /* 5 GHz band; 80 MHz; channels 36..64,100..144,149..177 */
+ case 133: /* 6 GHz band; 80 MHz; channels 1,5,..,229 */
+ chandef->center_freq1 = control_freq + 30 - (offset & 3) * 20;
+ chandef->width = NL80211_CHAN_WIDTH_80;
+ return true;
+ case 129: /* 5 GHz band; 160 MHz; channels 36..64,100..144,149..177 */
+ case 134: /* 6 GHz band; 160 MHz; channels 1,5,..,229 */
+ chandef->center_freq1 = control_freq + 70 - (offset & 7) * 20;
+ chandef->width = NL80211_CHAN_WIDTH_160;
+ return true;
+ case 130: /* 5 GHz band; 80+80 MHz; channels 36..64,100..144,149..177 */
+ case 135: /* 6 GHz band; 80+80 MHz; channels 1,5,..,229 */
+ /* The center_freq2 of 80+80 MHz is unknown */
+ case 137: /* 6 GHz band; 320 MHz; channels 1,5,..,229 */
+ /* 320-1 or 320-2 channelization is unknown */
+ default:
+ return false;
+ }
+}
+EXPORT_SYMBOL(ieee80211_operating_class_to_chandef);
+
bool ieee80211_chandef_to_operating_class(struct cfg80211_chan_def *chandef,
u8 *op_class)
{
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v3] docs: dt-bindings: add DTS Coding Style document
From: Francesco Dolcini @ 2023-11-29 7:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Andrew Davis, Andrew Lunn,
Arnd Bergmann, Bjorn Andersson, Chen-Yu Tsai, Dmitry Baryshkov,
Geert Uytterhoeven, Heiko Stuebner, Jonathan Corbet,
Konrad Dybcio, Michal Simek, Neil Armstrong, Nishanth Menon,
Olof Johansson, Rafał Miłecki, linux-rockchip,
linux-samsung-soc, linux-amlogic, linux-arm-msm, workflows,
linux-doc
In-Reply-To: <20231125184422.12315-1-krzysztof.kozlowski@linaro.org>
On Sat, Nov 25, 2023 at 07:44:22PM +0100, Krzysztof Kozlowski wrote:
> Document preferred coding style for Devicetree sources (DTS and DTSI),
> to bring consistency among all (sub)architectures and ease in reviews.
Thank Krzysztof, we had most of this collected as BKM in some internal
documents and it's great to see the effort to consolidate this and add
it to the kernel documentation.
> ---
> +Following order of properties in device nodes is preferred:
> +
> +1. compatible
> +2. reg
> +3. ranges
> +4. Standard/common properties (defined by common bindings, e.g. without
> + vendor-prefixes)
> +5. Vendor-specific properties
> +6. status (if applicable)
> +7. Child nodes, where each node is preceded with a blank line
On point 4, do you have a more explicit way to define what is an actual
standard/common property? You mention the vendor-prefixes as an example,
is this just an example or this is the whole definition?
What would be the order for this for example (from an existing DTS file)?
reg_sdhc1_vmmc: regulator-sdhci1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1_pwr_en>;
enable-active-high;
gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <100000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SD";
startup-delay-us = <2000>;
};
I guess the point that is not obvious to me here is where do we want
pinctrl. I like it at position between 3 and 4, the rationale is that is
a very frequent property and this way it will be in a similar place for
every node.
Francesco
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