* Re: [PATCH net] net: airoha: Disable GDM2 forwarding before configuring GDM2 loopback
From: patchwork-bot+netdevbpf @ 2026-05-21 15:30 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, linux-arm-kernel,
linux-mediatek, netdev, madhur.agrawal
In-Reply-To: <20260520-airoha-disable-gdm2-fwd-v1-1-1eeea5dffc2f@kernel.org>
Hello:
This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Wed, 20 May 2026 15:12:02 +0200 you wrote:
> Hw design requires to disable GDM2 forwarding before configuring GDM2
> loopback in airoha_set_gdm2_loopback routine.
>
> Fixes: 9cd451d414f6e ("net: airoha: Add loopback support for GDM2")
> Tested-by: Madhur Agrawal <madhur.agrawal@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
>
> [...]
Here is the summary with links:
- [net] net: airoha: Disable GDM2 forwarding before configuring GDM2 loopback
https://git.kernel.org/netdev/net/c/985d4a55e64e
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v12 5/5] mfd: Add support for MediaTek SPMI PMICs and MT6363/73
From: Lee Jones @ 2026-05-21 14:13 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: linux-mediatek, robh, krzk+dt, conor+dt, matthias.bgg, lgirdwood,
broonie, devicetree, linux-kernel, linux-arm-kernel, kernel,
wenst, Nícolas F. R. A. Prado
In-Reply-To: <20260511101355.122478-6-angelogioacchino.delregno@collabora.com>
On Mon, 11 May 2026, AngeloGioacchino Del Regno wrote:
> This driver adds support for the MediaTek SPMI PMICs and their
> interrupt controller (which is present in 95% of the cases).
>
> Other than probing all of the sub-devices of a SPMI PMIC, this
> sets up a regmap from the relevant SPMI bus and initializes an
> interrupt controller with its irq domain and irqchip to handle
> chained interrupts, with the SPMI bus itself being its parent
> irq controller, and the PMIC being the outmost device.
>
> This driver hence holds all of the information about a specific
> PMIC's interrupts and will properly handle them, calling the
> ISR for any subdevice that requested an interrupt.
>
> As for the interrupt spec, this driver wants either three or
> two interrupt cells, but in the case 3 were given it ignores
> the first one: this is because of how this first revision of
> of the MediaTek SPMI 2.0 Controller works, which doesn't hold
> hold irq number information in its register, but delegates
> that to the SPMI device - it's possible that this will change
> in the future with a newer revision of the controller IP, and
> this is the main reason for that.
>
> To make use of this implementation, this driver also adds the
> required bits to support MediaTek MT6363 and MT6373 SPMI PMICs.
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/mfd/Kconfig | 16 +
> drivers/mfd/Makefile | 1 +
> drivers/mfd/mtk-spmi-pmic.c | 427 ++++++++++++++++++++++
> include/linux/mfd/mt63x3_spmi/registers.h | 34 ++
> 4 files changed, 478 insertions(+)
> create mode 100644 drivers/mfd/mtk-spmi-pmic.c
> create mode 100644 include/linux/mfd/mt63x3_spmi/registers.h
>
> diff --git "a/drivers/mfd/Kconfig" "b/drivers/mfd/Kconfig"
> index 7192c9d1d268..3e9acdf648b7 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1148,6 +1148,22 @@ config MFD_MT6397
> accessing the device; additional drivers must be enabled in order
> to use the functionality of the device.
>
> +config MFD_MTK_SPMI_PMIC
> + tristate "MediaTek SPMI PMICs"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on OF
> + depends on SPMI
> + select REGMAP_SPMI
> + help
> + Say yes here to enable support for MediaTek's SPMI PMICs.
> + These PMICs made their first appearance in board designs using the
> + MediaTek Dimensity 9400 series of SoCs.
> + Note that this will only be useful when paired with descriptions
> + of the independent functions as child nodes in the device tree.
> +
> + Say M here if you want to include support for the MediaTek SPMI
> + PMICs as a module. The module will be called "mtk-spmi-pmic".
> +
> config MFD_MENF21BMC
> tristate "MEN 14F021P00 Board Management Controller Support"
> depends on I2C
> diff --git "a/drivers/mfd/Makefile" "b/drivers/mfd/Makefile"
> index e75e8045c28a..e00d283450c6 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -190,6 +190,7 @@ obj-$(CONFIG_MFD_MT6360) += mt6360-core.o
> obj-$(CONFIG_MFD_MT6370) += mt6370.o
> mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o
> obj-$(CONFIG_MFD_MT6397) += mt6397.o
> +obj-$(CONFIG_MFD_MTK_SPMI_PMIC) += mtk-spmi-pmic.o
>
> obj-$(CONFIG_RZ_MTU3) += rz-mtu3.o
> obj-$(CONFIG_ABX500_CORE) += abx500-core.o
> diff --git "a/drivers/mfd/mtk-spmi-pmic.c" "b/drivers/mfd/mtk-spmi-pmic.c
> new file mode 100644
> index 000000000000..d1fc8156e696
> --- /dev/null
> +++ b/drivers/mfd/mtk-spmi-pmic.c
> @@ -0,0 +1,427 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * MediaTek SPMI PMICs Driver
> + *
> + * Copyright (c) 2024 MediaTek Inc.
> + * Copyright (c) 2025 Collabora Ltd
> + *
> + * Authors:
> + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/errno.h>
> +#include <linux/gfp.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/mt63x3_spmi/registers.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/regmap.h>
> +#include <linux/spmi.h>
> +#include <linux/types.h>
> +
> +#define MTK_SPMI_PMIC_VAL_BITS 8
> +#define MTK_SPMI_PMIC_REG_CHIP_ID 0xb
> +#define MTK_SPMI_PMIC_RCS_IRQ_DONE 0x41b
> +
> +/**
> + * struct mtk_spmi_pmic_irq_group - Group of interrupts in SPMI PMIC
> + * @num_int_regs: Number of registers for this group of interrupts
> + * @con_reg: PMIC Interrupt Group Control 0 register
> + * @sta_reg: PMIC Interrupt Group Status 0 register
> + * @group_num: PMIC Interrupt Group number - also corresponds to the
> + * status bit in the global IRQ Control register
> + */
> +struct mtk_spmi_pmic_irq_grp {
> + u8 hwirq_base;
> + u8 num_int_regs;
> + u16 con_reg;
> + u16 sta_reg;
> + u8 group_num;
> +};
> +
> +/**
> + * struct mtk_spmi_pmic_variant - SPMI PMIC variant-specific data
> + * @pmic_irq: Group of interrupts in SPMI PMIC
> + * @num_groups: Number of groups of interrupts
> + * @con_reg_len: Length in bytes of Control registers, depends on
> + * existence of SET and CLR registers in the layout
> + * @irq_grp_reg: Global interrupt status register, explains which
> + * group needs attention because of a group IRQ;
> + * if this is zero, it means that there is only one
> + * group and the device has no irqgroup register
> + * @chip_id_reg: Chip ID Register
> + */
> +struct mtk_spmi_pmic_variant {
> + const struct mtk_spmi_pmic_irq_grp *pmic_irq;
> + u8 num_groups;
> + u8 con_reg_len;
> + u8 irq_grp_reg;
> + u8 chip_id_reg;
> +};
Where is chip_id_reg used?
> +
> +/**
> + * struct mtk_spmi_pmic - Main driver structure
> + * @variant: SPMI PMIC variant-specific data
> + * @dev: Handle to SPMI Device
> + * @dom: IRQ Domain of the PMIC's interrupt controller
> + * @regmap: Handle to PMIC regmap
> + * @irq: PMIC chained interrupt
> + */
> +struct mtk_spmi_pmic {
> + const struct mtk_spmi_pmic_variant *variant;
> + struct device *dev;
> + struct irq_domain *dom;
> + struct regmap *regmap;
> + int irq;
> +};
> +
> +static void mtk_spmi_pmic_irq_set_unmasking(struct irq_data *d, bool unmask)
> +{
> + struct mtk_spmi_pmic *pmic = irq_data_get_irq_chip_data(d);
> + const struct mtk_spmi_pmic_variant *variant = pmic->variant;
> + struct regmap *regmap = pmic->regmap;
> + irq_hw_number_t hwirq = irqd_to_hwirq(d);
> + unsigned short i;
> +
> + for (i = 0; i < variant->num_groups; i++) {
for (ini i = 0; ...
Did I not bring this up last time?
> + const struct mtk_spmi_pmic_irq_grp *irq_grp = &variant->pmic_irq[i];
> + u32 con_reg;
> + u8 irq_en_bit;
> +
> + if (hwirq < irq_grp->hwirq_base)
> + continue;
> +
> + con_reg = irq_grp->con_reg + (variant->con_reg_len * i);
> + irq_en_bit = hwirq - irq_grp->hwirq_base;
> + regmap_assign_bits(regmap, con_reg, BIT(irq_en_bit), unmask);
> +
> + break;
> + }
> +}
> +
> +static void mtk_spmi_pmic_irq_mask(struct irq_data *d)
> +{
> + mtk_spmi_pmic_irq_set_unmasking(d, false);
> +}
> +
> +static void mtk_spmi_pmic_irq_unmask(struct irq_data *d)
> +{
> + mtk_spmi_pmic_irq_set_unmasking(d, true);
> +}
> +
> +static struct irq_chip mtk_spmi_pmic_irq_chip = {
> + .name = "mtk-spmi-pmic",
> + .irq_mask = mtk_spmi_pmic_irq_mask,
> + .irq_unmask = mtk_spmi_pmic_irq_unmask,
> + .flags = IRQCHIP_SKIP_SET_WAKE,
> +};
> +
> +static struct lock_class_key mtk_spmi_pmic_irq_lock_class, mtk_spmi_pmic_irq_request_class;
> +
> +static int mtk_spmi_pmic_irq_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
> + unsigned long *out_hwirq, unsigned int *out_type)
> +{
> + struct mtk_spmi_pmic *pmic = d->host_data;
> + u32 intsize = fwspec->param_count;
> + u32 *intspec = fwspec->param;
> + unsigned int irq_type_index;
> + unsigned int irq_num_index;
> +
> + /*
> + * Interrupt cell index - For interrupt size 3:
> + * [0] - SID Interrupt number
> + * [1] - SPMI PMIC (Sub-)Device Interrupt number
> + * [2] - Interrupt Type mask
> + *
> + * When only two cells are specified the SID Interrupt is not present.
> + */
> + if (intsize != 2 && intsize != 3) {
> + dev_err(pmic->dev, "Expected IRQ specifier of size 2 or 3, got %u\n", intsize);
> + return -EINVAL;
> + }
> +
> + /* irq_num_index refers to the SPMI (Sub-)Device Interrupt number */
> + irq_num_index = intsize - 2;
> + irq_type_index = irq_num_index + 1;
> +
> + /*
> + * For 3 cells, the IRQ number in intspec[0] is ignored on purpose here!
> + *
> + * This is because of how at least the first revision of the SPMI 2.0
> + * controller works in MediaTek SoCs: the controller will raise an
> + * interrupt for each SID (but doesn't know the details), and the
> + * specific IRQ number that got raised must be read from the PMIC or
> + * its sub-device driver.
> + * It's possible that this will change in the future with a newer
> + * revision of the SPMI controller, and this is why the device tree
> + * holds the full interrupt specifier.
> + *
> + * out_hwirq: SPMI PMIC (Sub-)Device Interrupt number
> + * out_type: Interrupt type sense mask
> + */
> + *out_hwirq = intspec[irq_num_index];
> + *out_type = intspec[irq_type_index] & IRQ_TYPE_SENSE_MASK;
> +
> + return 0;
> +}
> +
> +static int mtk_spmi_pmic_irq_alloc(struct irq_domain *d, unsigned int virq,
> + unsigned int nr_irqs, void *data)
> +{
> + struct mtk_spmi_pmic *pmic = d->host_data;
> + struct irq_fwspec *fwspec = data;
> + irq_hw_number_t hwirq;
> + unsigned int irqtype;
> + int i, ret;
> +
> + ret = mtk_spmi_pmic_irq_translate(d, fwspec, &hwirq, &irqtype);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < nr_irqs; i++) {
As above.
> + irq_set_lockdep_class(virq, &mtk_spmi_pmic_irq_lock_class,
> + &mtk_spmi_pmic_irq_request_class);
> + irq_domain_set_info(d, virq, hwirq, &mtk_spmi_pmic_irq_chip,
> + pmic, handle_level_irq, NULL, NULL);
> + }
> +
> + return 0;
> +}
> +
> +
> +static const struct irq_domain_ops mtk_spmi_pmic_irq_domain_ops = {
> + .alloc = mtk_spmi_pmic_irq_alloc,
> + .free = irq_domain_free_irqs_common,
> + .translate = mtk_spmi_pmic_irq_translate,
> +};
> +
> +static int mtk_spmi_pmic_handle_group_irq(struct mtk_spmi_pmic *pmic, int group)
> +{
> + const struct mtk_spmi_pmic_irq_grp *irq_grp = &pmic->variant->pmic_irq[group];
> + struct regmap *regmap = pmic->regmap;
> + struct device *dev = pmic->dev;
> + int i, ret;
Etc.
> +
> + for (i = 0; i < irq_grp->num_int_regs; i++) {
> + u32 status, saved_status;
> +
> + ret = regmap_read(regmap, irq_grp->sta_reg + i, &status);
> + if (ret) {
> + dev_err(dev, "Could not read IRQ status register: %d", ret);
> + return ret;
> + }
> +
> + if (status == 0)
> + continue;
> +
> + saved_status = status;
> + do {
> + irq_hw_number_t hwirq;
> + u8 bit = __ffs(status);
> +
> + /* Each register has 8 bits: this is the first IRQ of this group */
> + hwirq = MTK_SPMI_PMIC_VAL_BITS * i;
> +
> + /* Offset by this group's start interrupt */
> + hwirq += irq_grp->hwirq_base;
> +
> + /* Finally, offset by the fired IRQ's bit number */
> + hwirq += bit;
> +
> + status &= ~BIT(bit);
> +
> + generic_handle_domain_irq_safe(pmic->dom, hwirq);
> + } while (status);
> +
> + /* Clear the interrupts by writing the previous status */
> + regmap_write(regmap, irq_grp->sta_reg + i, saved_status);
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_spmi_pmic_handle_chained_irq(struct irq_desc *desc)
> +{
> + struct mtk_spmi_pmic *pmic = irq_desc_get_handler_data(desc);
> + const struct mtk_spmi_pmic_variant *variant = pmic->variant;
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + struct regmap *regmap = pmic->regmap;
> + bool irq_handled = false;
> + int i, ret;
> + u32 val;
> +
> + chained_irq_enter(chip, desc);
> +
> + /* If irq_grp_reg is present there are multiple IRQ groups */
> + if (variant->irq_grp_reg > 0) {
> + ret = regmap_read(regmap, variant->irq_grp_reg, &val);
> + if (ret)
> + handle_bad_irq(desc);
> +
> + /* This is very unlikely to happen */
> + if (val == 0) {
> + chained_irq_exit(chip, desc);
> + return;
> + }
> + } else {
> + val = BIT(0);
> + }
> +
> + for (i = 0; i < variant->num_groups; i++) {
> + const struct mtk_spmi_pmic_irq_grp *irq_grp = &variant->pmic_irq[i];
> + u8 group_bit = BIT(irq_grp[i].group_num);
Did you mean to index twice here?
irq_grp[i + i].group_num
> +
> + if (val & group_bit) {
> + ret = mtk_spmi_pmic_handle_group_irq(pmic, i);
> + if (ret == 0)
> + irq_handled = true;
> + }
> + }
> +
> + /* The RCS flag has to be cleared even if the IRQ was not handled. */
> + ret = regmap_write(regmap, MTK_SPMI_PMIC_RCS_IRQ_DONE, 1);
> + if (ret)
> + dev_warn(pmic->dev, "Could not clear RCS flag!\n");
> +
> + if (!irq_handled)
> + handle_bad_irq(desc);
> +
> + chained_irq_exit(chip, desc);
> +}
> +
> +static void mtk_spmi_pmic_irq_remove(void *data)
> +{
> + struct mtk_spmi_pmic *pmic = (struct mtk_spmi_pmic *)data;
You shouldn't need from a void.
> +
> + irq_set_chained_handler_and_data(pmic->irq, NULL, NULL);
> + irq_domain_remove(pmic->dom);
> +}
> +
> +static int mtk_spmi_pmic_irq_init(struct device *dev, struct regmap *regmap,
> + const struct mtk_spmi_pmic_variant *variant)
> +{
> + struct fwnode_handle *fwnode = of_fwnode_handle(dev->of_node);
> + struct mtk_spmi_pmic *pmic;
> + int ret;
> +
> + pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
> + if (!pmic)
> + return -ENOMEM;
> +
> + pmic->irq = of_irq_get(dev->of_node, 0);
> + if (pmic->irq < 0)
> + return dev_err_probe(dev, pmic->irq, "Cannot get IRQ\n");
> +
> + pmic->dev = dev;
> + pmic->regmap = regmap;
> + pmic->variant = variant;
> +
> + pmic->dom = irq_domain_create_tree(fwnode, &mtk_spmi_pmic_irq_domain_ops, pmic);
> + if (!pmic->dom)
> + return dev_err_probe(dev, -ENOMEM, "Cannot create IRQ domain\n");
> +
> + ret = devm_add_action_or_reset(dev, mtk_spmi_pmic_irq_remove, pmic);
> + if (ret) {
> + irq_domain_remove(pmic->dom);
You just double-freed.
> + return ret;
> + }
> +
> + irq_set_chained_handler_and_data(pmic->irq, mtk_spmi_pmic_handle_chained_irq, pmic);
> +
> + return 0;
> +}
> +
> +#define MTK_SPMI_PMIC_IRQ_GROUP(pmic, group_name, group_index, first_irq, last_irq) \
> +{ \
> + .hwirq_base = first_irq, \
> + .num_int_regs = ((last_irq - first_irq) / MTK_SPMI_PMIC_VAL_BITS) + 1, \
> + .con_reg = pmic##_REG_##group_name##_TOP_INT_CON0, \
> + .sta_reg = pmic##_REG_##group_name##_TOP_INT_STATUS0, \
> + .group_num = group_index, \
> +}
> +
> +static const struct mtk_spmi_pmic_irq_grp mt6363_irq_groups[] = {
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6363, BUCK, 0, 0, 9),
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6363, LDO, 1, 16, 40),
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6363, PSC, 2, 48, 57),
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6363, MISC, 3, 64, 79),
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6363, HK, 4, 80, 87),
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6363, BM, 6, 88, 107)
> +};
> +
> +static const struct mtk_spmi_pmic_irq_grp mt6373_irq_groups[] = {
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6373, BUCK, 0, 0, 9),
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6373, LDO, 1, 16, 39),
> + MTK_SPMI_PMIC_IRQ_GROUP(MT6373, MISC, 3, 56, 71),
> +};
> +
> +static const struct mtk_spmi_pmic_variant mt6363_variant = {
> + .pmic_irq = mt6363_irq_groups,
> + .num_groups = ARRAY_SIZE(mt6363_irq_groups),
> + .con_reg_len = 3,
> + .irq_grp_reg = MT6363_REG_TOP_INT_STATUS1,
> + .chip_id_reg = MTK_SPMI_PMIC_REG_CHIP_ID,
> +};
> +
> +static const struct mtk_spmi_pmic_variant mt6373_variant = {
> + .pmic_irq = mt6373_irq_groups,
> + .num_groups = ARRAY_SIZE(mt6373_irq_groups),
> + .con_reg_len = 3,
> + .irq_grp_reg = MT6373_REG_TOP_INT_STATUS1,
> + .chip_id_reg = MTK_SPMI_PMIC_REG_CHIP_ID,
> +};
> +
> +static const struct regmap_config mtk_spmi_regmap_config = {
> + .reg_bits = 16,
> + .val_bits = MTK_SPMI_PMIC_VAL_BITS,
> + .max_register = 0xffff,
> + .fast_io = true,
> +};
> +
> +static int mtk_spmi_pmic_probe(struct spmi_device *sdev)
> +{
> + const struct mtk_spmi_pmic_variant *variant;
> + struct device *dev = &sdev->dev;
> + struct regmap *regmap;
> + int ret;
> +
> + regmap = devm_regmap_init_spmi_ext(sdev, &mtk_spmi_regmap_config);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + variant = (const struct mtk_spmi_pmic_variant *)device_get_match_data(dev);
Again, no casting required.
> + if (variant && variant->num_groups) {
> + ret = mtk_spmi_pmic_irq_init(dev, regmap, variant);
> + if (ret)
> + return ret;
> + }
> +
> + return devm_of_platform_populate(dev);
> +}
> +
> +static const struct of_device_id mtk_pmic_spmi_id_table[] = {
> + { .compatible = "mediatek,mt6363", .data = &mt6363_variant },
> + { .compatible = "mediatek,mt6373", .data = &mt6373_variant },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mtk_pmic_spmi_id_table);
> +
> +static struct spmi_driver mtk_spmi_pmic_driver = {
> + .probe = mtk_spmi_pmic_probe,
> + .driver = {
> + .name = "mtk-spmi-pmic",
> + .of_match_table = mtk_pmic_spmi_id_table,
> + },
> +};
> +module_spmi_driver(mtk_spmi_pmic_driver);
> +
> +MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
> +MODULE_DESCRIPTION("MediaTek SPMI PMIC driver");
> +MODULE_LICENSE("GPL");
> diff --git "a/include/linux/mfd/mt63x3_spmi/registers.h" "b/include/linux/mfd/mt63x3_spmi/registers.h
> new file mode 100644
> index 000000000000..808927280b40
> --- /dev/null
> +++ "b/include/linux/mfd/mt63x3_spmi/registers.h"
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + * Copyright (c) 2025 Collabora Ltd
> + */
> +
> +#ifndef __MFD_MT63X3_SPMI_REGISTERS_H__
> +#define __MFD_MT63X3_SPMI_REGISTERS_H__
> +
> +/* MT6363 PMIC Registers */
> +#define MT6363_REG_MISC_TOP_INT_CON0 0x37
> +#define MT6363_REG_MISC_TOP_INT_STATUS0 0x43
> +#define MT6363_REG_TOP_INT_STATUS1 0x4e
> +#define MT6363_REG_PSC_TOP_INT_CON0 0x90f
> +#define MT6363_REG_PSC_TOP_INT_STATUS0 0x91b
> +#define MT6363_REG_BM_TOP_INT_CON0 0xc24
> +#define MT6363_REG_BM_TOP_INT_STATUS0 0xc36
> +#define MT6363_REG_HK_TOP_INT_CON0 0xf92
> +#define MT6363_REG_HK_TOP_INT_STATUS0 0xf9e
> +#define MT6363_REG_BUCK_TOP_INT_CON0 0x1411
> +#define MT6363_REG_BUCK_TOP_INT_STATUS0 0x141d
> +#define MT6363_REG_LDO_TOP_INT_CON0 0x1b11
> +#define MT6363_REG_LDO_TOP_INT_STATUS0 0x1b29
> +
> +/* MT6373 PMIC Registers */
> +#define MT6373_REG_MISC_TOP_INT_CON0 0x3c
> +#define MT6373_REG_MISC_TOP_INT_STATUS0 0x48
> +#define MT6373_REG_TOP_INT_STATUS1 0x53
> +#define MT6373_REG_BUCK_TOP_INT_CON0 0x1411
> +#define MT6373_REG_BUCK_TOP_INT_STATUS0 0x141d
> +#define MT6373_REG_LDO_TOP_INT_CON0 0x1b10
> +#define MT6373_REG_LDO_TOP_INT_STATUS0 0x1b22
> +
> +#endif /* __MFD_MT63X3_SPMI_REGISTERS_H__ */
> --
> 2.53.0
>
--
Lee Jones
^ permalink raw reply
* [GIT PULL] mediatek drm next - 20260521
From: Chun-Kuang Hu @ 2026-05-21 14:08 UTC (permalink / raw)
To: David Airlie, Simona Vetter, dri-devel, linux-mediatek, sai madhu,
Rosen Penev, Shivam Kalra, Abhishek Rajput, Luca Leonardo Scorcia
Hi, Dave & Sima:
This includes:
1. hdmi: Convert DRM_ERROR() to drm_err()
2. Simplify mtk_crtc allocation
3. mtk_dpi: Open-code drm_simple_encoder_init()
4. Convert legacy DRM logging to drm_* helpers in mtk_dsi.c
5. dsi: Add compatible for mt8167-dsi
Regards,
Chun-Kuang.
The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731:
Linux 7.1-rc1 (2026-04-26 14:19:00 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git tags/mediatek-drm-next-20260521
for you to fetch changes up to 6428eaf0c1f39815b08d57054895c1934d5782f3:
drm/mediatek: dsi: Add compatible for mt8167-dsi (2026-05-18 13:44:33 +0000)
----------------------------------------------------------------
Mediatek DRM Next - 20260521
1. hdmi: Convert DRM_ERROR() to drm_err()
2. Simplify mtk_crtc allocation
3. mtk_dpi: Open-code drm_simple_encoder_init()
4. Convert legacy DRM logging to drm_* helpers in mtk_dsi.c
5. dsi: Add compatible for mt8167-dsi
----------------------------------------------------------------
Abhishek Rajput (1):
drm/mediatek: Convert legacy DRM logging to drm_* helpers in mtk_dsi.c
Luca Leonardo Scorcia (1):
drm/mediatek: dsi: Add compatible for mt8167-dsi
Rosen Penev (1):
drm/mediatek: Simplify mtk_crtc allocation
Shivam Kalra (1):
drm/mediatek: mtk_dpi: Open-code drm_simple_encoder_init()
sai madhu (1):
drm/mediatek: hdmi: Convert DRM_ERROR() to drm_err()
drivers/gpu/drm/mediatek/mtk_crtc.c | 15 ++++++---------
drivers/gpu/drm/mediatek/mtk_dpi.c | 10 +++++++---
drivers/gpu/drm/mediatek/mtk_dsi.c | 28 ++++++++++++++++++----------
drivers/gpu/drm/mediatek/mtk_hdmi.c | 4 ++--
4 files changed, 33 insertions(+), 24 deletions(-)
^ permalink raw reply
* [GIT PULL] mediatek drm fixes - 20260521
From: Chun-Kuang Hu @ 2026-05-21 13:56 UTC (permalink / raw)
To: David Airlie, Simona Vetter, dri-devel, linux-mediatek,
Louis-Alexis Eyraud
Hi, Dave & Sima:
This includes:
1. fix sparse warnings
Regards,
Chun-Kuang.
The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731:
Linux 7.1-rc1 (2026-04-26 14:19:00 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git tags/mediatek-drm-fixes-20260521
for you to fetch changes up to 87ed4e845d5a90bba1a56c0a5c580a13982e8648:
drm/mediatek: mtk_hdmi_ddc: Fix non-static global variable (2026-05-18 14:21:39 +0000)
----------------------------------------------------------------
Mediatek DRM Fixes - 20260521
1. fix sparse warnings
----------------------------------------------------------------
Louis-Alexis Eyraud (4):
drm/mediatek: mtk_hdmi_ddc_v2: Fix non-static global variable
drm/mediatek: mtk_hdmi_v2: Fix non-static global variable
drm/mediatek: mtk_cec: Fix non-static global variable
drm/mediatek: mtk_hdmi_ddc: Fix non-static global variable
drivers/gpu/drm/mediatek/mtk_cec.c | 2 +-
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c | 2 +-
drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c | 2 +-
drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
^ permalink raw reply
* [bug report] wifi: mt76: mt7996: Add NPU offload support to MT7996 driver
From: Dan Carpenter @ 2026-05-21 12:51 UTC (permalink / raw)
To: Lorenzo Bianconi; +Cc: linux-mediatek
Hello Lorenzo Bianconi,
Commit 377aa17d2aed ("wifi: mt76: mt7996: Add NPU offload support to
MT7996 driver") from Oct 17, 2025, leads to the following Smatch
complaint:
drivers/net/wireless/mediatek/mt76/mt7996/pci.c:144 mt7996_pci_probe()
warn: variable dereferenced before check 'pdev->bus' (see line 126)
drivers/net/wireless/mediatek/mt76/mt7996/pci.c
125
126 mt76_pci_disable_aspm(pdev);
^^^^
This dereferences pdev->bus so...
127
128 if (id->device == MT7996_DEVICE_ID_2 ||
129 id->device == MT7992_DEVICE_ID_2 ||
130 id->device == MT7990_DEVICE_ID_2)
131 return mt7996_pci_hif2_probe(pdev);
132
133 dev = mt7996_mmio_probe(&pdev->dev, pcim_iomap_table(pdev)[0],
134 id->device);
135 if (IS_ERR(dev))
136 return PTR_ERR(dev);
137
138 mdev = &dev->mt76;
139 mt7996_wfsys_reset(dev);
140 hif2 = mt7996_pci_init_hif2(pdev);
141 dev->hif2 = hif2;
142
143 mt76_npu_init(mdev, pci_resource_start(pdev, 0),
144 pdev->bus && pci_domain_nr(pdev->bus) ? 3 : 2);
^^^^^^^^^
so hopefully this check can be removed?
(Proably this warning is showing up seven months later because I
deleted my cross function database. Probably Smatch wasn't
complaining before because it knew that ->bus couldn't actually be
NULL?)
145
146 ret = mt7996_mmio_wed_init(dev, pdev, false, &irq);
This email is a free service from the Smatch-CI project [smatch.sf.net].
regards,
dan carpenter
^ permalink raw reply
* Re: [PATCH v5 4/6] dt-bindings: display: mediatek: tdshp: Add support for MT8196
From: Jay Liu (刘博) @ 2026-05-21 11:40 UTC (permalink / raw)
To: chunkuang.hu@kernel.org, tzimmermann@suse.de, simona@ffwll.ch,
mripard@kernel.org, p.zabel@pengutronix.de,
CK Hu (胡俊光),
maarten.lankhorst@linux.intel.com, conor+dt@kernel.org,
robh@kernel.org, airlied@gmail.com, matthias.bgg@gmail.com,
krzk+dt@kernel.org, AngeloGioacchino Del Regno
Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
In-Reply-To: <c9ed6676f1ae77e21b2ba2daf75a76f3a9a13389.camel@mediatek.com>
On Wed, 2026-05-13 at 08:03 +0000, CK Hu (胡俊光) wrote:
> On Mon, 2026-04-27 at 19:20 +0800, Jay Liu wrote:
> > Add tdshp hardware description for MediaTek MT8196 SoC
> >
> > Signed-off-by: Jay Liu <jay.liu@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,tdshp.yaml | 46
> > +++++++++++++++++++
> > 1 file changed, 46 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.y
> > aml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp
> > .yaml
> > new file mode 100644
> > index 000000000000..50b24cc22420
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp
> > .yaml
> > @@ -0,0 +1,46 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,tdshp.yaml*__;Iw!!CTRNKA9wMg0ARbw!jvLiL6w7ScJqhkM0IyiLok4cwzb-e1gME-mO9r5lLT3JTrgaBBiiV1j8LFkmJkIafaGiBya2GJN6h38e$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jvLiL6w7ScJqhkM0IyiLok4cwzb-e1gME-mO9r5lLT3JTrgaBBiiV1j8LFkmJkIafaGiBya2GCPflrFz$
> >
> > +
> > +title: MediaTek display 2D sharpness processor
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > + - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > + MediaTek display 2D sharpness processor, namely TDSHP, provides
> > a
>
> a -> an
>
> > + operation used to adjust sharpness in display system.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt8196-disp-tdshp
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
>
> Refer to other display block binding document, and find out the
> common property.
> Such as power-domains, gce-client-reg, ports.
>
> Regards,
> CK
>
Thank you for your review and helpful suggestions.
I will review other display block binding documents and identify the
common properties, such as power-domains, gce-client-reg, and ports.
If I have further questions or need clarification, I will reach out.
Thanks again for your guidance.
Best regards,
Jay
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + tdshp@321e0000 {
> > + compatible = "mediatek,mt8196-disp-tdshp";
> > + reg = <0 0x321e0000 0 0x1000>;
> > + clocks = <&dispsys_config_clk 107>;
> > + };
> > + };
>
>
^ permalink raw reply
* Re: [PATCH net-next v4 1/6] dt-bindings: net: Add support for Airoha AN8801R GbE PHY
From: Rob Herring (Arm) @ 2026-05-21 10:15 UTC (permalink / raw)
To: Louis-Alexis Eyraud
Cc: linux-arm-kernel, Andrew Lunn, linux-mediatek, Russell King,
kevin-kw.huang, matthias.bgg, Andrew Lunn, Jakub Kicinski,
David S. Miller, devicetree, Krzysztof Kozlowski, Heiner Kallweit,
netdev, linux-kernel, AngeloGioacchino Del Regno, Paolo Abeni,
Conor Dooley, kernel, Eric Dumazet, macpaul.lin
In-Reply-To: <20260521-add-airoha-an8801-support-v4-1-1e4837d30ef4@collabora.com>
On Thu, 21 May 2026 10:21:54 +0200, Louis-Alexis Eyraud wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Add a new binding to support the Airoha AN8801R Series Gigabit
> Ethernet PHY.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
> ---
> .../devicetree/bindings/net/airoha,an8801.yaml | 116 +++++++++++++++++++++
> 1 file changed, 116 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/net/airoha,an8801.yaml: ^led@[0-2]$: Missing additionalProperties/unevaluatedProperties constraint
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260521-add-airoha-an8801-support-v4-1-1e4837d30ef4@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* [PATCH net-next v4 6/6] net: phy: air_an8801: ensure maximum available speed link use
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
To ensure that the Airoha AN8801R PHY uses the maximum available link
speed, an additional register write is needed to configure the function
mode for either 1G or 100M/10M operation after link detection.
So, in air_an8801 driver, implement a custom read_status callback, that
after genphy_read_status determines the link speed, sets the bit 0 of
the link mode register (REG_LINK_MODE) if the detected speed is 1Gbps,
or unsets it otherwise.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_an8801.c | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
index 73f94e84da07..c64fa153b738 100644
--- a/drivers/net/phy/air_an8801.c
+++ b/drivers/net/phy/air_an8801.c
@@ -977,6 +977,48 @@ static int an8801r_config_init(struct phy_device *phydev)
return 0;
}
+static int an8801r_read_status(struct phy_device *phydev)
+{
+ int prev_speed, ret;
+ u32 val;
+
+ prev_speed = phydev->speed;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (!phydev->link) {
+ phydev->speed = SPEED_UNKNOWN;
+ return 0;
+ }
+
+ if (prev_speed != phydev->speed) {
+ /* Ensure that PHY switches to 1G speed when available,
+ * by configuring the function mode for either 1G or 100M/10M
+ * operation.
+ * Therefore, set the link mode register, after read_status
+ * determines the link speed.
+ */
+ val = phydev->speed == SPEED_1000 ?
+ AN8801_BPBUS_LINK_MODE_1000 : 0;
+
+ ret = an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LINK_MODE,
+ AN8801_BPBUS_LINK_MODE_1000,
+ val);
+ if (ret) {
+ /* Restore previous speed on failure to ensure this
+ * register setting is retried on the next poll
+ */
+ phydev->speed = prev_speed;
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int an8801r_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -1074,6 +1116,7 @@ static struct phy_driver airoha_driver[] = {
.suspend = an8801r_suspend,
.resume = an8801r_resume,
.config_aneg = genphy_config_aneg,
+ .read_status = an8801r_read_status,
.config_intr = an8801r_config_intr,
.handle_interrupt = an8801r_handle_interrupt,
.set_wol = an8801r_set_wol,
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 5/6] net: phy: Introduce Airoha AN8801R Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Introduce a driver for the Airoha AN8801R Series Gigabit Ethernet
PHY; this currently supports setting up PHY LEDs, 10/100M, 1000M
speeds, and Wake on LAN and PHY interrupts.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8801.c | 1101 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1108 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d969a792beb5..099f25dceabb 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -90,6 +90,12 @@ config AS21XXX_PHY
AS21210PB1 that all register with the PHY ID 0x7500 0x7500
before the firmware is loaded.
+config AIR_AN8801_PHY
+ tristate "Airoha AN8801 Gigabit PHY"
+ select AIR_NET_PHYLIB
+ help
+ Currently supports the Airoha AN8801R PHY.
+
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7cf1fa9e12cb..de660ae94945 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -29,6 +29,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
+obj-$(CONFIG_AIR_AN8801_PHY) += air_an8801.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
new file mode 100644
index 000000000000..73f94e84da07
--- /dev/null
+++ b/drivers/net/phy/air_an8801.c
@@ -0,0 +1,1101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for the Airoha AN8801 Gigabit PHY.
+ *
+ * Copyright (C) 2025 Airoha Technology Corp.
+ * Copyright (C) 2025 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/pm_wakeirq.h>
+
+#include "air_phy_lib.h"
+
+#define AN8801R_PHY_ID 0xc0ff0421
+
+/* MII Registers */
+
+/* MII Registers - Airoha Page 1 */
+#define AN8801_EXT_REG_PHY 0x14
+#define AN8801_EXT_PHY_STATUS0 GENMASK(1, 0)
+#define AN8801_EXT_PHY_DOWNSHIFT_CTL GENMASK(3, 2) /* 2 to 5 1G auto-neg attempts (0..3) */
+#define AN8801_EXT_PHY_DOWNSHIFT_EN BIT(4)
+#define AN8801_EXT_PHY_CTRL0 BIT(5)
+#define AN8801_EXT_PHY_STATUS1 GENMASK(8, 6)
+#define AN8801_EXT_PHY_CTRL1 GENMASK(14, 9)
+
+/* MII Registers - Airoha Page 4 */
+#define AN8801_PBUS_ACCESS BIT(28)
+#define AN8801_PBUS_EPHY_ACCESS BIT(24)
+#define AN8801_PBUS_CL22_ACCESS BIT(23)
+
+/* BPBUS Registers */
+#define AN8801_BPBUS_REG_LED_GPIO 0x54
+#define AN8801_BPBUS_REG_LED_ID_SEL 0x58
+#define LED_ID_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3))
+#define LED_ID_GPIO_SEL_MASK(gpio) (0x7 << ((gpio) * 3))
+#define AN8801_BPBUS_REG_GPIO_MODE 0x70
+#define AN8801_BPBUS_REG_PHY_IRQ_GPIO 0x7c
+#define AN8801_PHY_IRQ_GPIO_NUM_MASK GENMASK(19, 16)
+#define AN8801_PHY_IRQ_GPIO_NUM 1
+
+#define AN8801_BPBUS_REG_CKO 0x1a4
+#define AN8801_CKO_OUTPUT_MODE_AUTO 3
+
+#define AN8801_BPBUS_REG_LINK_MODE 0x5054
+#define AN8801_BPBUS_LINK_MODE_1000 BIT(0)
+
+#define AN8801_BPBUS_REG_BYPASS_PTP 0x21c004
+#define AN8801_BYP_PTP_SGMII_TO_GPHY BIT(8)
+#define AN8801_BYP_PTP_RGMII_TO_GPHY BIT(0)
+
+#define AN8801_BPBUS_REG_TXDLY_STEP 0x21c024
+#define RGMII_DELAY_STEP_MASK GENMASK(2, 0)
+#define RGMII_DELAY_NO_STEP 0
+#define RGMII_DELAY_STEP_1 1
+#define RGMII_DELAY_STEP_2 2
+#define RGMII_DELAY_STEP_3 3
+#define RGMII_DELAY_STEP_4 4
+#define RGMII_DELAY_STEP_5 5
+#define RGMII_DELAY_STEP_6 6
+#define RGMII_DELAY_STEP_7 7
+#define RGMII_TXDELAY_FORCE_MODE BIT(24)
+
+/* Default RGMII TX delay setting, corresponding to a 1.883ns delay */
+#define AN8801_RGMII_TXDELAY_DEFAULT RGMII_DELAY_STEP_4
+
+#define AN8801_BPBUS_REG_RXDLY_STEP 0x21c02c
+#define RGMII_RXDELAY_ALIGN BIT(4)
+#define RGMII_RXDELAY_FORCE_MODE BIT(24)
+
+/* Default RGMII RX delay setting, corresponding to a 1.992ns delay,
+ * when align bit is set or -0.008ns otherwise.
+ */
+#define AN8801_RGMII_RXDELAY_DEFAULT RGMII_DELAY_NO_STEP
+
+#define AN8801_BPBUS_REG_EFIFO_CTL(x) (0x270004 + (0x100 * (x))) /* 0..2 */
+#define AN8801_EFIFO_ALL_EN GENMASK(7, 0)
+#define AN8801_EFIFO_RX_EN BIT(0)
+#define AN8801_EFIFO_TX_EN BIT(1)
+#define AN8801_EFIFO_RX_CLK_EN BIT(2)
+#define AN8801_EFIFO_TX_CLK_EN BIT(3)
+#define AN8801_EFIFO_RX_EEE_EN BIT(4)
+#define AN8801_EFIFO_TX_EEE_EN BIT(5)
+#define AN8801_EFIFO_RX_ODD_NIBBLE_EN BIT(6)
+#define AN8801_EFIFO_TX_ODD_NIBBLE_EN BIT(7)
+
+#define AN8801_BPBUS_REG_WOL_MAC_16_47 0x285114
+#define AN8801_BPBUS_REG_WOL_MAC_0_15 0x285118
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL1 0x285400
+#define AN8801_WOL_WAKE_MAGIC_EN GENMASK(3, 1)
+#define AN8801_WOL_WAKE_LNKCHG_EN BIT(4)
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL2 0x285404
+#define AN8801_WAKE_OUT_TYPE_PULSE BIT(0) /* Set/Unset: Pulse/Static */
+#define AN8801_WAKE_OUT_POLARITY_NEG BIT(1) /* Set/Unset: Negative/Positive */
+#define AN8801_WAKE_OUT_WIDTH GENMASK(3, 2)
+#define AN8801_WAKE_OUT_84MS 0
+#define AN8801_WAKE_OUT_168MS 1
+#define AN8801_WAKE_OUT_336MS 2
+#define AN8801_WAKE_OUT_672MS 3
+#define AN8801_WAKE_OUT_EN BIT(4)
+#define AN8801_PME_WAKEUP_CLR BIT(8)
+
+#define AN8801_BPBUS_REG_WAKE_IRQ_EN 0x285700
+#define AN8801_BPBUS_REG_WAKE_IRQ_STS 0x285704
+#define AN8801_IRQ_WAKE_LNKCHG BIT(0) /* Wake on link change */
+#define AN8801_IRQ_WAKE_UNIPKT BIT(1) /* Wake on unicast packet */
+#define AN8801_IRQ_WAKE_MULPKT BIT(2) /* Wake on multicast packet */
+#define AN8801_IRQ_WAKE_BCPKT BIT(3) /* Wake on broadcast packet */
+#define AN8801_IRQ_WAKE_MAGICPKT BIT(4) /* Wake on magic packet */
+#define AN8801_IRQ_WAKE_ALL GENMASK(4, 0)
+
+/* MDIO_MMD_VEND1 Registers */
+#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE 0x13
+#define AN8801_PHY_PAIR_DLY_SEL_A_GBE GENMASK(14, 12)
+#define AN8801_PHY_PAIR_DLY_SEL_B_GBE GENMASK(10, 8)
+#define AN8801_PHY_PAIR_DLY_SEL_C_GBE GENMASK(6, 4)
+#define AN8801_PHY_PAIR_DLY_SEL_D_GBE GENMASK(2, 0)
+#define AN8801_PHY_RXADC_CTRL 0xd8
+#define AN8801_PHY_RXADC_SAMP_PHSEL_A BIT(12)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_B BIT(8)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_C BIT(4)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_D BIT(0)
+#define AN8801_PHY_RXADC_REV_0 0xd9
+#define AN8801_PHY_RXADC_REV_MASK_A GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_B GENMASK(7, 0)
+#define AN8801_PHY_RXADC_REV_1 0xda
+#define AN8801_PHY_RXADC_REV_MASK_C GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_D GENMASK(7, 0)
+
+/* MDIO_MMD_VEND2 Registers */
+#define LED_BCR 0x21
+#define LED_BCR_MODE_MASK GENMASK(1, 0)
+#define LED_BCR_TIME_TEST BIT(2)
+#define LED_BCR_CLK_EN BIT(3)
+#define LED_BCR_EVT_ALL BIT(4)
+#define LED_BCR_EXT_CTRL BIT(15)
+#define LED_BCR_MODE_DISABLE 0
+#define LED_BCR_MODE_2LED 1
+#define LED_BCR_MODE_3LED_1 2
+#define LED_BCR_MODE_3LED_2 3
+
+#define LED_ON_DUR 0x22
+#define LED_ON_DUR_MASK GENMASK(15, 0)
+
+#define LED_BLINK_DUR 0x23
+#define LED_BLINK_DUR_MASK GENMASK(15, 0)
+
+#define LED_ON_CTRL(i) (0x24 + ((i) * 2))
+#define LED_ON_EVT_MASK GENMASK(6, 0)
+#define LED_ON_EVT_LINK_1000M BIT(0)
+#define LED_ON_EVT_LINK_100M BIT(1)
+#define LED_ON_EVT_LINK_10M BIT(2)
+#define LED_ON_EVT_LINK_DN BIT(3)
+#define LED_ON_EVT_FDX BIT(4)
+#define LED_ON_EVT_HDX BIT(5)
+#define LED_ON_EVT_FORCE BIT(6)
+#define LED_ON_POL BIT(14)
+#define LED_ON_EN BIT(15)
+
+#define LED_BLINK_CTRL(i) (0x25 + ((i) * 2))
+#define LED_BLINK_EVT_MASK GENMASK(9, 0)
+#define LED_BLINK_EVT_1000M_TX BIT(0)
+#define LED_BLINK_EVT_1000M_RX BIT(1)
+#define LED_BLINK_EVT_100M_TX BIT(2)
+#define LED_BLINK_EVT_100M_RX BIT(3)
+#define LED_BLINK_EVT_10M_TX BIT(4)
+#define LED_BLINK_EVT_10M_RX BIT(5)
+#define LED_BLINK_EVT_COLLISION BIT(6)
+#define LED_BLINK_EVT_RX_CRC_ERR BIT(7)
+#define LED_BLINK_EVT_RX_IDLE_ERR BIT(8)
+#define LED_BLINK_EVT_FORCE BIT(9)
+
+#define AN8801R_NUM_LEDS 3
+#define AN8801_PERIOD_SHIFT 15
+#define AN8801_PERIOD_UNIT 32768 /* (1 << AN8801_PERIOD_SHIFT) */
+#define AN8801_MAX_PERIOD_MS 2147
+
+#define AN8801_LED_DURATION_UNIT_US 32768
+
+#define AN8801_REG_PHY_INTERNAL0 0x600
+#define AN8801_REG_PHY_INTERNAL1 0x601
+#define AN8801_PHY_INTFUNC_MASK GENMASK(15, 0) /* PHY internal functions */
+
+enum an8801r_led_fn {
+ AN8801R_LED_FN_NONE,
+ AN8801R_LED_FN_LINK,
+ AN8801R_LED_FN_ACTIVITY,
+ AN8801R_LED_FN_MAX,
+};
+
+struct an8801r_priv {
+ bool wake_magic_enabled;
+ bool wake_lnkchg_enabled;
+};
+
+static const unsigned long an8801r_led_trig = BIT(TRIGGER_NETDEV_LINK) |
+ BIT(TRIGGER_NETDEV_LINK_10) |
+ BIT(TRIGGER_NETDEV_LINK_100) |
+ BIT(TRIGGER_NETDEV_LINK_1000) |
+ BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_RX_ERR) |
+ BIT(TRIGGER_NETDEV_TX);
+
+static int an8801_buckpbus_reg_rmw(struct phy_device *phydev,
+ u32 addr, u32 mask, u32 set)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, set);
+}
+
+static int an8801_buckpbus_reg_set_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, mask);
+}
+
+static int an8801_buckpbus_reg_clear_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, 0);
+}
+
+static int an8801_buckpbus_reg_write(struct phy_device *phydev, u32 addr,
+ u32 data)
+{
+ return air_phy_buckpbus_reg_write(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static int an8801_buckpbus_reg_read(struct phy_device *phydev, u32 addr,
+ u32 *data)
+{
+ return air_phy_buckpbus_reg_read(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static u32 an8801r_led_blink_ms_to_hw(unsigned long req_ms)
+{
+ u32 req_ns, regval;
+
+ if (req_ms > AN8801_MAX_PERIOD_MS)
+ req_ms = AN8801_MAX_PERIOD_MS;
+
+ req_ns = req_ms * NSEC_PER_MSEC;
+
+ /* Round to the nearest period unit... */
+ regval = req_ns + (AN8801_PERIOD_UNIT / 2);
+
+ /* ...and now divide by the full period */
+ regval >>= AN8801_PERIOD_SHIFT;
+
+ return regval;
+}
+
+static int an8801r_led_blink_set(struct phy_device *phydev, u8 index,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ u32 hw_delay_on, hw_delay_off;
+ bool blink;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ if (delay_on && delay_off) {
+ blink = true;
+
+ if (*delay_on == 0 || *delay_off == 0) {
+ *delay_on = 64;
+ *delay_off = 64;
+ }
+
+ hw_delay_on = an8801r_led_blink_ms_to_hw(*delay_on);
+ hw_delay_off = an8801r_led_blink_ms_to_hw(*delay_off);
+ } else {
+ blink = false;
+ }
+
+ if (blink) {
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR,
+ (hw_delay_on + hw_delay_off) &
+ LED_BLINK_DUR_MASK);
+ if (ret)
+ goto error;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR,
+ hw_delay_on);
+ if (ret)
+ goto error;
+ }
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK,
+ blink ? LED_BLINK_EVT_FORCE : 0);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK,
+ 0);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, blink ? LED_ON_EN : 0);
+
+error:
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, 0);
+ return ret;
+}
+
+static int an8801r_led_brightness_set(struct phy_device *phydev, u8 index,
+ enum led_brightness value)
+{
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK,
+ (value == LED_OFF) ? 0 : LED_ON_EVT_FORCE);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, (value == LED_OFF) ? 0 : LED_ON_EN);
+}
+
+static int an8801r_led_hw_control_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules)
+{
+ int on, blink;
+
+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index));
+ if (on < 0)
+ return on;
+
+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index));
+ if (blink < 0)
+ return blink;
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_10, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_100M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_100, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_100M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_RX, blink))
+ __set_bit(TRIGGER_NETDEV_RX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_TX, blink))
+ __set_bit(TRIGGER_NETDEV_TX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_RX_CRC_ERR, blink))
+ __set_bit(TRIGGER_NETDEV_RX_ERR, rules);
+
+ return 0;
+}
+
+static int an8801r_led_trig_to_hw(unsigned long rules, u16 *on, u16 *blink)
+{
+ /* All combinations of the supported triggers are allowed */
+ if (rules & ~an8801r_led_trig)
+ return -EOPNOTSUPP;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+ *on |= LED_ON_EVT_LINK_10M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+ *on |= LED_ON_EVT_LINK_100M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+ *on |= LED_ON_EVT_LINK_1000M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK, &rules)) {
+ *on |= LED_ON_EVT_LINK_10M;
+ *on |= LED_ON_EVT_LINK_100M;
+ *on |= LED_ON_EVT_LINK_1000M;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_RX;
+ *blink |= LED_BLINK_EVT_100M_RX;
+ *blink |= LED_BLINK_EVT_1000M_RX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_TX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_TX;
+ *blink |= LED_BLINK_EVT_100M_TX;
+ *blink |= LED_BLINK_EVT_1000M_TX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX_ERR, &rules))
+ *blink |= LED_BLINK_EVT_RX_CRC_ERR;
+
+ return 0;
+}
+
+static int an8801r_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ return an8801r_led_trig_to_hw(rules, &on, &blink);
+}
+
+static int an8801r_led_hw_control_set(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ ret = an8801r_led_trig_to_hw(rules, &on, &blink);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK, on);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK, blink);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, on | blink ? LED_ON_EN : 0);
+}
+
+static int an8801r_led_polarity_set(struct phy_device *phydev, int index,
+ unsigned long modes)
+{
+ bool active_high = true;
+ unsigned long mode;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ switch (mode) {
+ case PHY_LED_ACTIVE_HIGH:
+ break;
+ case PHY_LED_ACTIVE_LOW:
+ active_high = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_POL, active_high ? LED_ON_POL : 0);
+}
+
+static int an8801r_led_init(struct phy_device *phydev, u8 *led_cfg)
+{
+ int led_id, ret;
+
+ /* Set LED BCR Enable */
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LED_BCR,
+ LED_BCR_EXT_CTRL | LED_BCR_CLK_EN);
+ if (ret)
+ return ret;
+
+ for (led_id = 0; led_id < AN8801R_NUM_LEDS; led_id++) {
+ unsigned long led_trigger = 0;
+ u32 led_gpio = led_id + 1;
+
+ switch (led_cfg[led_id]) {
+ case AN8801R_LED_FN_LINK:
+ led_trigger = BIT(TRIGGER_NETDEV_LINK);
+ break;
+ case AN8801R_LED_FN_ACTIVITY:
+ led_trigger = BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_TX);
+ break;
+ default:
+ led_trigger = 0;
+ break;
+ }
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_LED_GPIO,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LED_ID_SEL,
+ LED_ID_GPIO_SEL_MASK(led_gpio),
+ LED_ID_GPIO_SEL(led_id,
+ led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_GPIO_MODE,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ if (!led_trigger)
+ continue;
+
+ ret = an8801r_led_hw_control_set(phydev, led_id, led_trigger);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int an8801r_reset_wake(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ u32 reg_val = 0;
+ int ret;
+
+ /* Enable wakeup clear and disable wake up output */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_PME_WAKEUP_CLR |
+ AN8801_WAKE_OUT_POLARITY_NEG);
+ if (ret)
+ return ret;
+
+ /* Clear WAKEUP_CTL1 register before enabling the wakeup events
+ * again
+ */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ 0);
+ if (ret)
+ return ret;
+
+ if (priv->wake_magic_enabled)
+ reg_val |= AN8801_WOL_WAKE_MAGIC_EN;
+
+ if (priv->wake_lnkchg_enabled)
+ reg_val |= AN8801_WOL_WAKE_LNKCHG_EN;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* Disable wake up clear and re-enable wake up output */
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_WAKE_OUT_POLARITY_NEG |
+ AN8801_WAKE_OUT_EN);
+}
+
+static int an8801r_ack_interrupt(struct phy_device *phydev)
+{
+ int ret;
+
+ /* Reset wake status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+
+ /* Clear the interrupts by writing the reg */
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ AN8801_IRQ_WAKE_ALL);
+}
+
+static int an8801r_config_intr(struct phy_device *phydev)
+{
+ int ret;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ u32 val = FIELD_PREP(AN8801_PHY_IRQ_GPIO_NUM_MASK,
+ AN8801_PHY_IRQ_GPIO_NUM);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ 0);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ return an8801r_ack_interrupt(phydev);
+}
+
+static irqreturn_t an8801r_handle_interrupt(struct phy_device *phydev)
+{
+ u32 irq_status = 0;
+ bool irq_handled = false;
+ int ret;
+
+ ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ &irq_status);
+ if (ret)
+ return IRQ_NONE;
+
+ ret = an8801r_ack_interrupt(phydev);
+ if (ret)
+ return IRQ_NONE;
+
+ if (irq_status & AN8801_IRQ_WAKE_MAGICPKT) {
+ pm_wakeup_event(&phydev->mdio.dev, 0);
+ irq_handled = true;
+ }
+
+ if (irq_status & AN8801_IRQ_WAKE_LNKCHG) {
+ phy_trigger_machine(phydev);
+ irq_handled = true;
+ }
+
+ return irq_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static void an8801r_get_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ u32 reg_val;
+ int ret;
+
+ /* If the PHY is not capable of waking the system, then WoL can not
+ * be supported.
+ */
+ if (!device_can_wakeup(&phydev->mdio.dev)) {
+ wol->supported = 0;
+ return;
+ }
+
+ wol->supported = WAKE_MAGIC;
+ wol->wolopts = 0;
+
+ ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ ®_val);
+ if (ret)
+ return;
+
+ if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
+ wol->wolopts |= WAKE_MAGIC;
+ else
+ wol->wolopts &= ~WAKE_MAGIC;
+}
+
+static int an8801r_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *attach_dev = phydev->attached_dev;
+ const unsigned char *macaddr = attach_dev->dev_addr;
+ struct an8801r_priv *priv = phydev->priv;
+ u32 reg_val;
+ int ret;
+
+ if (!device_can_wakeup(&phydev->mdio.dev))
+ return -EOPNOTSUPP;
+
+ if (wol->wolopts & ~WAKE_MAGIC)
+ return -EINVAL;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ /* MAC bits 16..47 */
+ reg_val = (macaddr[2] << 24) | (macaddr[3] << 16);
+ reg_val |= (macaddr[4] << 8) | (macaddr[5]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_16_47,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* MAC bits 0..15 */
+ reg_val = (macaddr[0] << 8) | (macaddr[1]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_0_15,
+ reg_val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+ }
+
+ priv->wake_magic_enabled = !!(wol->wolopts & WAKE_MAGIC);
+
+ return device_set_wakeup_enable(&phydev->mdio.dev,
+ priv->wake_magic_enabled);
+}
+
+static int an8801r_of_init_leds(struct phy_device *phydev, u8 *led_cfg)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *leds;
+ u32 function_enum_idx;
+ int ret = 0;
+
+ if (!np)
+ return 0;
+
+ /* If devicetree is present, leds configuration is required */
+ leds = of_get_child_by_name(np, "leds");
+ if (!leds)
+ return 0;
+
+ for_each_available_child_of_node_scoped(leds, led) {
+ u32 led_idx;
+
+ ret = of_property_read_u32(led, "reg", &led_idx);
+ if (ret)
+ goto out;
+
+ if (led_idx >= AN8801R_NUM_LEDS) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = of_property_read_u32(led, "function-enumerator",
+ &function_enum_idx);
+ if (ret) {
+ function_enum_idx = AN8801R_LED_FN_NONE;
+ ret = 0;
+ }
+
+ if (function_enum_idx >= AN8801R_LED_FN_MAX) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ led_cfg[led_idx] = function_enum_idx;
+ }
+out:
+ of_node_put(leds);
+ return ret;
+}
+
+static int an8801r_rgmii_rxdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ /* Set force mode bit to enable RX delay insertion */
+ reg_val = delay_steps | RGMII_RXDELAY_FORCE_MODE;
+
+ /* Set align bit to add extra offset for RX delay */
+ reg_val |= RGMII_RXDELAY_ALIGN;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_txdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ /* Set force mode bit to enable TX delay insertion */
+ reg_val = delay_steps | RGMII_TXDELAY_FORCE_MODE;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_delay_config(struct phy_device *phydev)
+{
+ bool enable_delay;
+ u16 delay_step;
+ int ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_TXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ ret = an8801r_rgmii_txdelay(phydev, enable_delay, delay_step);
+ if (ret)
+ return ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_RXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ return an8801r_rgmii_rxdelay(phydev, enable_delay, delay_step);
+}
+
+static int an8801r_config_init(struct phy_device *phydev)
+{
+ u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
+ int ret;
+
+ ret = an8801r_of_init_leds(phydev, led_default_function);
+ if (ret)
+ return ret;
+
+ /* Disable Low Power Mode (LPM) */
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2));
+ if (ret)
+ return ret;
+
+ /* Set the PHY to perform auto-downshift after 3 auto-negotiation
+ * attempts
+ */
+ ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,
+ AN8801_EXT_REG_PHY,
+ FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
+ FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
+ AN8801_EXT_PHY_DOWNSHIFT_EN);
+ if (ret < 0)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP,
+ AN8801_BYP_PTP_RGMII_TO_GPHY);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0),
+ AN8801_EFIFO_RX_EN |
+ AN8801_EFIFO_TX_EN |
+ AN8801_EFIFO_RX_CLK_EN |
+ AN8801_EFIFO_TX_CLK_EN |
+ AN8801_EFIFO_RX_EEE_EN |
+ AN8801_EFIFO_TX_EEE_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ AN8801_PHY_TX_PAIR_DLY_SEL_GBE,
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_A_GBE, 4) |
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_C_GBE, 4));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_CTRL,
+ AN8801_PHY_RXADC_SAMP_PHSEL_A |
+ AN8801_PHY_RXADC_SAMP_PHSEL_C);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_A, 1));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_C, 1));
+ if (ret)
+ return ret;
+
+ ret = an8801r_rgmii_delay_config(phydev);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_CKO,
+ AN8801_CKO_OUTPUT_MODE_AUTO);
+ if (ret)
+ return ret;
+
+ ret = an8801r_led_init(phydev, led_default_function);
+ if (ret) {
+ phydev_err(phydev, "Cannot initialize LEDs: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int an8801r_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct an8801r_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->wake_lnkchg_enabled = true;
+
+ phydev->priv = priv;
+
+ /* Mark this PHY as wakeup capable and register the interrupt as a
+ * wakeup IRQ if the PHY is marked as a wakeup source in devicetree,
+ * and the interrupt is valid.
+ */
+ if (of_property_read_bool(dev->of_node, "wakeup-source") &&
+ phy_interrupt_is_valid(phydev)) {
+ device_set_wakeup_capable(dev, true);
+ devm_pm_set_wake_irq(dev, phydev->irq);
+ }
+
+ return 0;
+}
+
+static int an8801r_suspend(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ /* If the PHY may wake up by a wake-on-line event, disable the link
+ * interrupt to only keep the WOL magic interrupt enabled
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = false;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ /* Reset Wol status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+ }
+
+ if (!phydev->wol_enabled)
+ return genphy_suspend(phydev);
+
+ return 0;
+}
+
+static int an8801r_resume(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ ret = genphy_resume(phydev);
+ if (ret)
+ return ret;
+
+ /* Restore the interrupt enable so phylib can receive link
+ * state interrupts.
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = true;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_LNKCHG_EN);
+ if (ret)
+ return ret;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ }
+ }
+
+ return ret;
+}
+
+static struct phy_driver airoha_driver[] = {
+{
+ PHY_ID_MATCH_MODEL(AN8801R_PHY_ID),
+ .name = "Airoha AN8801R",
+ .probe = an8801r_probe,
+ .config_init = an8801r_config_init,
+ .suspend = an8801r_suspend,
+ .resume = an8801r_resume,
+ .config_aneg = genphy_config_aneg,
+ .config_intr = an8801r_config_intr,
+ .handle_interrupt = an8801r_handle_interrupt,
+ .set_wol = an8801r_set_wol,
+ .get_wol = an8801r_get_wol,
+ .read_page = air_phy_read_page,
+ .write_page = air_phy_write_page,
+ .flags = PHY_ALWAYS_CALL_SUSPEND,
+ .led_brightness_set = an8801r_led_brightness_set,
+ .led_blink_set = an8801r_led_blink_set,
+ .led_hw_is_supported = an8801r_led_hw_is_supported,
+ .led_hw_control_set = an8801r_led_hw_control_set,
+ .led_hw_control_get = an8801r_led_hw_control_get,
+ .led_polarity_set = an8801r_led_polarity_set,
+} };
+module_phy_driver(airoha_driver);
+
+static struct mdio_device_id __maybe_unused an8801_tbl[] = {
+ { PHY_ID_MATCH_MODEL(AN8801R_PHY_ID) },
+ { }
+};
+MODULE_DEVICE_TABLE(mdio, an8801_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8801 PHY driver");
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 4/6] net: phy: Rename Airoha common BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
Rename the BuckPBus register accessors functions present in air_phy_lib
and their calls in air_en8811h driver, so all exported functions start
with the same prefix.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 110 +++++++++++++++++++++---------------------
drivers/net/phy/air_phy_lib.c | 18 +++----
drivers/net/phy/air_phy_lib.h | 12 ++---
3 files changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 2498bd3f7993..a42898ae4135 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -287,8 +287,8 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev)
{
int ret, reg_value;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_FINISH);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_FINISH);
if (ret)
return ret;
@@ -313,28 +313,29 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 set1,
int ret;
/* Configure CRC */
- ret = air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN,
- AN8811HB_CRC_RD_EN);
+ ret = air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ AN8811HB_CRC_RD_EN);
if (ret < 0)
return ret;
- air_buckpbus_reg_read(phydev, set1, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, set1, &pbus_value);
do {
msleep(300);
- air_buckpbus_reg_read(phydev, mon2, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value);
/* We do not know what errors this check is supposed
* catch or what to do about a failure. So print the
* result and continue like the vendor driver does.
*/
if (pbus_value & AN8811HB_CRC_ST) {
- air_buckpbus_reg_read(phydev, mon3, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value);
phydev_dbg(phydev, "CRC Check %s!\n",
pbus_value & AN8811HB_CRC_CHECK_PASS ?
"PASS" : "FAIL");
- return air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN, 0);
+ return air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ 0);
}
} while (--retry);
@@ -346,8 +347,8 @@ static void en8811h_print_fw_version(struct phy_device *phydev)
{
struct en8811h_priv *priv = phydev->priv;
- air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
- &priv->firmware_version);
+ air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
+ &priv->firmware_version);
phydev_info(phydev, "MD32 firmware version: %08x\n",
priv->firmware_version);
}
@@ -372,8 +373,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -414,14 +415,14 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_rel1;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING,
- EN8811H_FW_CTRL_2_LOADING);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING,
+ EN8811H_FW_CTRL_2_LOADING);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -433,8 +434,8 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING, 0);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING, 0);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -460,8 +461,8 @@ static int en8811h_restart_mcu(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -755,7 +756,7 @@ static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
if (ret < 0)
return ret;
@@ -767,9 +768,9 @@ static int an8811hb_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK,
- AN8811HB_CLK_DRV_CKO_MASK);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK,
+ AN8811HB_CLK_DRV_CKO_MASK);
}
static void an8811hb_clk_disable(struct clk_hw *hw)
@@ -777,8 +778,8 @@ static void an8811hb_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK, 0);
+ air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK, 0);
}
static int an8811hb_clk_is_enabled(struct clk_hw *hw)
@@ -788,7 +789,7 @@ static int an8811hb_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
if (ret < 0)
return ret;
@@ -854,7 +855,7 @@ static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
if (ret < 0)
return ret;
@@ -866,9 +867,9 @@ static int en8811h_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO,
- EN8811H_CLK_CGM_CKO);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO,
+ EN8811H_CLK_CGM_CKO);
}
static void en8811h_clk_disable(struct clk_hw *hw)
@@ -876,8 +877,8 @@ static void en8811h_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO, 0);
+ air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO, 0);
}
static int en8811h_clk_is_enabled(struct clk_hw *hw)
@@ -887,7 +888,7 @@ static int en8811h_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
if (ret < 0)
return ret;
@@ -998,9 +999,9 @@ static int an8811hb_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
- AN8811HB_GPIO_OUTPUT_345,
- AN8811HB_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
+ AN8811HB_GPIO_OUTPUT_345,
+ AN8811HB_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1039,9 +1040,9 @@ static int en8811h_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
- EN8811H_GPIO_OUTPUT_345,
- EN8811H_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
+ EN8811H_GPIO_OUTPUT_345,
+ EN8811H_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1061,9 +1062,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
return ret;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
- AN8811HB_RX_POLARITY_NORMAL,
- pbus_value);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
+ AN8811HB_RX_POLARITY_NORMAL,
+ pbus_value);
if (ret < 0)
return ret;
@@ -1074,9 +1075,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
pbus_value = 0;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
- return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
- AN8811HB_TX_POLARITY_NORMAL,
- pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
+ AN8811HB_TX_POLARITY_NORMAL,
+ pbus_value);
}
static int en8811h_config_serdes_polarity(struct phy_device *phydev)
@@ -1110,9 +1111,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev)
if (pol == PHY_POL_NORMAL)
pbus_value |= EN8811H_POLARITY_TX_NORMAL;
- return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
- EN8811H_POLARITY_RX_REVERSE |
- EN8811H_POLARITY_TX_NORMAL, pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
+ EN8811H_POLARITY_RX_REVERSE |
+ EN8811H_POLARITY_TX_NORMAL,
+ pbus_value);
}
static int an8811hb_config_init(struct phy_device *phydev)
@@ -1264,8 +1266,8 @@ static int en8811h_read_status(struct phy_device *phydev)
val & MDIO_AN_10GBT_STAT_LP2_5G);
} else {
/* Get link partner 2.5GBASE-T ability from vendor register */
- ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
- &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
+ &pbus_value);
if (ret < 0)
return ret;
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index aba4f95fe9e6..859fa41406d1 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -137,8 +137,8 @@ static int __air_buckpbus_reg_modify(struct phy_device *phydev,
return 0;
}
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data)
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
{
int saved_page;
int ret = 0;
@@ -154,10 +154,10 @@ int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_read);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data)
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
{
int saved_page;
int ret = 0;
@@ -174,10 +174,10 @@ int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_write);
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set)
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
{
int saved_page;
int ret = 0;
@@ -194,7 +194,7 @@ int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_modify);
int air_phy_read_page(struct phy_device *phydev)
{
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index b637f3e0f2d5..a2f8b3725761 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -27,12 +27,12 @@
#define AIR_BPBUS_RD_DATA_HIGH 0x17
#define AIR_BPBUS_RD_DATA_LOW 0x18
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set);
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data);
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 3/6] net: phy: air_phy_lib: Factorize BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
In preparation of Airoha AN8801R PHY support, move the BuckPBus
register accessors and definitions, present in air_en8811h driver,
into the Airoha PHY shared code (air_phy_lib), so they will be usable
by the new driver without duplicating them.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 193 ------------------------------------------
drivers/net/phy/air_phy_lib.c | 181 +++++++++++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 23 +++++
3 files changed, 204 insertions(+), 193 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index be7c3426182a..2498bd3f7993 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -42,22 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_PHY_PAGE_STANDARD 0x0000
-#define AIR_PHY_PAGE_EXTENDED_4 0x0004
-
-/* MII Registers Page 4*/
-#define AIR_BPBUS_MODE 0x10
-#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
-#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
-#define AIR_BPBUS_WR_ADDR_HIGH 0x11
-#define AIR_BPBUS_WR_ADDR_LOW 0x12
-#define AIR_BPBUS_WR_DATA_HIGH 0x13
-#define AIR_BPBUS_WR_DATA_LOW 0x14
-#define AIR_BPBUS_RD_ADDR_HIGH 0x15
-#define AIR_BPBUS_RD_ADDR_LOW 0x16
-#define AIR_BPBUS_RD_DATA_HIGH 0x17
-#define AIR_BPBUS_RD_DATA_LOW 0x18
-
/* Registers on MDIO_MMD_VEND1 */
#define EN8811H_PHY_FW_STATUS 0x8009
#define EN8811H_PHY_READY 0x02
@@ -245,183 +229,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int __air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_write(phydev, pbus_address,
- pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int pbus_data_low, pbus_data_high;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- *pbus_data = pbus_data_low | (pbus_data_high << 16);
- return 0;
-}
-
-static int air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int pbus_data_low, pbus_data_high;
- u32 pbus_data_old, pbus_data_new;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- pbus_data_old = pbus_data_low | (pbus_data_high << 16);
- pbus_data_new = (pbus_data_old & ~mask) | set;
- if (pbus_data_new == pbus_data_old)
- return 0;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
- set);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
static int __air_write_buf(struct phy_device *phydev, u32 address,
const struct firmware *fw)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index 8ef5af4becf0..aba4f95fe9e6 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -10,11 +10,192 @@
#include <linux/export.h>
#include <linux/module.h>
#include <linux/phy.h>
+#include <linux/wordpart.h>
#include "air_phy_lib.h"
#define AIR_EXT_PAGE_ACCESS 0x1f
+static int __air_buckpbus_reg_read(struct phy_device *phydev,
+ u32 pbus_address, u32 *pbus_data)
+{
+ int pbus_data_low, pbus_data_high;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ *pbus_data = pbus_data_low | (pbus_data_high << 16);
+ return 0;
+}
+
+static int __air_buckpbus_reg_write(struct phy_device *phydev,
+ u32 pbus_address, u32 pbus_data)
+{
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int __air_buckpbus_reg_modify(struct phy_device *phydev,
+ u32 pbus_address, u32 mask, u32 set)
+{
+ int pbus_data_low, pbus_data_high;
+ u32 pbus_data_old, pbus_data_new;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ pbus_data_new = (pbus_data_old & ~mask) | set;
+ if (pbus_data_new == pbus_data_old)
+ return 0;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
+
+int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_write(phydev, pbus_address,
+ pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
+
+int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
+ set);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
+
int air_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index 79367e8e5907..b637f3e0f2d5 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -10,6 +10,29 @@
#include <linux/phy.h>
+#define AIR_PHY_PAGE_STANDARD 0x0000
+#define AIR_PHY_PAGE_EXTENDED_1 0x0001
+#define AIR_PHY_PAGE_EXTENDED_4 0x0004
+
+/* MII Registers Page 4*/
+#define AIR_BPBUS_MODE 0x10
+#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
+#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
+#define AIR_BPBUS_WR_ADDR_HIGH 0x11
+#define AIR_BPBUS_WR_ADDR_LOW 0x12
+#define AIR_BPBUS_WR_DATA_HIGH 0x13
+#define AIR_BPBUS_WR_DATA_LOW 0x14
+#define AIR_BPBUS_RD_ADDR_HIGH 0x15
+#define AIR_BPBUS_RD_ADDR_LOW 0x16
+#define AIR_BPBUS_RD_DATA_HIGH 0x17
+#define AIR_BPBUS_RD_DATA_LOW 0x18
+
+int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 2/6] net: phy: Add Airoha phy library for shared code
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
In preparation of Airoha AN8801R PHY support, split out the interface
functions that will be common between the already present air_en8811h
driver and the new one, and put them into a new library named
air_phy_lib.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_en8811h.c | 13 ++-----------
drivers/net/phy/air_phy_lib.c | 32 ++++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 16 ++++++++++++++++
5 files changed, 57 insertions(+), 11 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 8b51bdc2e945..d969a792beb5 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -92,10 +92,16 @@ config AS21XXX_PHY
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ select AIR_NET_PHYLIB
select PHY_COMMON_PROPS
help
Currently supports the Airoha EN8811H PHY.
+config AIR_NET_PHYLIB
+ tristate
+ help
+ Airoha Ethernet PHY common library
+
config AMD_PHY
tristate "AMD and Altima PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 05e4878af27a..7cf1fa9e12cb 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,6 +30,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o
obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 29ae73e65caa..be7c3426182a 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -21,6 +21,8 @@
#include <linux/wordpart.h>
#include <linux/unaligned.h>
+#include "air_phy_lib.h"
+
#define EN8811H_PHY_ID 0x03a2a411
#define AN8811HB_PHY_ID 0xc0ff04a0
@@ -40,7 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_EXT_PAGE_ACCESS 0x1f
#define AIR_PHY_PAGE_STANDARD 0x0000
#define AIR_PHY_PAGE_EXTENDED_4 0x0004
@@ -244,16 +245,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int air_phy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-}
-
-static int air_phy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-}
-
static int __air_buckpbus_reg_write(struct phy_device *phydev,
u32 pbus_address, u32 pbus_data)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
new file mode 100644
index 000000000000..8ef5af4becf0
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Airoha Ethernet PHY common library
+ *
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+
+#include "air_phy_lib.h"
+
+#define AIR_EXT_PAGE_ACCESS 0x1f
+
+int air_phy_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
+}
+EXPORT_SYMBOL_GPL(air_phy_read_page);
+
+int air_phy_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
+}
+EXPORT_SYMBOL_GPL(air_phy_write_page);
+
+MODULE_DESCRIPTION("Airoha PHY Library");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Louis-Alexis Eyraud");
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
new file mode 100644
index 000000000000..79367e8e5907
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef __AIR_PHY_LIB_H
+#define __AIR_PHY_LIB_H
+
+#include <linux/phy.h>
+
+int air_phy_read_page(struct phy_device *phydev);
+int air_phy_write_page(struct phy_device *phydev, int page);
+
+#endif /* __AIR_PHY_LIB_H */
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 0/6] Introduce Airoha AN8801R series Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
This series introduces the Airoha AN8801R Gigabit Ethernet PHY initial
support.
The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
with Single-port serdes interface for 1000Base-X/RGMII.
This chip is compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE
802.3(u,ab) and supports:
- Energy Efficient Ethernet (802.3az)
- Full Duplex Control Flow (802.3x)
- auto-negotiation
- crossover detect and autocorrection,
- Wake-on-LAN with Magic Packet
- Jumbo Frame up to 9 Kilobytes.
This PHY also supports up to three user-configurable LEDs, which are
usually used for LAN Activity, 100M, 1000M indication.
The series provides the devicetree binding and the driver that have been
written by AngeloGioacchino Del Regno, based on downstream
implementation ([1]). The driver allows setting up PHY LEDs, 10/100M,
1000M speeds, and Wake on LAN and PHY interrupts.
Since v2, the series also adds the air_phy_lib library, which goal is to
share common code between air_en8811h and air_an8801 drivers, and its use
in them. The first shared functions are the existing BuckPbus register
accessors and air_phy_read/write_page functions coming from air_en8811h
driver.
The series is based on net-next kernel tree (sha1: 830d8771ae3c) and
I have tested it on Mediatek Genio 720-EVK board (that integrates an
Airoha AN8801RIN/A Ethernet PHY) with early board hardware enablement
patches.
[1]: https://gitlab.com/mediatek/aiot/bsp/linux/-/blob/mtk-v6.6/drivers/net/phy/an8801.c
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Changes in v4:
- Rebased on net-next (830d8771ae3c)
- Added in patch 1 the missing function-enumator property description,
that should already have been present in v3
- Modified patch 1 and patch 5 subjects to use AN8801R and not AN8801/R
(detected by sashiko-nipa)
- Modified patch 3 to add missing wordpath.h include (detected by
sashiko.dev)
- Modified patch 5 to use NSEC_PER_MSEC definition instead of hardcoded
value in an8801r_led_blink_ms_to_hw
- Removed unnecessary RGMII_DELAY_STEP_MASK mask operation in
an8801r_rgmii_rxdelay and an8801r_rgmii_txdelay
- Removed extra empty line in an8801r_led_hw_control_set
- Improved AN8801_RGMII_TX/RXDELAY_DEFAULT definition comments
- Fixed inverted GENMASK arguments in AN8801_WAKE_OUT_WIDTH
definition (detected by sashiko-nipa)
- Fixed possible overflow when writing LED_BLINK_DUR register value
in an8801r_led_blink_set (detected by sashiko-nipa and sashiko.dev)
- Modified the an8801r_handle_interrupt to allow the WAKE_MAGICPKT and
WAKE_LNKCHG interrupts handling in the same call
(detected by sashiko-nipa and sashiko.dev)
- Add extra check in an8801r_set_wol to reject unsupported modes
(detected by sashiko-nipa)
- Fixed supported led trigger detection in an8801r_led_trig_to_hw
(detected by sashiko.dev)
- Fixed possible uninitialized return value in an8801r_of_init_leds
(detected by sashiko-nipa and sashiko.dev)
- Modified patch 6 to fix possible cases where the link mode register value
might not be updated (detected by sashiko-nipa)
- Added new reviewed-by trailers
- Link to v3: https://lore.kernel.org/r/20260512-add-airoha-an8801-support-v3-0-1edb34e363ae@collabora.com
Changes in v3:
- Rebased on net-next (7e0cccae6b45)
- Updated patch 1 to describe the function-enumator property for the
LEDs and its possible values
- Modified patch 2 to add missing includes in air_phy_lib source and
header files
- Split patch 3 in two so that the api call renames in air_en8811h
driver is done in a separate patch
- Simplified return code handling in several functions
- Fixed return code handling in several functions detected by AI
peer-reviews (netdev-ai or sashiko)
- Added additional interrupt enabled check before enabling/disabling
link changed interrupt in an8801r_suspend/resume callbacks
- Fixed register mask for GPIO LED selection register in
an8801r_led_init function
- Fixed potential uninitialized variable in an8801r_led_polarity_set
function
- Fixed LED blink register settings in an8801r_led_blink_set function
- Split an8801r_read_status function implementation in a separate patch
as requested and add comment to describe why the link mode register
needed to be modified after reading the link speed.
- Link to v2: https://lore.kernel.org/r/20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com
Changes in v2:
- Rebased on net-next (d1e59a4697371)
- Fixed dt-bindings to remove the leds property from the required ones and
add wakeup-source as valid property
- Added new reviewed-by trailer for dt_bindings
- Added new patches (2 and 3) to create air_phy_lib, to share common code
between air_en8811h and air_an8801 drivers and use it in air_en8811h.
- Remove custom BuckPBus register accessor functions and definitions from
air_an8801 and use the ones from air_phy_lib. It also fixes a build
issue on v1 due to an uninitialized variable used in
__air_buckpbus_reg_read, that is now removed from driver code
- Added air_an8801_probe function to allocate the newly added private
data structure and detect if the PHY is wakeup capable and the interrupt
can be registered as a wakeup IRQ, and perform the needed actions
- Added an8801r_suspend and an8801r_resume functions to perform specific
actions when WoL is enabled (reset its status, enable/disable the Link
Changed interrupt) and call the genphy_suspend/resume functions if
needed
- Modified an8801r_get_wol to return WoL is not supported if the PHY
device is not wakeup capable
- Modified an8801r_set_wol to return EOPNOTSUPP error code if the PHY
device is not wakeup capable, and to update the wakeup flag according
to WoL mode
- Modified an8801r_config_init to remove EEE disabling and replace
__phy_write use by phy_write_paged
- Reworked an8801r_rgmii_delay_config and its subfunctions to fix a
double return use in PHY_INTERFACE_MODE_RGMII_ID case, replace the
magic value use for default TX and RX delay and handle better the
enable/disable the inserted delays for all RGMII modes
- Merged an8801r_did_interrupt function in an8801r_handle_interrupt
- Modified the an8801r_handle_interrupt processing to process differently
the Magic Packet (to notify system wakeup) and the Link Changed
interrupt (to notify PHY state machine)
- Splitted the reset WoL status part from an8801r_ack_interrupt and fix
an issue that in some random cases made WAKEUP_CTL1 register lose the
Magic Packet WoL settings
- Modified an8801r_of_init_leds function so it does not return an error
if the leds configuration is not present in devicetree
- Removed feature field and add PHY_ALWAYS_CALL_SUSPEND flag in
airoha_driver data structure
- Link to v1: https://lore.kernel.org/r/20260304-add-airoha-an8801-support-v1-0-0ae4ee5a2f9d@collabora.com
---
AngeloGioacchino Del Regno (2):
dt-bindings: net: Add support for Airoha AN8801R GbE PHY
net: phy: Introduce Airoha AN8801R Gigabit Ethernet PHY driver
Louis-Alexis Eyraud (4):
net: phy: Add Airoha phy library for shared code
net: phy: air_phy_lib: Factorize BuckPBus register accessors
net: phy: Rename Airoha common BuckPBus register accessors
net: phy: air_an8801: ensure maximum available speed link use
.../devicetree/bindings/net/airoha,an8801.yaml | 116 ++
drivers/net/phy/Kconfig | 12 +
drivers/net/phy/Makefile | 2 +
drivers/net/phy/air_an8801.c | 1144 ++++++++++++++++++++
drivers/net/phy/air_en8811h.c | 316 +-----
drivers/net/phy/air_phy_lib.c | 213 ++++
drivers/net/phy/air_phy_lib.h | 39 +
7 files changed, 1584 insertions(+), 258 deletions(-)
---
base-commit: 830d8771ae3c7bc90a62dde76a6556e612529fbc
change-id: 20260303-add-airoha-an8801-support-57d544a4afed
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply
* [PATCH net-next v4 1/6] dt-bindings: net: Add support for Airoha AN8801R GbE PHY
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add a new binding to support the Airoha AN8801R Series Gigabit
Ethernet PHY.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../devicetree/bindings/net/airoha,an8801.yaml | 116 +++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
new file mode 100644
index 000000000000..fb2f70ceb33a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8801.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8801R Series PHY
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
+ with Single-port serdes interface for 1000Base-X/RGMII; this chip is
+ compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab)
+ and supports Energy Efficient Ethernet (802.3az), Full Duplex Control
+ Flow (802.3x), auto-negotiation, crossover detect and autocorrection,
+ Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes.
+ This PHY also supports up to three user-configurable LEDs, which are
+ usually used for LAN Activity, 100M, 1000M indication.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-idc0ff.0421
+
+ reg:
+ maxItems: 1
+
+ leds:
+ type: object
+ description:
+ Describes the LEDs associated to the PHY
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^led@[0-2]$":
+ type: object
+ description: PHY LEDs
+ $ref: /schemas/leds/common.yaml#
+
+ properties:
+ reg:
+ enum: [0, 1, 2]
+
+ function-enumerator:
+ enum: [0, 1, 2]
+ description: |
+ Specifies a function for offloading LED functionality to the PHY:
+ 0 - No offloading
+ 1 - Link Availability
+ 2 - Network Activity
+
+ required:
+ - reg
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enable Wake-on-LAN support
+
+required:
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-idc0ff.0421";
+ reg = <0>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ default-state = "keep";
+ };
+ };
+ };
+ };
--
2.54.0
^ permalink raw reply related
* [PATCH] PCI: mediatek: Free IRQ domains while freeing Root Ports
From: Manivannan Sadhasivam @ 2026-05-21 7:19 UTC (permalink / raw)
To: lpieralisi, kwilczynski, mani, ryder.lee, jianjun.wang
Cc: bhelgaas, robh, linux-pci, linux-mediatek, linux-kernel,
Manivannan Sadhasivam, stable, Caleb James DeLisle
Currently, the driver frees the IRQ domains only during driver remove().
But when mtk_pcie_enable_port() fails for some reason, the domains are
not freed. This leads to resource leakage.
Hence, free the IRQ domains inside mtk_pcie_port_free() helper which gets
called in the error path of mtk_pcie_enable_port() and also during driver
removal.
This issue was flagged by Sashiko when reviewing the EcoNet EN7528 SoC
support series.
Cc: stable@vger.kernel.org # 5.10
Cc: Caleb James DeLisle <cjd@cjdns.fr>
Fixes: b099631df160 ("PCI: mediatek: Add controller support for MT2712 and MT7622")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
drivers/pci/controller/pcie-mediatek.c | 35 +++++++++++---------------
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index c503fbd774d0..c45baf681cf5 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -250,6 +250,20 @@ static void mtk_pcie_port_free(struct mtk_pcie_port *port)
struct mtk_pcie *pcie = port->pcie;
struct device *dev = pcie->dev;
+ if (port->irq) {
+ irq_set_chained_handler_and_data(port->irq, NULL, NULL);
+
+ if (port->irq_domain)
+ irq_domain_remove(port->irq_domain);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ if (port->inner_domain)
+ irq_domain_remove(port->inner_domain);
+ }
+
+ irq_dispose_mapping(port->irq);
+ }
+
devm_iounmap(dev, port->base);
list_del(&port->list);
devm_kfree(dev, port);
@@ -531,25 +545,6 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
writel(val, port->base + PCIE_INT_MASK);
}
-static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
-{
- struct mtk_pcie_port *port, *tmp;
-
- list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
- irq_set_chained_handler_and_data(port->irq, NULL, NULL);
-
- if (port->irq_domain)
- irq_domain_remove(port->irq_domain);
-
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- if (port->inner_domain)
- irq_domain_remove(port->inner_domain);
- }
-
- irq_dispose_mapping(port->irq);
- }
-}
-
static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
@@ -1186,8 +1181,6 @@ static void mtk_pcie_remove(struct platform_device *pdev)
pci_remove_root_bus(host->bus);
mtk_pcie_free_resources(pcie);
- mtk_pcie_irq_teardown(pcie);
-
mtk_pcie_put_resources(pcie);
}
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v8 1/3] PCI: mediatek: Use actual physical address instead of virt_to_phys()
From: Manivannan Sadhasivam @ 2026-05-21 5:14 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Caleb James DeLisle, linux-pci, linux-mips, naseefkm, ryder.lee,
lpieralisi, kwilczynski, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Manivannan Sadhasivam
In-Reply-To: <20260520195900.GA86018@bhelgaas>
On Wed, May 20, 2026 at 02:59:00PM -0500, Bjorn Helgaas wrote:
> On Wed, May 20, 2026 at 09:17:35PM +0200, Caleb James DeLisle wrote:
> >
> > On 20/05/2026 20:55, Bjorn Helgaas wrote:
> > > On Wed, May 20, 2026 at 06:38:25PM +0000, Caleb James DeLisle wrote:
> > > > From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > >
> > > > The driver previously used virt_to_phys() on the ioremapped register base
> > > > (port->base) to compute the MSI message address. Using virt_to_phys() on an
> > > > IO mapped address is incorrect because it expects a kernel virtual address.
> > > >
> > > > To fix it, store the physical start of the I/O register region in
> > > > mtk_pcie_port->phys_base and use it to build the MSI address. This replaces
> > > > the incorrect virt_to_phys() usage and ensures MSI addresses are generated
> > > > correctly.
> > > >
> > > > Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > > Tested-by: Caleb James DeLisle <cjd@cjdns.fr>
> > > > ---
> > > > drivers/pci/controller/pcie-mediatek.c | 16 +++++++++++++---
> > > > 1 file changed, 13 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> > > > index 75722524fe74..c503fbd774d0 100644
> > > > --- a/drivers/pci/controller/pcie-mediatek.c
> > > > +++ b/drivers/pci/controller/pcie-mediatek.c
> > > > @@ -175,6 +175,7 @@ struct mtk_pcie_soc {
> > > > /**
> > > > * struct mtk_pcie_port - PCIe port information
> > > > * @base: IO mapped register base
> > > > + * @phys_base: Physical address of the I/O register base region
> > > > * @list: port list
> > > > * @pcie: pointer to PCIe host info
> > > > * @reset: pointer to port reset control
> > > > @@ -196,6 +197,7 @@ struct mtk_pcie_soc {
> > > > */
> > > > struct mtk_pcie_port {
> > > > void __iomem *base;
> > > > + phys_addr_t phys_base;
> > > > struct list_head list;
> > > > struct mtk_pcie *pcie;
> > > > struct reset_control *reset;
> > > > @@ -405,7 +407,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> > > > phys_addr_t addr;
> > > > /* MT2712/MT7622 only support 32-bit MSI addresses */
> > > > - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> > > > + addr = port->phys_base + PCIE_MSI_VECTOR;
> > >
> > > This doesn't look right because the MSI address is a PCI bus address,
> > > and port->phys_base is a CPU physical address. Often a PCI bus
> > > address is the same as the CPU physical address, but not always.
> > > I think the DT 'ranges' property tells you the translation.
>
> Oops, sorry, I muddied the waters here.
>
> 'ranges' tells you the translation applied by a bridge, e.g., when a
> CPU does a load/store, the PCI host bridge turns it into a PCI
> read/write transaction. The bridge might add an offset to the CPU
> load/store physical address to get the PCI read/write bus address.
>
> But that's not the issue here. The MSI is basically a DMA write
> performed by the PCI device, not a store done by a CPU, so I don't
> think 'ranges' is the right thing to look at.
>
Yeah, it is so easy to confuse both. To summarise, 'ranges' describes the
outbound translation and 'dma-ranges' describes the inbound translation from
host perspective.
> Based on this:
> https://elinux.org/Device_Tree_Usage#PCI_DMA_Address_Translation
> I think 'dma-ranges' is the relevant property. I don't think your DT
> includes a 'dma-ranges' property, and in that case the default is that
> the system bus (CPU) address is the same as the PCI address.
>
> So I think this patch works because it assumes DMA addresses like the
> MSI address are mapped to identical system bus addresses.
>
> It still seems to me that drivers should be prepared for the presence
> of dma-ranges and use it when computing the MSI target address. But I
> don't think any drivers really do that, so for now I think you should
> pretend that I never responded about this patch.
>
Your observations are correct. This driver assumes that the identical mapping
exists between CPU and PCI bus addresses. Usually, the drivers make use of
phys_to_dma() to handle the translations. This API internally makes use of the
'dma_range_map' which gets populated by the OF core based on the 'dma-ranges'
property (if present in DT).
But it makes sense to use it irrespective of whether the platform supports
non-identical DMA/inbound translation or not. Since this API behaves like a
no-op and returns the CPU physical address if there is an identical mapping,
there is literally zero overhead in using it.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH] Bluetooth: btmtk: remove extra copy in cmd array init
From: Jiajia Liu @ 2026-05-21 2:26 UTC (permalink / raw)
To: Luiz Augusto von Dentz
Cc: Marcel Holtmann, Matthias Brugger, AngeloGioacchino Del Regno,
linux-bluetooth, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <CABBYNZLLNFNuSv0UBNQ7C2HTTg5W2m41hBTNpPw822GMAVNuhQ@mail.gmail.com>
On Wed, May 20, 2026 at 08:55:46AM -0400, Luiz Augusto von Dentz wrote:
> Hi Jiajia,
>
> On Tue, May 19, 2026 at 10:15 PM Jiajia Liu <liujiajia@kylinos.cn> wrote:
> >
> > In btmtk_setup_firmware_79xx, the data length indicated by wmt_params.dlen
> > in the cmd buffer is MTK_SEC_MAP_NEED_SEND_SIZE + 1. Except for the first
> > byte, the remaining length is MTK_SEC_MAP_NEED_SEND_SIZE. memcpy copied one
> > more byte to cmd + 1 than the remaining length. Align the length passed to
> > memcpy to avoid exceeding current section map.
> >
> > Signed-off-by: Jiajia Liu <liujiajia@kylinos.cn>
> > ---
> > drivers/bluetooth/btmtk.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/bluetooth/btmtk.c b/drivers/bluetooth/btmtk.c
> > index ea7a031000cd..53cba71cb07f 100644
> > --- a/drivers/bluetooth/btmtk.c
> > +++ b/drivers/bluetooth/btmtk.c
> > @@ -188,7 +188,7 @@ int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
> > MTK_FW_ROM_PATCH_GD_SIZE +
> > MTK_FW_ROM_PATCH_SEC_MAP_SIZE * i +
> > MTK_SEC_MAP_COMMON_SIZE,
> > - MTK_SEC_MAP_NEED_SEND_SIZE + 1);
> > + MTK_SEC_MAP_NEED_SEND_SIZE);
> >
> > wmt_params.op = BTMTK_WMT_PATCH_DWNLD;
> > wmt_params.status = &status;
> > --
> > 2.53.0
> >
>
> Have you tested this on the actual hardware? If not we need a Tested-by.
Yes, I have tested with MT7922 (0489:e0d8) on linux 7.1-rc4 applied this patch
and the following two.
Bluetooth: btmtk: accept too short WMT FUNC_CTRL events
Bluetooth: btmtk: fix urb->setup_packet leak in error paths
setup log of boot and rfkill switch:
$ dmesg | grep hci0
[ 6.108240] Bluetooth: hci0: HW/SW Version: 0x008a008a, Build Time: 20260224103448
[ 8.933508] Bluetooth: hci0: Device setup in 2765295 usecs
[ 8.938846] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
[ 57.209143] Bluetooth: hci0: HW/SW Version: 0x008a008a, Build Time: 20260224103448
[ 57.366004] Bluetooth: hci0: Device setup in 160450 usecs
[ 57.371248] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
[ 203.687643] Bluetooth: hci0: HW/SW Version: 0x008a008a, Build Time: 20260224103448
[ 203.844163] Bluetooth: hci0: Device setup in 158989 usecs
[ 203.849426] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
[ 214.723250] Bluetooth: hci0: HW/SW Version: 0x008a008a, Build Time: 20260224103448
[ 214.879380] Bluetooth: hci0: Device setup in 155239 usecs
[ 214.884644] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
>
> --
> Luiz Augusto von Dentz
^ permalink raw reply
* Re: [PATCH 2/2] ASoC: mt8173-max98090: use standard callback to set jack
From: kernel test robot @ 2026-05-20 23:12 UTC (permalink / raw)
To: Srinivas Kandagatla, broonie
Cc: oe-kbuild-all, lgirdwood, perex, tiwai, matthias.bgg,
angelogioacchino.delregno, sharq0406, kuninori.morimoto.gx,
ckeepax, srinivas.kandagatla, linux-sound, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260520132930.54333-3-srinivas.kandagatla@oss.qualcomm.com>
Hi Srinivas,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-sound/for-next]
[also build test WARNING on linus/master v7.1-rc4 next-20260520]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Srinivas-Kandagatla/ASoC-codecs-max98090-use-component-set_jack-callback/20260520-213646
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
patch link: https://lore.kernel.org/r/20260520132930.54333-3-srinivas.kandagatla%40oss.qualcomm.com
patch subject: [PATCH 2/2] ASoC: mt8173-max98090: use standard callback to set jack
config: x86_64-rhel-9.4-ltp (https://download.01.org/0day-ci/archive/20260521/202605210132.USry3Haw-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260521/202605210132.USry3Haw-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202605210132.USry3Haw-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> Warning: sound/soc/codecs/max98090.c:2353 function parameter 'data' not described in 'max98090_set_jack'
>> Warning: sound/soc/codecs/max98090.c:2353 function parameter 'data' not described in 'max98090_set_jack'
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v8 1/3] PCI: mediatek: Use actual physical address instead of virt_to_phys()
From: Bjorn Helgaas @ 2026-05-20 19:59 UTC (permalink / raw)
To: Caleb James DeLisle
Cc: linux-pci, linux-mips, naseefkm, ryder.lee, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Manivannan Sadhasivam
In-Reply-To: <afd47d4b-8309-4025-a40b-29606fed3c50@cjdns.fr>
On Wed, May 20, 2026 at 09:17:35PM +0200, Caleb James DeLisle wrote:
>
> On 20/05/2026 20:55, Bjorn Helgaas wrote:
> > On Wed, May 20, 2026 at 06:38:25PM +0000, Caleb James DeLisle wrote:
> > > From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > >
> > > The driver previously used virt_to_phys() on the ioremapped register base
> > > (port->base) to compute the MSI message address. Using virt_to_phys() on an
> > > IO mapped address is incorrect because it expects a kernel virtual address.
> > >
> > > To fix it, store the physical start of the I/O register region in
> > > mtk_pcie_port->phys_base and use it to build the MSI address. This replaces
> > > the incorrect virt_to_phys() usage and ensures MSI addresses are generated
> > > correctly.
> > >
> > > Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > Tested-by: Caleb James DeLisle <cjd@cjdns.fr>
> > > ---
> > > drivers/pci/controller/pcie-mediatek.c | 16 +++++++++++++---
> > > 1 file changed, 13 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> > > index 75722524fe74..c503fbd774d0 100644
> > > --- a/drivers/pci/controller/pcie-mediatek.c
> > > +++ b/drivers/pci/controller/pcie-mediatek.c
> > > @@ -175,6 +175,7 @@ struct mtk_pcie_soc {
> > > /**
> > > * struct mtk_pcie_port - PCIe port information
> > > * @base: IO mapped register base
> > > + * @phys_base: Physical address of the I/O register base region
> > > * @list: port list
> > > * @pcie: pointer to PCIe host info
> > > * @reset: pointer to port reset control
> > > @@ -196,6 +197,7 @@ struct mtk_pcie_soc {
> > > */
> > > struct mtk_pcie_port {
> > > void __iomem *base;
> > > + phys_addr_t phys_base;
> > > struct list_head list;
> > > struct mtk_pcie *pcie;
> > > struct reset_control *reset;
> > > @@ -405,7 +407,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> > > phys_addr_t addr;
> > > /* MT2712/MT7622 only support 32-bit MSI addresses */
> > > - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> > > + addr = port->phys_base + PCIE_MSI_VECTOR;
> >
> > This doesn't look right because the MSI address is a PCI bus address,
> > and port->phys_base is a CPU physical address. Often a PCI bus
> > address is the same as the CPU physical address, but not always.
> > I think the DT 'ranges' property tells you the translation.
Oops, sorry, I muddied the waters here.
'ranges' tells you the translation applied by a bridge, e.g., when a
CPU does a load/store, the PCI host bridge turns it into a PCI
read/write transaction. The bridge might add an offset to the CPU
load/store physical address to get the PCI read/write bus address.
But that's not the issue here. The MSI is basically a DMA write
performed by the PCI device, not a store done by a CPU, so I don't
think 'ranges' is the right thing to look at.
Based on this:
https://elinux.org/Device_Tree_Usage#PCI_DMA_Address_Translation
I think 'dma-ranges' is the relevant property. I don't think your DT
includes a 'dma-ranges' property, and in that case the default is that
the system bus (CPU) address is the same as the PCI address.
So I think this patch works because it assumes DMA addresses like the
MSI address are mapped to identical system bus addresses.
It still seems to me that drivers should be prepared for the presence
of dma-ranges and use it when computing the MSI target address. But I
don't think any drivers really do that, so for now I think you should
pretend that I never responded about this patch.
> This is all still a little over my head here, but my understanding was that
> this is in the middle of the device's register map because the DT has the
> following:
>
> reg = <0x1fb83000 0x1000>;
> reg-names = "port1";
>
> Per the manual, that offset (base + 0xc0) is in undocumented area but it's
> in the registers.
>
> The PCI memory is 0x20000000 - 0x2fffffff and we split it between the two
> devices. Here's the one using the upper half:
>
> ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>, (IO)
>
> <0x82000000 0 0x28000000 0x28000000 0 0x08000000>; (MEM)
>
> Hope I'm adding something useful here... Let me know if you want me to get
> or test anything else.
Obviously it's over my head too, so I'm sorry I confused the
situation.
> > > msg->address_hi = 0;
> > > msg->address_lo = lower_32_bits(addr);
> > > @@ -520,7 +522,7 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
> > > u32 val;
> > > phys_addr_t msg_addr;
> > > - msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> > > + msg_addr = port->phys_base + PCIE_MSI_VECTOR;
> > > val = lower_32_bits(msg_addr);
> > > writel(val, port->base + PCIE_IMSI_ADDR);
> > > @@ -953,6 +955,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> > > struct mtk_pcie_port *port;
> > > struct device *dev = pcie->dev;
> > > struct platform_device *pdev = to_platform_device(dev);
> > > + struct resource *res;
> > > char name[20];
> > > int err;
> > > @@ -961,7 +964,14 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> > > return -ENOMEM;
> > > snprintf(name, sizeof(name), "port%d", slot);
> > > - port->base = devm_platform_ioremap_resource_byname(pdev, name);
> > > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> > > + if (!res) {
> > > + dev_err(dev, "failed to get port%d base\n", slot);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + port->phys_base = res->start;
> > > + port->base = devm_ioremap_resource(&pdev->dev, res);
> > > if (IS_ERR(port->base)) {
> > > dev_err(dev, "failed to map port%d base\n", slot);
> > > return PTR_ERR(port->base);
> > > --
> > > 2.39.5
> > >
^ permalink raw reply
* Re: [PATCH v8 1/3] PCI: mediatek: Use actual physical address instead of virt_to_phys()
From: Caleb James DeLisle @ 2026-05-20 19:17 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, linux-mips, naseefkm, ryder.lee, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Manivannan Sadhasivam
In-Reply-To: <20260520185534.GA72799@bhelgaas>
On 20/05/2026 20:55, Bjorn Helgaas wrote:
> On Wed, May 20, 2026 at 06:38:25PM +0000, Caleb James DeLisle wrote:
>> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>>
>> The driver previously used virt_to_phys() on the ioremapped register base
>> (port->base) to compute the MSI message address. Using virt_to_phys() on an
>> IO mapped address is incorrect because it expects a kernel virtual address.
>>
>> To fix it, store the physical start of the I/O register region in
>> mtk_pcie_port->phys_base and use it to build the MSI address. This replaces
>> the incorrect virt_to_phys() usage and ensures MSI addresses are generated
>> correctly.
>>
>> Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>> Tested-by: Caleb James DeLisle <cjd@cjdns.fr>
>> ---
>> drivers/pci/controller/pcie-mediatek.c | 16 +++++++++++++---
>> 1 file changed, 13 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
>> index 75722524fe74..c503fbd774d0 100644
>> --- a/drivers/pci/controller/pcie-mediatek.c
>> +++ b/drivers/pci/controller/pcie-mediatek.c
>> @@ -175,6 +175,7 @@ struct mtk_pcie_soc {
>> /**
>> * struct mtk_pcie_port - PCIe port information
>> * @base: IO mapped register base
>> + * @phys_base: Physical address of the I/O register base region
>> * @list: port list
>> * @pcie: pointer to PCIe host info
>> * @reset: pointer to port reset control
>> @@ -196,6 +197,7 @@ struct mtk_pcie_soc {
>> */
>> struct mtk_pcie_port {
>> void __iomem *base;
>> + phys_addr_t phys_base;
>> struct list_head list;
>> struct mtk_pcie *pcie;
>> struct reset_control *reset;
>> @@ -405,7 +407,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
>> phys_addr_t addr;
>>
>> /* MT2712/MT7622 only support 32-bit MSI addresses */
>> - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
>> + addr = port->phys_base + PCIE_MSI_VECTOR;
> This doesn't look right because the MSI address is a PCI bus address,
> and port->phys_base is a CPU physical address. Often a PCI bus
> address is the same as the CPU physical address, but not always.
> I think the DT 'ranges' property tells you the translation.
This is all still a little over my head here, but my understanding was
that this is in the middle of the device's register map because the DT
has the following:
reg = <0x1fb83000 0x1000>;
reg-names = "port1";
Per the manual, that offset (base + 0xc0) is in undocumented area but
it's in the registers.
The PCI memory is 0x20000000 - 0x2fffffff and we split it between the
two devices. Here's the one using the upper half:
ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>, (IO)
<0x82000000 0 0x28000000 0x28000000 0 0x08000000>; (MEM)
Hope I'm adding something useful here... Let me know if you want me to
get or test anything else.
Thanks,
Caleb
>> msg->address_hi = 0;
>> msg->address_lo = lower_32_bits(addr);
>>
>> @@ -520,7 +522,7 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
>> u32 val;
>> phys_addr_t msg_addr;
>>
>> - msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
>> + msg_addr = port->phys_base + PCIE_MSI_VECTOR;
>> val = lower_32_bits(msg_addr);
>> writel(val, port->base + PCIE_IMSI_ADDR);
>>
>> @@ -953,6 +955,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
>> struct mtk_pcie_port *port;
>> struct device *dev = pcie->dev;
>> struct platform_device *pdev = to_platform_device(dev);
>> + struct resource *res;
>> char name[20];
>> int err;
>>
>> @@ -961,7 +964,14 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
>> return -ENOMEM;
>>
>> snprintf(name, sizeof(name), "port%d", slot);
>> - port->base = devm_platform_ioremap_resource_byname(pdev, name);
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
>> + if (!res) {
>> + dev_err(dev, "failed to get port%d base\n", slot);
>> + return -EINVAL;
>> + }
>> +
>> + port->phys_base = res->start;
>> + port->base = devm_ioremap_resource(&pdev->dev, res);
>> if (IS_ERR(port->base)) {
>> dev_err(dev, "failed to map port%d base\n", slot);
>> return PTR_ERR(port->base);
>> --
>> 2.39.5
>>
^ permalink raw reply
* Re: [PATCH v8 1/3] PCI: mediatek: Use actual physical address instead of virt_to_phys()
From: Bjorn Helgaas @ 2026-05-20 18:55 UTC (permalink / raw)
To: Caleb James DeLisle
Cc: linux-pci, linux-mips, naseefkm, ryder.lee, lpieralisi,
kwilczynski, mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Manivannan Sadhasivam
In-Reply-To: <20260520183827.908243-2-cjd@cjdns.fr>
On Wed, May 20, 2026 at 06:38:25PM +0000, Caleb James DeLisle wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>
> The driver previously used virt_to_phys() on the ioremapped register base
> (port->base) to compute the MSI message address. Using virt_to_phys() on an
> IO mapped address is incorrect because it expects a kernel virtual address.
>
> To fix it, store the physical start of the I/O register region in
> mtk_pcie_port->phys_base and use it to build the MSI address. This replaces
> the incorrect virt_to_phys() usage and ensures MSI addresses are generated
> correctly.
>
> Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> Tested-by: Caleb James DeLisle <cjd@cjdns.fr>
> ---
> drivers/pci/controller/pcie-mediatek.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index 75722524fe74..c503fbd774d0 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -175,6 +175,7 @@ struct mtk_pcie_soc {
> /**
> * struct mtk_pcie_port - PCIe port information
> * @base: IO mapped register base
> + * @phys_base: Physical address of the I/O register base region
> * @list: port list
> * @pcie: pointer to PCIe host info
> * @reset: pointer to port reset control
> @@ -196,6 +197,7 @@ struct mtk_pcie_soc {
> */
> struct mtk_pcie_port {
> void __iomem *base;
> + phys_addr_t phys_base;
> struct list_head list;
> struct mtk_pcie *pcie;
> struct reset_control *reset;
> @@ -405,7 +407,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> phys_addr_t addr;
>
> /* MT2712/MT7622 only support 32-bit MSI addresses */
> - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> + addr = port->phys_base + PCIE_MSI_VECTOR;
This doesn't look right because the MSI address is a PCI bus address,
and port->phys_base is a CPU physical address. Often a PCI bus
address is the same as the CPU physical address, but not always.
I think the DT 'ranges' property tells you the translation.
> msg->address_hi = 0;
> msg->address_lo = lower_32_bits(addr);
>
> @@ -520,7 +522,7 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
> u32 val;
> phys_addr_t msg_addr;
>
> - msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> + msg_addr = port->phys_base + PCIE_MSI_VECTOR;
> val = lower_32_bits(msg_addr);
> writel(val, port->base + PCIE_IMSI_ADDR);
>
> @@ -953,6 +955,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> struct mtk_pcie_port *port;
> struct device *dev = pcie->dev;
> struct platform_device *pdev = to_platform_device(dev);
> + struct resource *res;
> char name[20];
> int err;
>
> @@ -961,7 +964,14 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> return -ENOMEM;
>
> snprintf(name, sizeof(name), "port%d", slot);
> - port->base = devm_platform_ioremap_resource_byname(pdev, name);
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> + if (!res) {
> + dev_err(dev, "failed to get port%d base\n", slot);
> + return -EINVAL;
> + }
> +
> + port->phys_base = res->start;
> + port->base = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(port->base)) {
> dev_err(dev, "failed to map port%d base\n", slot);
> return PTR_ERR(port->base);
> --
> 2.39.5
>
^ permalink raw reply
* [PATCH v8 3/3] PCI: mediatek: Add support for EcoNet EN7528 SoC
From: Caleb James DeLisle @ 2026-05-20 18:38 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Caleb James DeLisle
In-Reply-To: <20260520183827.908243-1-cjd@cjdns.fr>
Add support for the PCIe present on the EcoNet EN7528 (and EN751221) SoCs.
These SoCs have a mix of Gen1 and Gen2 capable ports, but the Gen2 ports
require re-training after startup.
Co-developed-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-mediatek.c | 152 +++++++++++++++++++++++++
2 files changed, 153 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 2247709ef6d6..8a3a31b2bc12 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -209,7 +209,7 @@ config PCI_MVEBU
config PCIE_MEDIATEK
tristate "MediaTek PCIe controller"
- depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
+ depends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST
depends on OF
depends on PCI_MSI
select IRQ_MSI_LIB
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index c503fbd774d0..4e4d4b1559f7 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -9,11 +9,13 @@
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/errno.h>
#include <linux/iopoll.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/irq-msi-lib.h>
#include <linux/irqdomain.h>
+#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/msi.h>
@@ -77,6 +79,7 @@
#define PCIE_CONF_VEND_ID 0x100
#define PCIE_CONF_DEVICE_ID 0x102
+#define PCIE_CONF_REV_CLASS 0x104
#define PCIE_CONF_CLASS_ID 0x106
#define PCIE_INT_MASK 0x420
@@ -89,6 +92,11 @@
#define MSI_MASK BIT(23)
#define MTK_MSI_IRQS_NUM 32
+#define EN7528_HOST_MODE 0x00804201
+#define EN7528_LINKUP_REG 0x50
+#define EN7528_RC0_LINKUP BIT(1)
+#define EN7528_RC1_LINKUP BIT(2)
+
#define PCIE_AHB_TRANS_BASE0_L 0x438
#define PCIE_AHB_TRANS_BASE0_H 0x43c
#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
@@ -148,12 +156,15 @@ struct mtk_pcie_port;
* @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed
* @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external block
* @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe
+ * @MTK_PCIE_RETRAIN: Retrain link to bridge after startup because some
+ * Gen2-capable devices start as Gen1.
*/
enum mtk_pcie_quirks {
MTK_PCIE_FIX_CLASS_ID = BIT(0),
MTK_PCIE_FIX_DEVICE_ID = BIT(1),
MTK_PCIE_NO_MSI = BIT(2),
MTK_PCIE_SKIP_RSTB = BIT(3),
+ MTK_PCIE_RETRAIN = BIT(4),
};
/**
@@ -755,6 +766,132 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
return 0;
}
+static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port)
+{
+ struct mtk_pcie *pcie = port->pcie;
+ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
+ struct resource *mem = NULL;
+ struct resource_entry *entry;
+ u32 val, link_mask;
+ int err;
+
+ entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
+ if (entry)
+ mem = entry->res;
+ if (!mem)
+ return -EINVAL;
+
+ if (!pcie->cfg) {
+ dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n");
+ return -EINVAL;
+ }
+
+ /* Assert all reset signals */
+ writel(0, port->base + PCIE_RST_CTRL);
+
+ /*
+ * Enable PCIe link down reset, if link status changed from link up to
+ * link down, this will reset MAC control registers and configuration
+ * space.
+ */
+ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
+
+ msleep(PCIE_T_PVPERL_MS);
+
+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
+ val = readl(port->base + PCIE_RST_CTRL);
+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
+ PCIE_MAC_SRSTB | PCIE_CRSTB;
+ writel(val, port->base + PCIE_RST_CTRL);
+
+ writel(PCIE_CLASS_CODE | PCIE_REVISION_ID,
+ port->base + PCIE_CONF_REV_CLASS);
+ writel(EN7528_HOST_MODE, port->base);
+
+ link_mask = (port->slot == 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINKUP;
+
+ /* 100ms timeout value should be enough for Gen1/2 training */
+ err = regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val,
+ !!(val & link_mask), 20,
+ PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
+ if (err) {
+ dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot);
+ return -ETIMEDOUT;
+ }
+
+ /* Activate INTx interrupts */
+ val = readl(port->base + PCIE_INT_MASK);
+ val &= ~INTX_MASK;
+ writel(val, port->base + PCIE_INT_MASK);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ mtk_pcie_enable_msi(port);
+
+ /* Set AHB to PCIe translation windows */
+ val = lower_32_bits(mem->start) |
+ AHB2PCIE_SIZE(fls(resource_size(mem)));
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
+
+ val = upper_32_bits(mem->start);
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
+
+ writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0);
+
+ if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK))
+ dev_info(pcie->dev,
+ "module not built-in, Gen2 unavailable even if supported\n");
+
+ return 0;
+}
+
+/**
+ * mtk_pcie_retrain - retrain the root bridge link if needed
+ * @dev: The device, for use in logging
+ * @host: The host bridge which contains the link
+ *
+ * Due to what is likely a hardware bug, some devices (notably EcoNet) start up
+ * as Gen1, and must be retrained once after initial configuration in order to
+ * reach Gen2.
+ *
+ * These devices always self-identify as Gen2 capable, but sometimes the PHY is
+ * only capable of Gen1 operation, and sometimes the PCIe card (e.g. wifi) is
+ * only Gen1 capable. Therefore it is most convenient to retrain every port
+ * after startup.
+ */
+static int mtk_pcie_retrain(struct device *dev, struct pci_host_bridge *host)
+{
+ struct pci_dev *rp;
+ int ret = -ENOENT;
+ u16 lnksta = 0;
+ u32 speed;
+
+ /* Should already have been warned about during startup_port */
+ if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK))
+ return 0;
+
+ for_each_pci_bridge(rp, host->bus) {
+ if (pci_pcie_type(rp) != PCI_EXP_TYPE_ROOT_PORT)
+ continue;
+
+#if IS_BUILTIN(CONFIG_PCIE_MEDIATEK)
+ ret = pcie_retrain_link(rp, true);
+#endif
+
+ if (ret)
+ return dev_err_probe(&rp->dev, ret,
+ "failed to retrain port\n");
+
+ pcie_capability_read_word(rp, PCI_EXP_LNKSTA, &lnksta);
+ speed = lnksta & PCI_EXP_LNKSTA_CLS;
+
+ pci_info(rp, "link retrained, speed %s\n",
+ pci_speed_string(pcie_link_speed[speed]));
+
+ }
+
+ return 0;
+}
+
static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
@@ -1159,6 +1296,13 @@ static int mtk_pcie_probe(struct platform_device *pdev)
if (err)
goto put_resources;
+ /*
+ * Ignore error because pci_host_probe() was already called, and in any
+ * case it is possible that the port will still work as Gen1.
+ */
+ if (pcie->soc->quirks & MTK_PCIE_RETRAIN)
+ mtk_pcie_retrain(dev, host);
+
return 0;
put_resources:
@@ -1274,8 +1418,16 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
.quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID,
};
+static const struct mtk_pcie_soc mtk_pcie_soc_en7528 = {
+ .ops = &mtk_pcie_ops_v2,
+ .startup = mtk_pcie_startup_port_en7528,
+ .setup_irq = mtk_pcie_setup_irq,
+ .quirks = MTK_PCIE_RETRAIN,
+};
+
static const struct of_device_id mtk_pcie_ids[] = {
{ .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 },
+ { .compatible = "econet,en7528-pcie", .data = &mtk_pcie_soc_en7528 },
{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
--
2.39.5
^ permalink raw reply related
* [PATCH v8 1/3] PCI: mediatek: Use actual physical address instead of virt_to_phys()
From: Caleb James DeLisle @ 2026-05-20 18:38 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Manivannan Sadhasivam, Caleb James DeLisle
In-Reply-To: <20260520183827.908243-1-cjd@cjdns.fr>
From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
The driver previously used virt_to_phys() on the ioremapped register base
(port->base) to compute the MSI message address. Using virt_to_phys() on an
IO mapped address is incorrect because it expects a kernel virtual address.
To fix it, store the physical start of the I/O register region in
mtk_pcie_port->phys_base and use it to build the MSI address. This replaces
the incorrect virt_to_phys() usage and ensures MSI addresses are generated
correctly.
Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Tested-by: Caleb James DeLisle <cjd@cjdns.fr>
---
drivers/pci/controller/pcie-mediatek.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 75722524fe74..c503fbd774d0 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -175,6 +175,7 @@ struct mtk_pcie_soc {
/**
* struct mtk_pcie_port - PCIe port information
* @base: IO mapped register base
+ * @phys_base: Physical address of the I/O register base region
* @list: port list
* @pcie: pointer to PCIe host info
* @reset: pointer to port reset control
@@ -196,6 +197,7 @@ struct mtk_pcie_soc {
*/
struct mtk_pcie_port {
void __iomem *base;
+ phys_addr_t phys_base;
struct list_head list;
struct mtk_pcie *pcie;
struct reset_control *reset;
@@ -405,7 +407,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
phys_addr_t addr;
/* MT2712/MT7622 only support 32-bit MSI addresses */
- addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
+ addr = port->phys_base + PCIE_MSI_VECTOR;
msg->address_hi = 0;
msg->address_lo = lower_32_bits(addr);
@@ -520,7 +522,7 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
u32 val;
phys_addr_t msg_addr;
- msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
+ msg_addr = port->phys_base + PCIE_MSI_VECTOR;
val = lower_32_bits(msg_addr);
writel(val, port->base + PCIE_IMSI_ADDR);
@@ -953,6 +955,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
struct mtk_pcie_port *port;
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
+ struct resource *res;
char name[20];
int err;
@@ -961,7 +964,14 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
return -ENOMEM;
snprintf(name, sizeof(name), "port%d", slot);
- port->base = devm_platform_ioremap_resource_byname(pdev, name);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+ if (!res) {
+ dev_err(dev, "failed to get port%d base\n", slot);
+ return -EINVAL;
+ }
+
+ port->phys_base = res->start;
+ port->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(port->base)) {
dev_err(dev, "failed to map port%d base\n", slot);
return PTR_ERR(port->base);
--
2.39.5
^ permalink raw reply related
* [PATCH v8 2/3] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528
From: Caleb James DeLisle @ 2026-05-20 18:38 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Caleb James DeLisle, Conor Dooley
In-Reply-To: <20260520183827.908243-1-cjd@cjdns.fr>
Introduce EcoNet EN7528 SoC compatible in MediaTek PCIe controller
binding.
EcoNet PCIe controller has the same configuration model as
Mediatek v2 but is initialized more similarly to an MT7621
PCIe.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/pci/mediatek-pcie.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
index 0b8c78ec4f91..c009a7a52bc6 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
@@ -14,6 +14,7 @@ properties:
oneOf:
- enum:
- airoha,an7583-pcie
+ - econet,en7528-pcie
- mediatek,mt2712-pcie
- mediatek,mt7622-pcie
- mediatek,mt7629-pcie
@@ -226,6 +227,31 @@ allOf:
mediatek,pbus-csr: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: econet,en7528-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ resets: false
+
+ reset-names: false
+
+ power-domains: false
+
+ mediatek,pbus-csr: false
+
+ required:
+ - phys
+ - phy-names
+
unevaluatedProperties: false
examples:
--
2.39.5
^ permalink raw reply related
* [PATCH v8 0/3] Add EcoNet EN7528 (and EN751221) PCIe support.
From: Caleb James DeLisle @ 2026-05-20 18:38 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Caleb James DeLisle
Tested on SmartFiber XP8421-B (EN751221)
Changes from v7:
* mtk_pcie_retrain retrain all root ports not just first
* Include fix from Manivannan Sadhasivam, wrong usage of virt_to_phys()
Changes from v6:
* s/reset/resets/ in .yaml
* s/re-train/retrain/g
* s/Root bridge/Root port/
* If module not builtin, log at mtk_pcie_startup_port_en7528()
* Do not fail if error in mtk_pcie_retrain()
* v6: https://lore.kernel.org/linux-mips/20260513191652.3200607-1-cjd@cjdns.fr
Changes from v5:
* s/errno-base.h/errno.h/
* Breakout mtk_pcie_retrain() into a function
* Use for_each_pci_bridge() to find root bridge
* v5: https://lore.kernel.org/linux-mips/20260413140339.16238-1-cjd@cjdns.fr/
Changes from v4:
* Fixed missing Acked-by
* Rebased to commit 66672af7a095 ("Add linux-next specific files for 20260410")
* v4: https://lore.kernel.org/linux-mips/20260404182854.2183651-1-cjd@cjdns.fr/
Changes from v3:
* s/initiallized/initialized/
* Use PCIE_T_PVPERL_MS for sleep time
* Use PCI_PM_D3COLD_WAIT for startup wait time
* Clarify comment "Activate INTx interrupts"
* Add MTK_PCIE_RETRAIN quirk for devices which require link re-train
* Do not retrain *all* bridges, only root bridge
* Better comments and logging in retraining logic
* v3: https://lore.kernel.org/linux-mips/20260320094212.696671-1-cjd@cjdns.fr/
Changes from v2:
* mediatek-pcie.yaml -> s/power-domain/power-domains/ and drop example
* Patch 3 dropped as it has been applied (Thanks!)
* v2: https://lore.kernel.org/linux-mips/20260316155157.679533-1-cjd@cjdns.fr/
Changes from v1:
* mediatek-pcie.yaml slot0 needs device-type = "pci", fix dt_binding_check
Link: https://lore.kernel.org/linux-mips/177334026016.3889069.9474337544951486443.robh@kernel.org
* v1: https://lore.kernel.org/linux-mips/20260312165332.569772-1-cjd@cjdns.fr/
This was split from a larger PCIe patchset which crossed multiple
subsystems. I'm not labeling this a v3 because it's a new patchset, but
I'm keeping the historical record anyway.
Changes from econet-pcie v2:
* mediatek-pcie.yaml add missing constraints to PCI node properties
* econet-pcie v2: https://lore.kernel.org/linux-mips/20260309131818.74467-1-cjd@cjdns.fr
Changes from econet-pcie v1:
* pcie-mediatek.c Exclude pcie_retrain_link() when building as a module
* econet-pcie v1: https://lore.kernel.org/linux-mips/20260303190948.694783-1-cjd@cjdns.fr/
Caleb James DeLisle (2):
dt-bindings: PCI: mediatek: Add support for EcoNet EN7528
PCI: mediatek: Add support for EcoNet EN7528 SoC
Manivannan Sadhasivam (1):
PCI: mediatek: Use actual physical address instead of virt_to_phys()
.../bindings/pci/mediatek-pcie.yaml | 26 +++
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-mediatek.c | 168 +++++++++++++++++-
3 files changed, 192 insertions(+), 4 deletions(-)
base-commit: 687da68900cd1a46549f7d9430c7d40346cb86a0
--
2.39.5
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox