* Re: [RFC PATCH net] netfilter: flowtable: fix offloaded ct timeout never being extended
From: Florian Westphal @ 2026-05-27 7:34 UTC (permalink / raw)
To: Adrian Bente
Cc: pablo, netfilter-devel, phil, nbd, sean.wang, lorenzo,
andrew+netdev, matthias.bgg, angelogioacchino.delregno, daniel,
coreteam, linux-mediatek
In-Reply-To: <20260526060138.3924-1-adibente@gmail.com>
Adrian Bente <adibente@gmail.com> wrote:
[ trimming CCs .. ]
> OpenWrt has recently migrated many platforms to kernel 6.18. On the
> MediaTek platform, which supports hardware network offloading, WiFi
> connections accelerated via the WED path were observed to drop after
> roughly 300 seconds.
>
> After several debugging sessions, assisted by the Claude LLM, the
> problem was narrowed down as follows:
>
> nf_flow_table_extend_ct_timeout() extends ct->timeout for offloaded
> flows using:
>
> cmpxchg(&ct->timeout, expires, new_timeout);
>
> 'expires' comes from nf_ct_expires(ct) and is a relative value, while
> ct->timeout holds an absolute timestamp. The two are never equal, so
> the cmpxchg always fails and the timeout is never extended.
>
> This goes unnoticed for most flows, but a long-lived hardware (WED)
> offloaded flow on MediaTek MT7986 eventually has ct->timeout decay to
> zero, the conntrack entry is reaped and the connection breaks.
>
> Compare against the current ct->timeout value instead.
>
> This patch is sent as RFC: the diagnosis is verified on hardware and
> the fix resolves the drop, but review of the chosen approach is
> welcome.
I guess we need to open-code expires, something like this (not even
compile tested). Also see https://sashiko.dev/#/patchset/20260526060138.3924-1-adibente%40gmail.com
diff --git a/net/netfilter/nf_flow_table_core.c b/net/netfilter/nf_flow_table_core.c
--- a/net/netfilter/nf_flow_table_core.c
+++ b/net/netfilter/nf_flow_table_core.c
@@ -506,7 +506,12 @@ static u32 nf_flow_table_tcp_timeout(const struct nf_conn *ct)
static void nf_flow_table_extend_ct_timeout(struct nf_conn *ct)
{
static const u32 min_timeout = 5 * 60 * HZ;
- u32 expires = nf_ct_expires(ct);
+ u32 ct_timeout = READ_ONCE(ct->timeout);
+ s32 expires;
+
+ expires = ct_timeout - nfct_time_stamp;
+ if (expires <= 0) /* already expired */
+ return;
/* normal case: large enough timeout, nothing to do. */
if (likely(expires >= min_timeout))
@@ -524,7 +529,7 @@ static void nf_flow_table_extend_ct_timeout(struct nf_conn *ct)
if (nf_ct_is_confirmed(ct) &&
test_bit(IPS_OFFLOAD_BIT, &ct->status)) {
u8 l4proto = nf_ct_protonum(ct);
- u32 new_timeout = true;
+ u32 new_timeout = 1;
switch (l4proto) {
case IPPROTO_UDP:
@@ -549,7 +554,7 @@ static void nf_flow_table_extend_ct_timeout(struct nf_conn *ct)
*/
if (new_timeout) {
new_timeout += nfct_time_stamp;
- cmpxchg(&ct->timeout, expires, new_timeout);
+ cmpxchg(&ct->timeout, ct_timeout, new_timeout);
}
}
^ permalink raw reply
* Re: [PATCH RFC 00/12] Add support for DisplayPort link training information report
From: Manasi Navare @ 2026-05-27 7:24 UTC (permalink / raw)
To: Jani Nikula
Cc: Kory Maincent, Dmitry Baryshkov, Ville Syrjälä,
Rodrigo Vivi, Joonas Lahtinen, Tvrtko Ursulin, David Airlie,
Simona Vetter, Dave Airlie, Jesse Barnes, Eric Anholt,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Chun-Kuang Hu, Philipp Zabel,
Matthias Brugger, AngeloGioacchino Del Regno, Chris Wilson,
Thomas Petazzoni, Mark Yacoub, Sean Paul, Louis Chauvet,
intel-gfx, intel-xe, dri-devel, linux-kernel, linux-mediatek,
linux-arm-kernel, Simona Vetter
In-Reply-To: <3698b69f20481ff9c6fb1002b46f9862a1fdd03d@intel.com>
Thank you Jani and Ville and others for your feedback on this approach.
I think adding the current negotiated link rate , lane count and DSC
status as part of a connector property is a great
way to standardize this instead of every driver adding a debugfs for
this same information.
Please find my comments for why OS would use this information as below:
On Mon, Apr 13, 2026 at 6:30 AM Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Mon, 13 Apr 2026, Kory Maincent <kory.maincent@bootlin.com> wrote:
> > On Fri, 10 Apr 2026 00:36:09 +0300
> > Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >
> >> On Thu, Apr 09, 2026 at 11:36:21PM +0300, Ville Syrjälä wrote:
> >> > On Thu, Apr 09, 2026 at 07:08:16PM +0200, Kory Maincent wrote:
> >> > > DisplayPort link training negotiates the physical-layer parameters needed
> >> > > for a reliable connection: lane count, link rate, voltage swing,
> >> > > pre-emphasis, and optionally Display Stream Compression (DSC). Currently,
> >> > > each driver exposes this state in its own way, often through
> >> > > driver-specific debugfs entries, with no standard interface for userspace
> >> > > diagnostic and monitoring tools.
> >> > >
> >> > > This series introduces a generic, DRM-managed framework for exposing DP
> >> > > link training state as standard connector properties, modeled after the
> >> > > existing HDMI helper drmm_connector_hdmi_init().
> >> > >
> >> > > The new drmm_connector_dp_init() helper initializes a DP connector and
> >> > > registers the following connector properties to expose the negotiated link
> >> > > state to userspace:
> >> > >
> >> > > - num_lanes: negotiated lane count (1, 2 or 4)
> >> > > - link_rate: negotiated link rate
> >> > > - dsc_en: whether Display Stream Compression is active
> >> > > - voltage_swingN: per-lane voltage swing level (lanes 0-3)
> >> > > - pre_emphasisN: per-lane pre-emphasis level (lanes 0-3)
> >> >
> >> > I don't see why any real userspace would be interested in those (apart
> >> > from maybe DSC). If this is just for diagnostics and whatnot then I
> >> > think sysfs/debugfs could be a better fit.
> >>
> >> I'd agree here. Please consider implementing it as a debugfs interface,
> >> possibly reusing the Intel's format.
> >
> > Sorry, I completely forgot to include a paragraph explaining the rationale
> > behind using DRM properties.
> >
> > This DisplayPort link information report was requested by OSes to allow them to
> > assess the capabilities of each DisplayPort connector on the system, and to
> > guide users from the most to least capable ones. It will also enable the OS to
> > warn the user when a cable is too long or experiencing noise (indicated by high
> > voltage swing and pre-emphasis levels).
>
> The selection of the number of lanes or link rate are at the discretion
> of the driver, or link policy manager in DP spec terms. It does not
> really convey the capabilities of the *connectors* but rather the
> current *link*. Ditto for enabling DSC.
I agree that it would be up to each driver to have a policy
on choosing link rate/lane count and when to enable DSC and then if it fails
fallback to lower link rate/lane count as per the VESA spec.
Currently this information is only available through a debugfs and not standard
across the drivers. However adding it as part of the connector property would
be useful for the userspace, such as DRM HWC to use this information along
with the link status property to understand the reason for reduced
resolutions/modes
exposed to userspace. This can be used to provide better diagnostics and useful
information up to the end user.
DSC being enabled or not or what was the final negotiated link rate
and lane count
could be used to take smarter mode configuration handling choices in
the usersapce
For example for MST, if usersapce can know the negotiated link parameters
usersapce can be smarter in choosing resolutions on each of the downstream sinks
based on the total link bandwidth between source and the hub.
At the end it just helps the OSs to provide better control to the user
in certain scenarios.
I agree that Voltage swing and pre emphasis values can be removed and we
can focus on adding property for link rate, lane count and dsc info
like enabled/disabled, compressed bpp etc.
Regards
Manasi
>
> I don't think the voltage swing and pre-emphasis are really diagnostic
> measures either, but a response to measuring and adapting to the
> link. And if the link training failed, the driver may have already
> reduced the number of lanes and link rate to compensate. So you could
> appear to have the perfect link only because it was so bad at high link
> rate that it was reduced already.
>
> The policies may also vary from driver to driver, and possibly depending
> on what makes sense for the hardware (e.g. power consumption with or
> without DSC).
>
> I think "link information report ... requested by OSs" is vague, and I
> don't think the concept has been completely thought through. I can't see
> how you could present reliable and actionable information to the user
> with what the patch at hand provides. Or how it could work in a generic
> manner across drivers.
>
> Overall sounds like an XY problem [1]. We should focus on what you're
> trying to achieve first, in userspace, and only then think about what
> the appropriate kernel mechanism should be.
>
> I don't think this is it.
>
>
> BR,
> Jani.
>
>
> [1] https://en.wikipedia.org/wiki/XY_problem
>
>
> >
> > Since this is information that OSes will consume on a regular basis, exposing
> > it directly as DRM properties seems the most appropriate approach.
>
>
>
>
>
> --
> Jani Nikula, Intel
^ permalink raw reply
* Re: [PATCH wireless-next] wifi: mt76: mt7925: add Netgear A8500 USB device ID
From: Sean Wang @ 2026-05-27 6:04 UTC (permalink / raw)
To: Lucid Duck
Cc: nbd, lorenzo.bianconi, sean.wang, linux-wireless, linux-mediatek,
morrownr, stable
In-Reply-To: <20260326190346.415226-1-lucid_duck@justthetip.ca>
Hi Devin,
On Thu, Mar 26, 2026 at 2:07 PM Lucid Duck <lucid_duck@justthetip.ca> wrote:
>
> Add USB device ID for the Netgear A8500 (0846:9050) which uses
> the mt7925 chipset.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Lucid Duck <lucid_duck@justthetip.ca>
Sorry for the late reply.
I ran checkpatch.pl on the patch and got the following warning:
WARNING: The commit message has 'stable@', perhaps it also needs a 'Fixes:' tag?
Could you please send a v2 that drops the Cc: stable tag and uses:
Signed-off-by: Devin Wittmayer <lucid_duck@justthetip.ca>
to keep it consistent with the other patches you sent?
Thanks.
> ---
> drivers/net/wireless/mediatek/mt76/mt7925/usb.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/usb.c b/drivers/net/wireless/mediatek/mt76/mt7925/usb.c
> index d9968f038..e44f0cafd 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/usb.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/usb.c
> @@ -12,6 +12,9 @@
> static const struct usb_device_id mt7925u_device_table[] = {
> { USB_DEVICE_AND_INTERFACE_INFO(0x0e8d, 0x7925, 0xff, 0xff, 0xff),
> .driver_info = (kernel_ulong_t)MT7925_FIRMWARE_WM },
> + /* Netgear, Inc. A8500 */
> + { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9050, 0xff, 0xff, 0xff),
> + .driver_info = (kernel_ulong_t)MT7925_FIRMWARE_WM },
> /* Netgear, Inc. A9000 */
> { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9072, 0xff, 0xff, 0xff),
> .driver_info = (kernel_ulong_t)MT7925_FIRMWARE_WM },
> --
> 2.53.0
>
>
^ permalink raw reply
* [PATCH v3] wifi: mt76: mt7921: fix resource leak in probe error path
From: Hongling Zeng @ 2026-05-27 5:35 UTC (permalink / raw)
To: nbd, lorenzo, ryder.lee, shayne.chen, sean.wang, matthias.bgg,
angelogioacchino.delregno, xiong.huang, madhurkumar004
Cc: linux-wireless, linux-kernel, linux-arm-kernel, linux-mediatek,
zhongling0719, Hongling Zeng
When pcim_iomap_region() or devm_kmemdup() fail, the code returns
directly without cleaning up previously allocated resources:
- mt76_device allocated by mt76_alloc_device()
- pci irq vectors allocated by pci_alloc_irq_vectors()
Fix this by jumping to the existing error cleanup path instead of
returning directly.
To avoid using an uninitialized variable in the error path, move the
dev initialization before the error checks.
Fixes: ee5bb35d2b83 ("wifi: mt76: mt7921: Replace deprecated PCI function")
Fixes: 222606f43b58 ("wifi: mt76: mt7921: handle MT7902 irq_map quirk with mutable copy")
Signed-off-by: Hongling Zeng <zenghongling@kylinos.cn>
---
Change in v3
- Fix incorrect Fixes: tag as pointed out by Sean
- Correct tag from unrelated phy/ti-pipe3 commit to the actual mt76 commit
that introduced the resource leak
---
drivers/net/wireless/mediatek/mt76/mt7921/pci.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
index 7a790ddf43bb..49a37185f056 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
@@ -343,11 +343,14 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
pci_set_drvdata(pdev, mdev);
+ dev = container_of(mdev, struct mt792x_dev, mt76);
+
regs = pcim_iomap_region(pdev, 0, pci_name(pdev));
- if (IS_ERR(regs))
- return PTR_ERR(regs);
+ if (IS_ERR(regs)) {
+ ret = PTR_ERR(regs);
+ goto err_free_dev;
+ }
- dev = container_of(mdev, struct mt792x_dev, mt76);
dev->fw_features = features;
dev->hif_ops = &mt7921_pcie_ops;
dev->irq_map = &irq_map;
@@ -359,8 +362,10 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
/* MT7902 needs a mutable copy because wm2_complete_mask differs */
map = devm_kmemdup(&pdev->dev, &irq_map,
sizeof(irq_map), GFP_KERNEL);
- if (!map)
- return -ENOMEM;
+ if (!map) {
+ ret = -ENOMEM;
+ goto err_free_dev;
+ }
map->rx.wm2_complete_mask = 0;
dev->irq_map = map;
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v2] wifi: mt76: mt7921: fix resource leak in probe error path
From: Hongling Zeng @ 2026-05-27 5:35 UTC (permalink / raw)
To: Sean Wang, Hongling Zeng
Cc: nbd, lorenzo, ryder.lee, shayne.chen, sean.wang, matthias.bgg,
angelogioacchino.delregno, xiong.huang, madhurkumar004,
linux-wireless, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <CAGp9LzruaD57tE5XHHAM8mKoPc-JQSAcaTdgvdSfESJjz-9XnA@mail.gmail.com>
Hi Sean,
Thanks for the review! You're absolutely right about the incorrect
Fixes: tag.
Here's v3 with the correct Fixes tags pointing to the actual commits that
introduced the resource leaks:
- ee5bb35d2b83 introduced the pcim_iomap_region() direct return
- 222606f43b58 introduced the devm_kmemdup() direct return
Thanks again for catching that.
Regards,
Hongling
在 2026年05月27日 12:48, Sean Wang 写道:
> Hi,
>
> On Tue, May 26, 2026 at 10:44 PM Hongling Zeng <zenghongling@kylinos.cn> wrote:
>> When pcim_iomap_region() or devm_kmemdup() fail, the code returns
>> directly without cleaning up previously allocated resources:
>> - mt76_device allocated by mt76_alloc_device()
>> - pci irq vectors allocated by pci_alloc_irq_vectors()
>> Fix this by jumping to the existing error cleanup path instead of
>> returning directly.
>>
>> To avoid using an uninitialized variable in the error path, move the
>> dev initialization before the error checks.
>>
>> Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
>> Signed-off-by: Hongling Zeng <zenghongling@kylinos.cn>
>>
> The code change itself looks correct, but commit message Fixes: tag is wrong.
>
> It points to 234738ea3390 ("phy: ti-pipe3: move clk initialization to
> a separate function"), which is unrelated to mt76/mt7921.
>
> The two direct-return leaks appear to come from:
> - ee5bb35d2b83 ("wifi: mt76: mt7921: Replace deprecated PCI
> function") for the pcim_iomap_region() path.
> - 222606f43b58 ("wifi: mt76: mt7921: handle MT7902 irq_map quirk
> with mutable copy") for the MT7902 devm_kmemdup() path.
>
>> ---
>> Change in v1
>> --fix uninitialized variable warning
>> ---
>> drivers/net/wireless/mediatek/mt76/mt7921/pci.c | 15 ++++++++++-----
>> 1 file changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
>> index 7a790ddf43bb..49a37185f056 100644
>> --- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
>> +++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
>> @@ -343,11 +343,14 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
>>
>> pci_set_drvdata(pdev, mdev);
>>
>> + dev = container_of(mdev, struct mt792x_dev, mt76);
>> +
>> regs = pcim_iomap_region(pdev, 0, pci_name(pdev));
>> - if (IS_ERR(regs))
>> - return PTR_ERR(regs);
>> + if (IS_ERR(regs)) {
>> + ret = PTR_ERR(regs);
>> + goto err_free_dev;
>> + }
>>
>> - dev = container_of(mdev, struct mt792x_dev, mt76);
>> dev->fw_features = features;
>> dev->hif_ops = &mt7921_pcie_ops;
>> dev->irq_map = &irq_map;
>> @@ -359,8 +362,10 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
>> /* MT7902 needs a mutable copy because wm2_complete_mask differs */
>> map = devm_kmemdup(&pdev->dev, &irq_map,
>> sizeof(irq_map), GFP_KERNEL);
>> - if (!map)
>> - return -ENOMEM;
>> + if (!map) {
>> + ret = -ENOMEM;
>> + goto err_free_dev;
>> + }
>>
>> map->rx.wm2_complete_mask = 0;
>> dev->irq_map = map;
>> --
>> 2.25.1
>>
>>
^ permalink raw reply
* Re: [PATCH v2] wifi: mt76: mt7921: fix resource leak in probe error path
From: Sean Wang @ 2026-05-27 4:48 UTC (permalink / raw)
To: Hongling Zeng
Cc: nbd, lorenzo, ryder.lee, shayne.chen, sean.wang, matthias.bgg,
angelogioacchino.delregno, xiong.huang, madhurkumar004,
linux-wireless, linux-kernel, linux-arm-kernel, linux-mediatek,
zhongling0719
In-Reply-To: <20260527034350.527482-1-zenghongling@kylinos.cn>
Hi,
On Tue, May 26, 2026 at 10:44 PM Hongling Zeng <zenghongling@kylinos.cn> wrote:
>
> When pcim_iomap_region() or devm_kmemdup() fail, the code returns
> directly without cleaning up previously allocated resources:
> - mt76_device allocated by mt76_alloc_device()
> - pci irq vectors allocated by pci_alloc_irq_vectors()
> Fix this by jumping to the existing error cleanup path instead of
> returning directly.
>
> To avoid using an uninitialized variable in the error path, move the
> dev initialization before the error checks.
>
> Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
> Signed-off-by: Hongling Zeng <zenghongling@kylinos.cn>
>
The code change itself looks correct, but commit message Fixes: tag is wrong.
It points to 234738ea3390 ("phy: ti-pipe3: move clk initialization to
a separate function"), which is unrelated to mt76/mt7921.
The two direct-return leaks appear to come from:
- ee5bb35d2b83 ("wifi: mt76: mt7921: Replace deprecated PCI
function") for the pcim_iomap_region() path.
- 222606f43b58 ("wifi: mt76: mt7921: handle MT7902 irq_map quirk
with mutable copy") for the MT7902 devm_kmemdup() path.
> ---
> Change in v1
> --fix uninitialized variable warning
> ---
> drivers/net/wireless/mediatek/mt76/mt7921/pci.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
> index 7a790ddf43bb..49a37185f056 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
> @@ -343,11 +343,14 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
>
> pci_set_drvdata(pdev, mdev);
>
> + dev = container_of(mdev, struct mt792x_dev, mt76);
> +
> regs = pcim_iomap_region(pdev, 0, pci_name(pdev));
> - if (IS_ERR(regs))
> - return PTR_ERR(regs);
> + if (IS_ERR(regs)) {
> + ret = PTR_ERR(regs);
> + goto err_free_dev;
> + }
>
> - dev = container_of(mdev, struct mt792x_dev, mt76);
> dev->fw_features = features;
> dev->hif_ops = &mt7921_pcie_ops;
> dev->irq_map = &irq_map;
> @@ -359,8 +362,10 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
> /* MT7902 needs a mutable copy because wm2_complete_mask differs */
> map = devm_kmemdup(&pdev->dev, &irq_map,
> sizeof(irq_map), GFP_KERNEL);
> - if (!map)
> - return -ENOMEM;
> + if (!map) {
> + ret = -ENOMEM;
> + goto err_free_dev;
> + }
>
> map->rx.wm2_complete_mask = 0;
> dev->irq_map = map;
> --
> 2.25.1
>
>
^ permalink raw reply
* [PATCH v2] wifi: mt76: mt7921: fix resource leak in probe error path
From: Hongling Zeng @ 2026-05-27 3:43 UTC (permalink / raw)
To: nbd, lorenzo, ryder.lee, shayne.chen, sean.wang, matthias.bgg,
angelogioacchino.delregno, xiong.huang, madhurkumar004
Cc: linux-wireless, linux-kernel, linux-arm-kernel, linux-mediatek,
zhongling0719, Hongling Zeng
When pcim_iomap_region() or devm_kmemdup() fail, the code returns
directly without cleaning up previously allocated resources:
- mt76_device allocated by mt76_alloc_device()
- pci irq vectors allocated by pci_alloc_irq_vectors()
Fix this by jumping to the existing error cleanup path instead of
returning directly.
To avoid using an uninitialized variable in the error path, move the
dev initialization before the error checks.
Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
Signed-off-by: Hongling Zeng <zenghongling@kylinos.cn>
---
Change in v1
--fix uninitialized variable warning
---
drivers/net/wireless/mediatek/mt76/mt7921/pci.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
index 7a790ddf43bb..49a37185f056 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
@@ -343,11 +343,14 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
pci_set_drvdata(pdev, mdev);
+ dev = container_of(mdev, struct mt792x_dev, mt76);
+
regs = pcim_iomap_region(pdev, 0, pci_name(pdev));
- if (IS_ERR(regs))
- return PTR_ERR(regs);
+ if (IS_ERR(regs)) {
+ ret = PTR_ERR(regs);
+ goto err_free_dev;
+ }
- dev = container_of(mdev, struct mt792x_dev, mt76);
dev->fw_features = features;
dev->hif_ops = &mt7921_pcie_ops;
dev->irq_map = &irq_map;
@@ -359,8 +362,10 @@ static int mt7921_pci_probe(struct pci_dev *pdev,
/* MT7902 needs a mutable copy because wm2_complete_mask differs */
map = devm_kmemdup(&pdev->dev, &irq_map,
sizeof(irq_map), GFP_KERNEL);
- if (!map)
- return -ENOMEM;
+ if (!map) {
+ ret = -ENOMEM;
+ goto err_free_dev;
+ }
map->rx.wm2_complete_mask = 0;
dev->irq_map = map;
--
2.25.1
^ permalink raw reply related
* Re: [PATCH] Input: mtk-pmic-keys - match loop with count
From: Dmitry Torokhov @ 2026-05-27 1:41 UTC (permalink / raw)
To: Rosen Penev
Cc: linux-input, Matthias Brugger, AngeloGioacchino Del Regno,
open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <20260527004543.22875-1-rosenp@gmail.com>
Hi Rosen,
On Tue, May 26, 2026 at 05:45:43PM -0700, Rosen Penev wrote:
> of_get_available_child_count is used along with
> for_each_child_of_node_scoped, which can cause a mismatch when keys have
> a disabled status.
>
> If a disabled child node exists in the device tree alongside available ones,
> the loop could execute more times than the initial validation accounted for.
> This might increment the index variable past the allocated array bounds,
> leading to out-of-bounds accesses on irqnames[] and keys->keys[].
>
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
> drivers/input/keyboard/mtk-pmic-keys.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboard/mtk-pmic-keys.c
> index c78d9f6d97c4..5d4ebbafd276 100644
> --- a/drivers/input/keyboard/mtk-pmic-keys.c
> +++ b/drivers/input/keyboard/mtk-pmic-keys.c
> @@ -363,7 +363,7 @@ static int mtk_pmic_keys_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - for_each_child_of_node_scoped(node, child) {
> + for_each_available_child_of_node_scoped(node, child) {
> keys->keys[index].regs = &mtk_pmic_regs->keys_regs[index];
>
> keys->keys[index].irq =
I think Sashiko correctly points out that this may result in incorrect
register data and interrupts being mapped to the keys (potentially
shifting them).
Maybe we should stop counting nodes separately, iterate over all of them
here and bail out with an error if we encounter more than 2 (does not
matter if they are marked available or not), and then skip not available
nodes? WDYT?
Thanks.
--
Dmitry
^ permalink raw reply
* [PATCH] Input: mtk-pmic-keys - match loop with count
From: Rosen Penev @ 2026-05-27 0:45 UTC (permalink / raw)
To: linux-input
Cc: Dmitry Torokhov, Matthias Brugger, AngeloGioacchino Del Regno,
open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
of_get_available_child_count is used along with
for_each_child_of_node_scoped, which can cause a mismatch when keys have
a disabled status.
If a disabled child node exists in the device tree alongside available ones,
the loop could execute more times than the initial validation accounted for.
This might increment the index variable past the allocated array bounds,
leading to out-of-bounds accesses on irqnames[] and keys->keys[].
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/input/keyboard/mtk-pmic-keys.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboard/mtk-pmic-keys.c
index c78d9f6d97c4..5d4ebbafd276 100644
--- a/drivers/input/keyboard/mtk-pmic-keys.c
+++ b/drivers/input/keyboard/mtk-pmic-keys.c
@@ -363,7 +363,7 @@ static int mtk_pmic_keys_probe(struct platform_device *pdev)
return -EINVAL;
}
- for_each_child_of_node_scoped(node, child) {
+ for_each_available_child_of_node_scoped(node, child) {
keys->keys[index].regs = &mtk_pmic_regs->keys_regs[index];
keys->keys[index].irq =
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v2] wifi: mt76: track rx napi ownership for cleanup
From: Sean Wang @ 2026-05-26 22:51 UTC (permalink / raw)
To: Ruslan Isaev
Cc: linux-wireless, sean.wang, nbd, lorenzo, ryder.lee,
linux-mediatek, linux-kernel
In-Reply-To: <ahTdpNQp2va_xTVR@wico-dev.wnam.ru>
Hi,
On Mon, May 25, 2026 at 6:39 PM Ruslan Isaev <legale.legale@gmail.com> wrote:
>
>
> mt76_dma_cleanup() deletes rx napi instances for every allocated rx
> queue. This is not symmetric with mt76_dma_init(), which skips WED_RRO
> queues when adding rx napi.
>
> Adding an unconditional napi_disable() in the cleanup path fixes the
> mt7915 remove warning, but it is not safe for all other mt76 paths. mt7921 and
> mt7925 can already disable rx napi in their unregister
> paths before calling mt76_dma_cleanup(). On mt7996/mt7992 WED_RRO
> queues may have ndesc set even though mt76 never added or enabled napi for them.
>
> Track rx napi ownership and enabled state in struct mt76_queue so
> cleanup only disables and deletes napi instances that were actually
> added by mt76.
>
> This keeps the existing reset/suspend/remove ordering intact while
> avoiding double napi_disable() and avoiding napi cleanup on WED_RRO
> queues without napi.
>
> Signed-off-by: Ruslan Isaev <legale.legale@gmail.com>
> ---
> v2:
> - track mt76 rx napi state added/enabled
> - avoid double napi_disable() on mt7921/mt7925 cleanup paths
> - avoid napi cleanup on WED_RRO queues without napi
I do not think v2 is the right shape yet, mainly for a few reasons:
1. The patch scope changed too much
v1 looked like a focused fix for the mt7915/mt7981 remove warning.
But v2 changes the title to RX NAPI ownership tracking and touches
many reset and unregister paths across mt76 and drivers
Could you clarify why the title and scope changed from a targeted
cleanup fix to a generic RX NAPI state refactor?
2. If the issue is limited to mt7915/mt7981 remove, we should consider
fixing it in that functional driver path first
Adding generic NAPI state tracking to struct mt76_queue feels too
broad if the original warning is only from a specific driver removal
path.
3. mt7921/mt7925 do not have the same original issue in practice
The problem I saw with v1 on mt7925 was caused by adding an
unconditional napi_disable() in mt76_dma_cleanup(), while mt7921 and
mt7925 already disable RX NAPI in their unregister paths that cause the
driver to hang.
If mt76_dma_cleanup() is going to own the final RX NAPI
disable/delete path, those duplicated RX NAPI disables in
mt7921/mt7925 unregister should be removed first.
4. If mt76 core does more, functional driver paths should become simpler
A common mt76-layer cleanup should reduce duplicated chip-specific
cleanup logic. v2 instead adds a new NAPI state machine and updates
many functional driver paths, which makes the overall flow harder to
reason about.
5. The WED RRO issue can probably be handled with a smaller symmetric
init/cleanup condition
mt76_dma_init() already skips WED RRO queues when adding RX NAPI.
mt76_dma_cleanup() should use the same condition and only
disable/delete RX NAPI for queues where init actually added RX NAPI.
That would keep init and cleanup symmetric without introducing RX
NAPI ownership state unless we really need it.
So my concern is not about fixing the warning itself, but about the
scope and complexity of v2.
I think we can handle this in two stages:
1. First, fix the current mt7915/mt7981 issue in the affected functional
driver remove path with a minimal and targeted patch. The patch should
also include the appropriate Fixes tag.
2. Then, as a follow-up, we can consider whether mt76 core should own
more of the RX NAPI cleanup path. If we do that, the goal should be
to make the functional driver paths simpler, keep the init/cleanup
conditions symmetric and not cause regression.
Also, I think the patch title should not change too much between v1 and
v2 If this series is still intended to fix the mt7915/mt7981 remove warning,
I would keep the title and scope focused on that first.
Sean
>
> drivers/net/wireless/mediatek/mt76/dma.c | 9 +++--
> drivers/net/wireless/mediatek/mt76/mt76.h | 40 +++++++++++++++++++
> .../net/wireless/mediatek/mt76/mt7603/mac.c | 8 ++--
> .../net/wireless/mediatek/mt76/mt7615/pci.c | 6 +--
> .../wireless/mediatek/mt76/mt7615/pci_mac.c | 4 +-
> .../net/wireless/mediatek/mt76/mt76x0/pci.c | 4 +-
> .../net/wireless/mediatek/mt76/mt76x02_mmio.c | 4 +-
> .../net/wireless/mediatek/mt76/mt76x2/pci.c | 6 +--
> .../net/wireless/mediatek/mt76/mt7915/mac.c | 8 ++--
> .../net/wireless/mediatek/mt76/mt7921/pci.c | 8 ++--
> .../wireless/mediatek/mt76/mt7921/pci_mac.c | 4 +-
> .../net/wireless/mediatek/mt76/mt7925/pci.c | 8 ++--
> .../wireless/mediatek/mt76/mt7925/pci_mac.c | 8 ++--
> .../net/wireless/mediatek/mt76/mt7996/mac.c | 8 ++--
> drivers/net/wireless/mediatek/mt76/npu.c | 3 +-
> 15 files changed, 86 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/dma.c b/drivers/net/wireless/mediatek/mt76/dma.c
> index f8c2fe5f2f58..5c531131a25f 100644
> --- a/drivers/net/wireless/mediatek/mt76/dma.c
> +++ b/drivers/net/wireless/mediatek/mt76/dma.c
> @@ -1099,9 +1099,12 @@ static void
> mt76_dma_rx_queue_init(struct mt76_dev *dev, enum mt76_rxq_id qid,
> int (*poll)(struct napi_struct *napi, int budget))
> {
> + struct mt76_queue *q = &dev->q_rx[qid];
> +
> netif_napi_add(dev->napi_dev, &dev->napi[qid], poll);
> - mt76_dma_rx_fill_buf(dev, &dev->q_rx[qid], false);
> - napi_enable(&dev->napi[qid]);
> + q->napi_state = MT76_NAPI_ADDED;
> + mt76_dma_rx_fill_buf(dev, q, false);
> + mt76_rx_napi_enable(dev, qid);
> }
>
> static int
> @@ -1189,7 +1192,7 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
> mt76_for_each_q_rx(dev, i) {
> struct mt76_queue *q = &dev->q_rx[i];
>
> - netif_napi_del(&dev->napi[i]);
> + mt76_rx_napi_del(dev, i);
> mt76_dma_rx_cleanup(dev, q);
>
> page_pool_destroy(q->page_pool);
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
> index 527bef97e122..3ce936bdcf88 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt76.h
> @@ -251,6 +251,7 @@ struct mt76_queue {
> int buf_size;
> bool stopped;
> bool blocked;
> + u8 napi_state;
>
> u8 buf_offset;
> u16 flags;
> @@ -1283,6 +1284,45 @@ static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q,
> for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \
> if ((dev)->q_rx[i].ndesc)
>
> +#define MT76_NAPI_ADDED BIT(0)
> +#define MT76_NAPI_ENABLED BIT(1)
> +
> +static inline void mt76_rx_napi_enable(struct mt76_dev *dev, int qid)
> +{
> + struct mt76_queue *q = &dev->q_rx[qid];
> +
> + if (!(q->napi_state & MT76_NAPI_ADDED) ||
> + (q->napi_state & MT76_NAPI_ENABLED))
> + return;
> +
> + napi_enable(&dev->napi[qid]);
> + q->napi_state |= MT76_NAPI_ENABLED;
> +}
> +
> +static inline void mt76_rx_napi_disable(struct mt76_dev *dev, int qid)
> +{
> + struct mt76_queue *q = &dev->q_rx[qid];
> +
> + if (!(q->napi_state & MT76_NAPI_ADDED) ||
> + !(q->napi_state & MT76_NAPI_ENABLED))
> + return;
> +
> + napi_disable(&dev->napi[qid]);
> + q->napi_state &= ~MT76_NAPI_ENABLED;
> +}
> +
> +static inline void mt76_rx_napi_del(struct mt76_dev *dev, int qid)
> +{
> + struct mt76_queue *q = &dev->q_rx[qid];
> +
> + if (!(q->napi_state & MT76_NAPI_ADDED))
> + return;
> +
> + mt76_rx_napi_disable(dev, qid);
> + netif_napi_del(&dev->napi[qid]);
> + q->napi_state = 0;
> +}
> +
>
> #define mt76_dereference(p, dev) \
> rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex))
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/mac.c b/drivers/net/wireless/mediatek/mt76/mt7603/mac.c
> index d3110eeb45d7..be35ec0d31d4 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7603/mac.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7603/mac.c
> @@ -1423,8 +1423,8 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
>
> mt76_worker_disable(&dev->mt76.tx_worker);
> tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
> - napi_disable(&dev->mt76.napi[0]);
> - napi_disable(&dev->mt76.napi[1]);
> + mt76_rx_napi_disable(&dev->mt76, 0);
> + mt76_rx_napi_disable(&dev->mt76, 1);
> napi_disable(&dev->mt76.tx_napi);
>
> mutex_lock(&dev->mt76.mutex);
> @@ -1474,8 +1474,8 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
> mt7603_beacon_set_timer(dev, -1, beacon_int);
>
> napi_enable(&dev->mt76.tx_napi);
> - napi_enable(&dev->mt76.napi[0]);
> - napi_enable(&dev->mt76.napi[1]);
> + mt76_rx_napi_enable(&dev->mt76, 0);
> + mt76_rx_napi_enable(&dev->mt76, 1);
>
> local_bh_disable();
> napi_schedule(&dev->mt76.tx_napi);
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/pci.c b/drivers/net/wireless/mediatek/mt76/mt7615/pci.c
> index f5018bfa317a..600b4f2bf1a1 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7615/pci.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7615/pci.c
> @@ -92,7 +92,7 @@ static int mt7615_pci_suspend(struct pci_dev *pdev, pm_message_t state)
> mt76_worker_disable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i) {
> - napi_disable(&mdev->napi[i]);
> + mt76_rx_napi_disable(mdev, i);
> }
> tasklet_kill(&mdev->irq_tasklet);
>
> @@ -127,7 +127,7 @@ static int mt7615_pci_suspend(struct pci_dev *pdev, pm_message_t state)
>
> restore:
> mt76_for_each_q_rx(mdev, i) {
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
> if (hif_suspend)
> @@ -166,7 +166,7 @@ static int mt7615_pci_resume(struct pci_dev *pdev)
> mt76_worker_enable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i) {
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/pci_mac.c b/drivers/net/wireless/mediatek/mt76/mt7615/pci_mac.c
> index 53cb1eed1e4f..a83589c628f9 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7615/pci_mac.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7615/pci_mac.c
> @@ -236,7 +236,7 @@ void mt7615_mac_reset_work(struct work_struct *work)
>
> mt76_worker_disable(&dev->mt76.tx_worker);
> mt76_for_each_q_rx(&dev->mt76, i)
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> napi_disable(&dev->mt76.tx_napi);
>
> mt7615_mutex_acquire(dev);
> @@ -264,7 +264,7 @@ void mt7615_mac_reset_work(struct work_struct *work)
>
> napi_enable(&dev->mt76.tx_napi);
> mt76_for_each_q_rx(&dev->mt76, i) {
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> }
>
> local_bh_disable();
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
> index f8d206a07f99..96380d016351 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
> @@ -257,7 +257,7 @@ static int mt76x0e_suspend(struct pci_dev *pdev, pm_message_t state)
> napi_disable(&mdev->tx_napi);
>
> mt76_for_each_q_rx(mdev, i)
> - napi_disable(&mdev->napi[i]);
> + mt76_rx_napi_disable(mdev, i);
>
> mt76x02_dma_disable(dev);
> mt76x02_mcu_cleanup(dev);
> @@ -285,7 +285,7 @@ static int mt76x0e_resume(struct pci_dev *pdev)
>
> mt76_for_each_q_rx(mdev, i) {
> mt76_queue_rx_reset(dev, i);
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c b/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c
> index dc7c03d23123..0da4bbad5ba3 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c
> @@ -444,7 +444,7 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
> napi_disable(&dev->mt76.tx_napi);
>
> mt76_for_each_q_rx(&dev->mt76, i) {
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> }
>
> mutex_lock(&dev->mt76.mutex);
> @@ -505,7 +505,7 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
>
> napi_enable(&dev->mt76.tx_napi);
> mt76_for_each_q_rx(&dev->mt76, i) {
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> }
>
> local_bh_disable();
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
> index 491a32921a06..a23c2560e90f 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
> @@ -119,7 +119,7 @@ mt76x2e_suspend(struct pci_dev *pdev, pm_message_t state)
> mt76_worker_disable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i)
> - napi_disable(&mdev->napi[i]);
> + mt76_rx_napi_disable(mdev, i);
>
> pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
> pci_save_state(pdev);
> @@ -131,7 +131,7 @@ mt76x2e_suspend(struct pci_dev *pdev, pm_message_t state)
>
> restore:
> mt76_for_each_q_rx(mdev, i)
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> napi_enable(&mdev->tx_napi);
>
> return err;
> @@ -153,7 +153,7 @@ mt76x2e_resume(struct pci_dev *pdev)
> mt76_worker_enable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i) {
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
> index cec2c4208255..354ed0b69013 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
> @@ -1327,7 +1327,7 @@ mt7915_mac_restart(struct mt7915_dev *dev)
> mt76_worker_disable(&dev->mt76.tx_worker);
> mt76_for_each_q_rx(mdev, i) {
> if (mdev->q_rx[i].ndesc)
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> }
> napi_disable(&dev->mt76.tx_napi);
>
> @@ -1339,7 +1339,7 @@ mt7915_mac_restart(struct mt7915_dev *dev)
>
> mt76_for_each_q_rx(mdev, i) {
> if (mdev->q_rx[i].ndesc) {
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> }
> }
>
> @@ -1527,7 +1527,7 @@ void mt7915_mac_reset_work(struct work_struct *work)
>
> mt76_worker_disable(&dev->mt76.tx_worker);
> mt76_for_each_q_rx(&dev->mt76, i)
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> napi_disable(&dev->mt76.tx_napi);
>
>
> @@ -1558,7 +1558,7 @@ void mt7915_mac_reset_work(struct work_struct *work)
> clear_bit(MT76_RESET, &phy2->mt76->state);
>
> mt76_for_each_q_rx(&dev->mt76, i) {
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> }
>
> local_bh_disable();
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
> index 7a790ddf43bb..c3188b344e50 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c
> @@ -52,7 +52,7 @@ static void mt7921e_unregister_device(struct mt792x_dev *dev)
> cancel_work_sync(&dev->init_work);
> mt76_unregister_device(&dev->mt76);
> mt76_for_each_q_rx(&dev->mt76, i)
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> cancel_delayed_work_sync(&pm->ps_work);
> cancel_work_sync(&pm->wake_work);
> cancel_work_sync(&dev->reset_work);
> @@ -492,7 +492,7 @@ static int mt7921_pci_suspend(struct device *device)
> mt76_worker_disable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i) {
> - napi_disable(&mdev->napi[i]);
> + mt76_rx_napi_disable(mdev, i);
> }
>
> /* wait until dma is idle */
> @@ -518,7 +518,7 @@ static int mt7921_pci_suspend(struct device *device)
>
> restore_napi:
> mt76_for_each_q_rx(mdev, i) {
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
>
> @@ -564,7 +564,7 @@ static int mt7921_pci_resume(struct device *device)
> mt76_worker_enable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i) {
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci_mac.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci_mac.c
> index 0db7acb3a637..5d7871b8f77c 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7921/pci_mac.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci_mac.c
> @@ -72,7 +72,7 @@ int mt7921e_mac_reset(struct mt792x_dev *dev)
>
> mt76_worker_disable(&dev->mt76.tx_worker);
> mt76_for_each_q_rx(&dev->mt76, i) {
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> }
> napi_disable(&dev->mt76.tx_napi);
>
> @@ -82,7 +82,7 @@ int mt7921e_mac_reset(struct mt792x_dev *dev)
> mt792x_wpdma_reset(dev, true);
>
> mt76_for_each_q_rx(&dev->mt76, i) {
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> }
>
> local_bh_disable();
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
> index c4161754c01d..1da650ac7f4d 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
> @@ -40,7 +40,7 @@ static void mt7925e_unregister_device(struct mt792x_dev *dev)
> cancel_work_sync(&dev->init_work);
> mt76_unregister_device(&dev->mt76);
> mt76_for_each_q_rx(&dev->mt76, i)
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> cancel_delayed_work_sync(&pm->ps_work);
> cancel_work_sync(&pm->wake_work);
> cancel_work_sync(&dev->reset_work);
> @@ -481,7 +481,7 @@ static int mt7925_pci_suspend(struct device *device)
> mt76_worker_disable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i) {
> - napi_disable(&mdev->napi[i]);
> + mt76_rx_napi_disable(mdev, i);
> }
>
> /* wait until dma is idle */
> @@ -509,7 +509,7 @@ static int mt7925_pci_suspend(struct device *device)
>
> restore_napi:
> mt76_for_each_q_rx(mdev, i) {
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
>
> @@ -559,7 +559,7 @@ static int _mt7925_pci_resume(struct device *device, bool restore)
> mt76_worker_enable(&mdev->tx_worker);
>
> mt76_for_each_q_rx(mdev, i) {
> - napi_enable(&mdev->napi[i]);
> + mt76_rx_napi_enable(mdev, i);
> }
> napi_enable(&mdev->tx_napi);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/pci_mac.c b/drivers/net/wireless/mediatek/mt76/mt7925/pci_mac.c
> index 3072850c2752..6bb47db8d16a 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/pci_mac.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/pci_mac.c
> @@ -88,11 +88,11 @@ int mt7925e_mac_reset(struct mt792x_dev *dev)
>
> mt76_worker_disable(&dev->mt76.tx_worker);
> if (irq_map->rx.data_complete_mask)
> - napi_disable(&dev->mt76.napi[MT_RXQ_MAIN]);
> + mt76_rx_napi_disable(&dev->mt76, MT_RXQ_MAIN);
> if (irq_map->rx.wm_complete_mask)
> - napi_disable(&dev->mt76.napi[MT_RXQ_MCU]);
> + mt76_rx_napi_disable(&dev->mt76, MT_RXQ_MCU);
> if (irq_map->rx.wm2_complete_mask)
> - napi_disable(&dev->mt76.napi[MT_RXQ_MCU_WA]);
> + mt76_rx_napi_disable(&dev->mt76, MT_RXQ_MCU_WA);
> if (irq_map->tx.all_complete_mask)
> napi_disable(&dev->mt76.tx_napi);
>
> @@ -102,7 +102,7 @@ int mt7925e_mac_reset(struct mt792x_dev *dev)
> mt792x_wpdma_reset(dev, true);
>
> mt76_for_each_q_rx(&dev->mt76, i) {
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> }
> napi_enable(&dev->mt76.tx_napi);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> index e2a83da3a09c..a75238ce8807 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> @@ -2262,7 +2262,7 @@ mt7996_mac_restart(struct mt7996_dev *dev)
> continue;
>
> if (mdev->q_rx[i].ndesc)
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> }
> napi_disable(&dev->mt76.tx_napi);
>
> @@ -2278,7 +2278,7 @@ mt7996_mac_restart(struct mt7996_dev *dev)
> continue;
>
> if (mdev->q_rx[i].ndesc) {
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> local_bh_disable();
> napi_schedule(&dev->mt76.napi[i]);
> local_bh_enable();
> @@ -2534,7 +2534,7 @@ void mt7996_mac_reset_work(struct work_struct *work)
> if (mt76_queue_is_npu_txfree(&dev->mt76.q_rx[i]))
> continue;
>
> - napi_disable(&dev->mt76.napi[i]);
> + mt76_rx_napi_disable(&dev->mt76, i);
> }
> napi_disable(&dev->mt76.tx_napi);
>
> @@ -2596,7 +2596,7 @@ void mt7996_mac_reset_work(struct work_struct *work)
> if (mt76_queue_is_npu_txfree(&dev->mt76.q_rx[i]))
> continue;
>
> - napi_enable(&dev->mt76.napi[i]);
> + mt76_rx_napi_enable(&dev->mt76, i);
> local_bh_disable();
> napi_schedule(&dev->mt76.napi[i]);
> local_bh_enable();
> diff --git a/drivers/net/wireless/mediatek/mt76/npu.c b/drivers/net/wireless/mediatek/mt76/npu.c
> index c4c7c0af6321..fb4ba5bdbf48 100644
> --- a/drivers/net/wireless/mediatek/mt76/npu.c
> +++ b/drivers/net/wireless/mediatek/mt76/npu.c
> @@ -291,8 +291,9 @@ int mt76_npu_rx_queue_init(struct mt76_dev *dev, struct mt76_queue *q)
> goto out;
>
> netif_napi_add(dev->napi_dev, &dev->napi[qid], mt76_npu_rx_poll);
> + q->napi_state = MT76_NAPI_ADDED;
> mt76_npu_fill_rx_queue(dev, q);
> - napi_enable(&dev->napi[qid]);
> + mt76_rx_napi_enable(dev, qid);
> out:
> mutex_unlock(&dev->mutex);
>
> --
> 2.39.5
>
>
^ permalink raw reply
* Re: [PATCH] wifi: mt76: mt7925: add wcid publish check in mt76_sta_add
From: Sean Wang @ 2026-05-26 21:52 UTC (permalink / raw)
To: Jiajia Liu
Cc: Felix Fietkau, Lorenzo Bianconi, Ryder Lee, Shayne Chen,
Sean Wang, Matthias Brugger, AngeloGioacchino Del Regno,
Ming Yen Hsieh, Michael Lo, Leon Yen, linux-wireless,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20260526060841.49161-1-liujiajia@kylinos.cn>
Hi,
On Tue, May 26, 2026 at 1:09 AM Jiajia Liu <liujiajia@kylinos.cn> wrote:
>
> Since mt7925_mac_sta_add publishes wcid, add publish check in mt76_sta_add
> to avoid reinitializing the wcid->poll_list for mt7925.
>
> Found dev->sta_poll_list corruption when using mt7925 and 7.0-rc4.
> According to the corruption information, prev->next was changed to itself.
>
> wlan0: disconnect from AP 90:fb:5d:94:8b:e3 for new auth to 90:fb:5d:94:8b:e2
> wlan0: authenticate with 90:fb:5d:94:8b:e2 (local address=84:9e:56:9c:7e:6b)
> wlan0: send auth to 90:fb:5d:94:8b:e2 (try 1/3)
> slab kmalloc-8k start ffff8c80958a6000 pointer offset 4160 size 8192
> list_add corruption. prev->next should be next (ffff8c808a7488f8), but was ffff8c80958a7040. (prev=ffff8c80958a7040).
>
> mt76_wcid_add_poll+0x95/0xd0 [mt76]
> mt7925_mac_add_txs.part.0+0xa5/0xe0 [mt7925_common]
> mt7925_rx_check+0xa7/0xc0 [mt7925_common]
> mt76_dma_rx_poll+0x50d/0x790 [mt76]
> mt792x_poll_rx+0x52/0xe0 [mt792x_lib]
>
> Signed-off-by: Jiajia Liu <liujiajia@kylinos.cn>
> ---
>
> Reproduced and tested using the script below over ssh. Roam between two
> bssids with the same SSID on a router.
>
> #!/bin/bash
>
> set -ex
>
> while :; do
> num=$(sudo iw wlan0 scan | grep Polaris | wc -l)
> if [ $num -eq 2 ]; then
> break
> fi
> done
>
> for i in $(seq 1 500); do
>
> echo "index $i"
> wpa_cli -i wlan0 roam 90:fb:5d:94:8b:e3
> sleep 5
> wpa_cli -i wlan0 roam 90:fb:5d:94:8b:e2
> sleep 5
>
> done
>
> ---
> drivers/net/wireless/mediatek/mt76/mac80211.c | 11 ++++++++---
> drivers/net/wireless/mediatek/mt76/mt76.h | 1 +
> drivers/net/wireless/mediatek/mt76/mt7925/main.c | 3 +++
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mac80211.c b/drivers/net/wireless/mediatek/mt76/mac80211.c
> index 4ae5e4715a9c..83f4f941b890 100644
> --- a/drivers/net/wireless/mediatek/mt76/mac80211.c
> +++ b/drivers/net/wireless/mediatek/mt76/mac80211.c
> @@ -1595,11 +1595,16 @@ mt76_sta_add(struct mt76_phy *phy, struct ieee80211_vif *vif,
> mtxq->wcid = wcid->idx;
> }
>
> - ewma_signal_init(&wcid->rssi);
> - rcu_assign_pointer(dev->wcid[wcid->idx], wcid);
> + if (!test_bit(MT_WCID_FLAG_DRV_PUBLISH, &wcid->flags)) {
> + ewma_signal_init(&wcid->rssi);
> + rcu_assign_pointer(dev->wcid[wcid->idx], wcid);
> + mt76_wcid_init(wcid, phy->band_idx);
> + } else {
> + wcid->phy_idx = phy->band_idx;
> + }
> +
> phy->num_sta++;
>
Thanks for spotting the roaming issue.
I think we can avoid adding MT_WCID_FLAG_DRV_PUBLISH and instead use the
WCID table itself for the publish check.
dev->wcid[] already encodes whether a WCID has been published, so checking
it directly avoids adding a second mirror state. MT_WCID_FLAG_* is also
better kept for WCID features that affect WTBL setup or data-path handling,
rather than common bookkeeping state.
Something like:
@@ -1620,6 +1620,7 @@ mt76_sta_add(struct mt76_phy *phy, struct
ieee80211_vif *vif,
{
struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv;
struct mt76_dev *dev = phy->dev;
+ struct mt76_wcid *published;
int ret;
int i;
@@ -1639,7 +1640,10 @@ mt76_sta_add(struct mt76_phy *phy, struct
ieee80211_vif *vif,
mtxq->wcid = wcid->idx;
}
- if (!test_bit(MT_WCID_FLAG_DRV_PUBLISH, &wcid->flags)) {
+ published = rcu_dereference_protected(dev->wcid[wcid->idx],
+ lockdep_is_held(&dev->mutex));
+ if (published != wcid) {
+ WARN_ON_ONCE(published);
ewma_signal_init(&wcid->rssi);
rcu_assign_pointer(dev->wcid[wcid->idx], wcid);
mt76_wcid_init(wcid, phy->band_idx);
....
> - mt76_wcid_init(wcid, phy->band_idx);
> out:
> mutex_unlock(&dev->mutex);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
> index 527bef97e122..8bfce686bff7 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt76.h
> @@ -361,6 +361,7 @@ enum mt76_wcid_flags {
> MT_WCID_FLAG_PS,
> MT_WCID_FLAG_4ADDR,
> MT_WCID_FLAG_HDR_TRANS,
> + MT_WCID_FLAG_DRV_PUBLISH,
> };
>
> #define MT76_N_WCIDS 1088
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/main.c b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
> index 73d3722739d0..35b5c718475c 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7925/main.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7925/main.c
> @@ -1102,6 +1102,9 @@ int mt7925_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
> &msta->deflink);
> }
>
> + if (!err)
> + set_bit(MT_WCID_FLAG_DRV_PUBLISH, &msta->deflink.wcid.flags);
> +
> return err;
> }
> EXPORT_SYMBOL_GPL(mt7925_mac_sta_add);
> --
> 2.53.0
>
>
^ permalink raw reply
* Re: [PATCH v2] wifi: mt76: track rx napi ownership for cleanup
From: Ruslan Isaev @ 2026-05-26 21:22 UTC (permalink / raw)
To: linux-wireless
Cc: sean.wang, nbd, lorenzo, ryder.lee, linux-mediatek, linux-kernel
In-Reply-To: <ahTdpNQp2va_xTVR@wico-dev.wnam.ru>
Hi Sean and others,
Tested on:
- MT7915E (PCI ID 14c3:7915)
- MT7981 WMAC
On both devices, the Wi-Fi driver module unloads cleanly without warnings
or errors.
Regards,
Ruslan
^ permalink raw reply
* Re: [PATCH RFC net-next v2] net: airoha: Add TCP LRO support
From: Lorenzo Bianconi @ 2026-05-26 21:08 UTC (permalink / raw)
To: Alexander Lobakin
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, linux-arm-kernel, linux-mediatek, netdev,
Madhur Agrawal
In-Reply-To: <7473204e-2ccd-44d8-b703-5a5dbcb29b61@intel.com>
[-- Attachment #1: Type: text/plain, Size: 4912 bytes --]
> From: Lorenzo Bianconi <lorenzo@kernel.org>
> Date: Tue, 26 May 2026 08:58:05 +0200
>
> > Add hardware TCP Large Receive Offload (LRO) support to the airoha_eth
> > driver, leveraging the EN7581/AN7583 SoC's 8 dedicated LRO hardware queues
> > mapped to RX queues 24–31. LRO hw offloading does not support
> > Scatter-Gather (SG) so it is required to increase the page_pool allocation
> > order to 2 for RX queues 24–31 (LRO queues).
> >
> > Performance comparison between GRO and hw LRO has been carried out using
> > a 10Gbps NIC:
> >
> > GRO: ~2.7 Gbps
> > LRO: ~8.1 Gbps
> >
> > Please note with respect to the previous implementation, page_pool
> > allocation order has been reduced from 5 to 2.
> >
> > Tested-by: Madhur Agrawal <madhur.agrawal@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
>
> [...]
>
> > @@ -587,6 +630,85 @@ static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,
> > return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;
> > }
> >
> > +static int airoha_qdma_lro_rx_process(struct airoha_queue *q,
> > + struct airoha_qdma_desc *desc)
> > +{
> > + u32 desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
> > + u32 msg1 = le32_to_cpu(READ_ONCE(desc->msg1));
> > + u32 msg2 = le32_to_cpu(READ_ONCE(desc->msg2));
> > + u32 msg3 = le32_to_cpu(READ_ONCE(desc->msg3));
>
> Why are these READ_ONCE()s needed? Does desc come from the HW (sorry I
> didn't follow the whole code flow) or...?
Correct, ctrl, msg1, msg2 and msg3 are subfields of the DMA descriptor read by
airoha_qdma_rx_process() from the NIC. I guess here we have a similar issue as
the one fixed in [0]
[0] https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=4ae0604a0673e11e2075b178387151fcad5111b5
>
> > + struct sk_buff *skb = q->skb;
> > + u32 len, th_off, tcp_ack_seq;
> > + u16 tcp_win, l2_len;
> > + struct tcphdr *th;
> > + bool ipv4, ipv6;
> > +
> > + if (FIELD_GET(QDMA_ETH_RXMSG_AGG_COUNT_MASK, msg2) <= 1)
> > + return 0;
> > +
> > + ipv4 = FIELD_GET(QDMA_ETH_RXMSG_IP4_MASK, msg1);
> > + ipv6 = FIELD_GET(QDMA_ETH_RXMSG_IP6_MASK, msg1);
> > + if (!ipv4 && !ipv6)
> > + return -EOPNOTSUPP;
> > +
> > + l2_len = FIELD_GET(QDMA_ETH_RXMSG_L2_LEN_MASK, msg2);
> > + len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
> > + if (ipv4) {
> > + struct iphdr *iph;
> > +
> > + if (!pskb_may_pull(skb, l2_len + sizeof(*iph)))
> > + return -EINVAL;
> > +
> > + iph = (struct iphdr *)(skb->data + l2_len);
> > + if (iph->protocol != IPPROTO_TCP)
> > + return -EOPNOTSUPP;
> > +
> > + iph->tot_len = cpu_to_be16(len - l2_len);
> > + iph->check = 0;
> > + iph->check = ip_fast_csum((void *)iph, iph->ihl);
> > + th_off = l2_len + (iph->ihl << 2);
> > + } else {
> > + struct ipv6hdr *ip6h;
> > +
> > + if (!pskb_may_pull(skb, l2_len + sizeof(*ip6h)))
> > + return -EINVAL;
> > +
> > + ip6h = (struct ipv6hdr *)(skb->data + l2_len);
> > + if (ip6h->nexthdr != NEXTHDR_TCP)
> > + return -EOPNOTSUPP;
> > +
> > + ip6h->payload_len = cpu_to_be16(len - l2_len - sizeof(*ip6h));
> > + th_off = l2_len + sizeof(*ip6h);
> > + }
> > +
> > + tcp_win = FIELD_GET(QDMA_ETH_RXMSG_TCP_WIN_MASK, msg3);
> > + tcp_ack_seq = le32_to_cpu(READ_ONCE(desc->data));
> > +
> > + if (!pskb_may_pull(skb, th_off + sizeof(*th)))
> > + return -EINVAL;
> > +
> > + th = (struct tcphdr *)(skb->data + th_off);
> > + th->ack_seq = cpu_to_be32(tcp_ack_seq);
> > + th->window = cpu_to_be16(tcp_win);
> > +
> > + /* Check tcp timestamp option */
> > + if (th->doff == (sizeof(*th) + TCPOLEN_TSTAMP_ALIGNED) / 4) {
> > + __be32 *topt = (__be32 *)(th + 1);
>
> Make sure you checked the code with sparse (sometimes it's needed to
> mark casts as __force, not this one tho)
$ make C=2 CHECK=sparse drivers/net/ethernet/airoha/
CHECK scripts/mod/empty.c
DESCEND objtool
INSTALL libsubcmd_headers
DESCEND bpf/resolve_btfids
INSTALL libsubcmd_headers
CHECK drivers/net/ethernet/airoha/airoha_eth.c
CHECK drivers/net/ethernet/airoha/airoha_ppe.c
CHECK drivers/net/ethernet/airoha/airoha_ppe_debugfs.c
CHECK drivers/net/ethernet/airoha/airoha_npu.c
$ sparse --version
v0.6.5-rc1
>
> > +
> > + if (*topt == cpu_to_be32((TCPOPT_NOP << 24) |
>
> Shouldn't this be `((u32)TCPOPT_NOP) << 24` to avoid sign issues?
I guess this is same approach used in [1]. Am I missing something?
[1] https://github.com/torvalds/linux/blob/master/net/ipv4/tcp_ipv4.c#L823
Regards,
Lorenzo
>
> > + (TCPOPT_NOP << 16) |
> > + (TCPOPT_TIMESTAMP << 8) |
> > + TCPOLEN_TIMESTAMP)) {
> > + __le32 tcp_ts_reply = READ_ONCE(desc->tcp_ts_reply);
> > +
> > + put_unaligned_be32(le32_to_cpu(tcp_ts_reply),
> > + topt + 2);
> > + }
> > + }
> > +
> > + return 0;
> > +}
> Thanks,
> Olek
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH] clk: mediatek: mt8196: Select REGMAP_MMIO for vlpckgen
From: Brian Masney @ 2026-05-26 17:15 UTC (permalink / raw)
To: Akari Tsuyukusa
Cc: mturquette, sboyd, matthias.bgg, angelogioacchino.delregno, wenst,
laura.nao, linux-clk, linux-kernel, linux-arm-kernel,
linux-mediatek, stable
In-Reply-To: <20260522133023.355404-1-akkun11.open@gmail.com>
On Fri, May 22, 2026 at 10:30:23PM +0900, Akari Tsuyukusa wrote:
> The MediaTek MT8196 vlpckgen clock driver uses
> __devm_regmap_init_mmio_clk() by devm_regmap_init_mmio(),
> which is defined in drivers/base/regmap/regmap-mmio.c.
> However, the driver's Kconfig entry does not select REGMAP_MMIO.
> This causes a linker error when REGMAP_MMIO is not enabled.
>
> Fix this by selecting REGMAP_MMIO in the Kconfig entry.
>
> Fixes: 2f8b3ae6f0cb ("clk: mediatek: Add MT8196 vlpckgen clock support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
^ permalink raw reply
* Re: [PATCH RFC net-next v2] net: airoha: Add TCP LRO support
From: Alexander Lobakin @ 2026-05-26 16:01 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, linux-arm-kernel, linux-mediatek, netdev,
Madhur Agrawal
In-Reply-To: <20260526-airoha-eth-lro-v2-1-24e2a9e7a397@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Tue, 26 May 2026 08:58:05 +0200
> Add hardware TCP Large Receive Offload (LRO) support to the airoha_eth
> driver, leveraging the EN7581/AN7583 SoC's 8 dedicated LRO hardware queues
> mapped to RX queues 24–31. LRO hw offloading does not support
> Scatter-Gather (SG) so it is required to increase the page_pool allocation
> order to 2 for RX queues 24–31 (LRO queues).
>
> Performance comparison between GRO and hw LRO has been carried out using
> a 10Gbps NIC:
>
> GRO: ~2.7 Gbps
> LRO: ~8.1 Gbps
>
> Please note with respect to the previous implementation, page_pool
> allocation order has been reduced from 5 to 2.
>
> Tested-by: Madhur Agrawal <madhur.agrawal@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
[...]
> @@ -587,6 +630,85 @@ static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,
> return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;
> }
>
> +static int airoha_qdma_lro_rx_process(struct airoha_queue *q,
> + struct airoha_qdma_desc *desc)
> +{
> + u32 desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
> + u32 msg1 = le32_to_cpu(READ_ONCE(desc->msg1));
> + u32 msg2 = le32_to_cpu(READ_ONCE(desc->msg2));
> + u32 msg3 = le32_to_cpu(READ_ONCE(desc->msg3));
Why are these READ_ONCE()s needed? Does desc come from the HW (sorry I
didn't follow the whole code flow) or...?
> + struct sk_buff *skb = q->skb;
> + u32 len, th_off, tcp_ack_seq;
> + u16 tcp_win, l2_len;
> + struct tcphdr *th;
> + bool ipv4, ipv6;
> +
> + if (FIELD_GET(QDMA_ETH_RXMSG_AGG_COUNT_MASK, msg2) <= 1)
> + return 0;
> +
> + ipv4 = FIELD_GET(QDMA_ETH_RXMSG_IP4_MASK, msg1);
> + ipv6 = FIELD_GET(QDMA_ETH_RXMSG_IP6_MASK, msg1);
> + if (!ipv4 && !ipv6)
> + return -EOPNOTSUPP;
> +
> + l2_len = FIELD_GET(QDMA_ETH_RXMSG_L2_LEN_MASK, msg2);
> + len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
> + if (ipv4) {
> + struct iphdr *iph;
> +
> + if (!pskb_may_pull(skb, l2_len + sizeof(*iph)))
> + return -EINVAL;
> +
> + iph = (struct iphdr *)(skb->data + l2_len);
> + if (iph->protocol != IPPROTO_TCP)
> + return -EOPNOTSUPP;
> +
> + iph->tot_len = cpu_to_be16(len - l2_len);
> + iph->check = 0;
> + iph->check = ip_fast_csum((void *)iph, iph->ihl);
> + th_off = l2_len + (iph->ihl << 2);
> + } else {
> + struct ipv6hdr *ip6h;
> +
> + if (!pskb_may_pull(skb, l2_len + sizeof(*ip6h)))
> + return -EINVAL;
> +
> + ip6h = (struct ipv6hdr *)(skb->data + l2_len);
> + if (ip6h->nexthdr != NEXTHDR_TCP)
> + return -EOPNOTSUPP;
> +
> + ip6h->payload_len = cpu_to_be16(len - l2_len - sizeof(*ip6h));
> + th_off = l2_len + sizeof(*ip6h);
> + }
> +
> + tcp_win = FIELD_GET(QDMA_ETH_RXMSG_TCP_WIN_MASK, msg3);
> + tcp_ack_seq = le32_to_cpu(READ_ONCE(desc->data));
> +
> + if (!pskb_may_pull(skb, th_off + sizeof(*th)))
> + return -EINVAL;
> +
> + th = (struct tcphdr *)(skb->data + th_off);
> + th->ack_seq = cpu_to_be32(tcp_ack_seq);
> + th->window = cpu_to_be16(tcp_win);
> +
> + /* Check tcp timestamp option */
> + if (th->doff == (sizeof(*th) + TCPOLEN_TSTAMP_ALIGNED) / 4) {
> + __be32 *topt = (__be32 *)(th + 1);
Make sure you checked the code with sparse (sometimes it's needed to
mark casts as __force, not this one tho)
> +
> + if (*topt == cpu_to_be32((TCPOPT_NOP << 24) |
Shouldn't this be `((u32)TCPOPT_NOP) << 24` to avoid sign issues?
> + (TCPOPT_NOP << 16) |
> + (TCPOPT_TIMESTAMP << 8) |
> + TCPOLEN_TIMESTAMP)) {
> + __le32 tcp_ts_reply = READ_ONCE(desc->tcp_ts_reply);
> +
> + put_unaligned_be32(le32_to_cpu(tcp_ts_reply),
> + topt + 2);
> + }
> + }
> +
> + return 0;
> +}
Thanks,
Olek
^ permalink raw reply
* [net v2] net: pcs: pcs-mtk-lynxi: fix bpi-r3 serdes configuration
From: Frank Wunderlich @ 2026-05-26 15:32 UTC (permalink / raw)
To: Alexander Couzens, Daniel Golle, Andrew Lunn, Heiner Kallweit,
Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Vladimir Oltean, linux-kernel, linux-mediatek, netdev,
linux-arm-kernel
From: Frank Wunderlich <frank-w@public-files.de>
Commit 8871389da151 introduces common pcs dts properties which writes
rx=normal,tx=normal polarity to register SGMSYS_QPHY_WRAP_CTRL of switch.
This is initialized with tx-bit set and so change inverts polarity
compared to before.
It looks like mt7531 has tx polarity inverted in hardware and set tx-bit
by default to restore the normal polarity.
The MT7531 datasheet quite clearly states:
Register 000050EC QPHY_WRAP_CTRL -- QPHY wrapper control
Reset value: 0x00000501
BIT 1 RX_BIT_POLARITY -- RX bit polarity control
1'b0: normal
1'b1: inverted
BIT 0 TX_BIT_POLARITY -- TX bit polarity control (TX default inversed
in MT7531)
1'b0: normal
1'b1: inverted
Till this patch the register write was only called when mediatek,pnswap
property was set which cannot be done for switch because the fw-node param
was always NULL from switch driver in the mtk_pcs_lynxi_create call.
Do not configure switch side like it's done before.
Fixes: 8871389da151 ("net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap"")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2:
- send as non-RFC
- add datasheet information from Daniel
---
drivers/net/pcs/pcs-mtk-lynxi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c
index c12f8087af9b..a753bd88cbc2 100644
--- a/drivers/net/pcs/pcs-mtk-lynxi.c
+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
@@ -129,6 +129,9 @@ static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs,
unsigned int val = 0;
int ret;
+ if (!fwnode)
+ return 0;
+
if (fwnode_property_read_bool(fwnode, "mediatek,pnswap"))
default_pol = PHY_POL_INVERT;
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v5 5/6] net: phy: Introduce Airoha AN8801R Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-05-26 14:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260526-add-airoha-an8801-support-v5-0-01aea8dee69b@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Introduce a driver for the Airoha AN8801R Series Gigabit Ethernet
PHY; this currently supports setting up PHY LEDs, 10/100M, 1000M
speeds, and Wake on LAN and PHY interrupts.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8801.c | 1120 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1127 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d969a792beb5..099f25dceabb 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -90,6 +90,12 @@ config AS21XXX_PHY
AS21210PB1 that all register with the PHY ID 0x7500 0x7500
before the firmware is loaded.
+config AIR_AN8801_PHY
+ tristate "Airoha AN8801 Gigabit PHY"
+ select AIR_NET_PHYLIB
+ help
+ Currently supports the Airoha AN8801R PHY.
+
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7cf1fa9e12cb..de660ae94945 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -29,6 +29,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
+obj-$(CONFIG_AIR_AN8801_PHY) += air_an8801.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
new file mode 100644
index 000000000000..aa24bb182d64
--- /dev/null
+++ b/drivers/net/phy/air_an8801.c
@@ -0,0 +1,1120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for the Airoha AN8801 Gigabit PHY.
+ *
+ * Copyright (C) 2025 Airoha Technology Corp.
+ * Copyright (C) 2025 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/etherdevice.h>
+#include <linux/init.h>
+#include <linux/minmax.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/pm_wakeirq.h>
+
+#include "air_phy_lib.h"
+
+#define AN8801R_PHY_ID 0xc0ff0421
+
+/* MII Registers */
+
+/* MII Registers - Airoha Page 1 */
+#define AN8801_EXT_REG_PHY 0x14
+#define AN8801_EXT_PHY_STATUS0 GENMASK(1, 0)
+#define AN8801_EXT_PHY_DOWNSHIFT_CTL GENMASK(3, 2) /* 2 to 5 1G auto-neg attempts (0..3) */
+#define AN8801_EXT_PHY_DOWNSHIFT_EN BIT(4)
+#define AN8801_EXT_PHY_CTRL0 BIT(5)
+#define AN8801_EXT_PHY_STATUS1 GENMASK(8, 6)
+#define AN8801_EXT_PHY_CTRL1 GENMASK(14, 9)
+
+/* MII Registers - Airoha Page 4 */
+#define AN8801_PBUS_ACCESS BIT(28)
+#define AN8801_PBUS_EPHY_ACCESS BIT(24)
+#define AN8801_PBUS_CL22_ACCESS BIT(23)
+
+/* BPBUS Registers */
+#define AN8801_BPBUS_REG_LED_GPIO 0x54
+#define AN8801_BPBUS_REG_LED_ID_SEL 0x58
+#define LED_ID_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3))
+#define LED_ID_GPIO_SEL_MASK(gpio) (0x7 << ((gpio) * 3))
+#define AN8801_BPBUS_REG_GPIO_MODE 0x70
+#define AN8801_BPBUS_REG_PHY_IRQ_GPIO 0x7c
+#define AN8801_PHY_IRQ_GPIO_NUM_MASK GENMASK(19, 16)
+#define AN8801_PHY_IRQ_GPIO_NUM 1
+
+#define AN8801_BPBUS_REG_CKO 0x1a4
+#define AN8801_CKO_OUTPUT_MODE_AUTO 3
+
+#define AN8801_BPBUS_REG_LINK_MODE 0x5054
+#define AN8801_BPBUS_LINK_MODE_1000 BIT(0)
+
+#define AN8801_BPBUS_REG_BYPASS_PTP 0x21c004
+#define AN8801_BYP_PTP_SGMII_TO_GPHY BIT(8)
+#define AN8801_BYP_PTP_RGMII_TO_GPHY BIT(0)
+
+#define AN8801_BPBUS_REG_TXDLY_STEP 0x21c024
+#define RGMII_DELAY_STEP_MASK GENMASK(2, 0)
+#define RGMII_DELAY_NO_STEP 0
+#define RGMII_DELAY_STEP_1 1
+#define RGMII_DELAY_STEP_2 2
+#define RGMII_DELAY_STEP_3 3
+#define RGMII_DELAY_STEP_4 4
+#define RGMII_DELAY_STEP_5 5
+#define RGMII_DELAY_STEP_6 6
+#define RGMII_DELAY_STEP_7 7
+#define RGMII_TXDELAY_FORCE_MODE BIT(24)
+
+/* Default RGMII TX delay setting, corresponding to a 1.883ns delay */
+#define AN8801_RGMII_TXDELAY_DEFAULT RGMII_DELAY_STEP_4
+
+#define AN8801_BPBUS_REG_RXDLY_STEP 0x21c02c
+#define RGMII_RXDELAY_ALIGN BIT(4)
+#define RGMII_RXDELAY_FORCE_MODE BIT(24)
+
+/* Default RGMII RX delay setting, corresponding to a 1.992ns delay,
+ * when align bit is set or -0.008ns otherwise.
+ */
+#define AN8801_RGMII_RXDELAY_DEFAULT RGMII_DELAY_NO_STEP
+
+#define AN8801_BPBUS_REG_EFIFO_CTL(x) (0x270004 + (0x100 * (x))) /* 0..2 */
+#define AN8801_EFIFO_ALL_EN GENMASK(7, 0)
+#define AN8801_EFIFO_RX_EN BIT(0)
+#define AN8801_EFIFO_TX_EN BIT(1)
+#define AN8801_EFIFO_RX_CLK_EN BIT(2)
+#define AN8801_EFIFO_TX_CLK_EN BIT(3)
+#define AN8801_EFIFO_RX_EEE_EN BIT(4)
+#define AN8801_EFIFO_TX_EEE_EN BIT(5)
+#define AN8801_EFIFO_RX_ODD_NIBBLE_EN BIT(6)
+#define AN8801_EFIFO_TX_ODD_NIBBLE_EN BIT(7)
+
+#define AN8801_BPBUS_REG_WOL_MAC_16_47 0x285114
+#define AN8801_BPBUS_REG_WOL_MAC_0_15 0x285118
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL1 0x285400
+#define AN8801_WOL_WAKE_MAGIC_EN GENMASK(3, 1)
+#define AN8801_WOL_WAKE_LNKCHG_EN BIT(4)
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL2 0x285404
+#define AN8801_WAKE_OUT_TYPE_PULSE BIT(0) /* Set/Unset: Pulse/Static */
+#define AN8801_WAKE_OUT_POLARITY_NEG BIT(1) /* Set/Unset: Negative/Positive */
+#define AN8801_WAKE_OUT_WIDTH GENMASK(3, 2)
+#define AN8801_WAKE_OUT_84MS 0
+#define AN8801_WAKE_OUT_168MS 1
+#define AN8801_WAKE_OUT_336MS 2
+#define AN8801_WAKE_OUT_672MS 3
+#define AN8801_WAKE_OUT_EN BIT(4)
+#define AN8801_PME_WAKEUP_CLR BIT(8)
+
+#define AN8801_BPBUS_REG_WAKE_IRQ_EN 0x285700
+#define AN8801_BPBUS_REG_WAKE_IRQ_STS 0x285704
+#define AN8801_IRQ_WAKE_LNKCHG BIT(0) /* Wake on link change */
+#define AN8801_IRQ_WAKE_UNIPKT BIT(1) /* Wake on unicast packet */
+#define AN8801_IRQ_WAKE_MULPKT BIT(2) /* Wake on multicast packet */
+#define AN8801_IRQ_WAKE_BCPKT BIT(3) /* Wake on broadcast packet */
+#define AN8801_IRQ_WAKE_MAGICPKT BIT(4) /* Wake on magic packet */
+#define AN8801_IRQ_WAKE_ALL GENMASK(4, 0)
+
+/* MDIO_MMD_VEND1 Registers */
+#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE 0x13
+#define AN8801_PHY_PAIR_DLY_SEL_A_GBE GENMASK(14, 12)
+#define AN8801_PHY_PAIR_DLY_SEL_B_GBE GENMASK(10, 8)
+#define AN8801_PHY_PAIR_DLY_SEL_C_GBE GENMASK(6, 4)
+#define AN8801_PHY_PAIR_DLY_SEL_D_GBE GENMASK(2, 0)
+#define AN8801_PHY_RXADC_CTRL 0xd8
+#define AN8801_PHY_RXADC_SAMP_PHSEL_A BIT(12)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_B BIT(8)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_C BIT(4)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_D BIT(0)
+#define AN8801_PHY_RXADC_REV_0 0xd9
+#define AN8801_PHY_RXADC_REV_MASK_A GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_B GENMASK(7, 0)
+#define AN8801_PHY_RXADC_REV_1 0xda
+#define AN8801_PHY_RXADC_REV_MASK_C GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_D GENMASK(7, 0)
+
+/* MDIO_MMD_VEND2 Registers */
+#define LED_BCR 0x21
+#define LED_BCR_MODE_MASK GENMASK(1, 0)
+#define LED_BCR_TIME_TEST BIT(2)
+#define LED_BCR_CLK_EN BIT(3)
+#define LED_BCR_EVT_ALL BIT(4)
+#define LED_BCR_EXT_CTRL BIT(15)
+#define LED_BCR_MODE_DISABLE 0
+#define LED_BCR_MODE_2LED 1
+#define LED_BCR_MODE_3LED_1 2
+#define LED_BCR_MODE_3LED_2 3
+
+#define LED_ON_DUR 0x22
+#define LED_ON_DUR_MASK GENMASK(15, 0)
+
+#define LED_BLINK_DUR 0x23
+#define LED_BLINK_DUR_MASK GENMASK(15, 0)
+
+#define LED_ON_CTRL(i) (0x24 + ((i) * 2))
+#define LED_ON_EVT_MASK GENMASK(6, 0)
+#define LED_ON_EVT_LINK_1000M BIT(0)
+#define LED_ON_EVT_LINK_100M BIT(1)
+#define LED_ON_EVT_LINK_10M BIT(2)
+#define LED_ON_EVT_LINK_DN BIT(3)
+#define LED_ON_EVT_FDX BIT(4)
+#define LED_ON_EVT_HDX BIT(5)
+#define LED_ON_EVT_FORCE BIT(6)
+#define LED_ON_POL BIT(14)
+#define LED_ON_EN BIT(15)
+
+#define LED_BLINK_CTRL(i) (0x25 + ((i) * 2))
+#define LED_BLINK_EVT_MASK GENMASK(9, 0)
+#define LED_BLINK_EVT_1000M_TX BIT(0)
+#define LED_BLINK_EVT_1000M_RX BIT(1)
+#define LED_BLINK_EVT_100M_TX BIT(2)
+#define LED_BLINK_EVT_100M_RX BIT(3)
+#define LED_BLINK_EVT_10M_TX BIT(4)
+#define LED_BLINK_EVT_10M_RX BIT(5)
+#define LED_BLINK_EVT_COLLISION BIT(6)
+#define LED_BLINK_EVT_RX_CRC_ERR BIT(7)
+#define LED_BLINK_EVT_RX_IDLE_ERR BIT(8)
+#define LED_BLINK_EVT_FORCE BIT(9)
+
+#define AN8801R_NUM_LEDS 3
+#define AN8801_PERIOD_SHIFT 15
+#define AN8801_PERIOD_UNIT 32768 /* (1 << AN8801_PERIOD_SHIFT) */
+#define AN8801_MAX_PERIOD_MS 2147
+
+#define AN8801_REG_PHY_INTERNAL0 0x600
+#define AN8801_REG_PHY_INTERNAL1 0x601
+#define AN8801_PHY_INTFUNC_MASK GENMASK(15, 0) /* PHY internal functions */
+
+enum an8801r_led_fn {
+ AN8801R_LED_FN_NONE,
+ AN8801R_LED_FN_LINK,
+ AN8801R_LED_FN_ACTIVITY,
+ AN8801R_LED_FN_MAX,
+};
+
+struct an8801r_priv {
+ bool wake_magic_enabled;
+ bool wake_lnkchg_enabled;
+};
+
+static const unsigned long an8801r_led_trig = BIT(TRIGGER_NETDEV_LINK) |
+ BIT(TRIGGER_NETDEV_LINK_10) |
+ BIT(TRIGGER_NETDEV_LINK_100) |
+ BIT(TRIGGER_NETDEV_LINK_1000) |
+ BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_RX_ERR) |
+ BIT(TRIGGER_NETDEV_TX);
+
+static int an8801_buckpbus_reg_rmw(struct phy_device *phydev,
+ u32 addr, u32 mask, u32 set)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, set);
+}
+
+static int an8801_buckpbus_reg_set_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, mask);
+}
+
+static int an8801_buckpbus_reg_clear_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, 0);
+}
+
+static int an8801_buckpbus_reg_write(struct phy_device *phydev, u32 addr,
+ u32 data)
+{
+ return air_phy_buckpbus_reg_write(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static int an8801_buckpbus_reg_read(struct phy_device *phydev, u32 addr,
+ u32 *data)
+{
+ return air_phy_buckpbus_reg_read(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static u32 an8801r_led_blink_ms_to_hw(unsigned long req_ms)
+{
+ u32 req_ns, regval;
+
+ if (req_ms > AN8801_MAX_PERIOD_MS)
+ req_ms = AN8801_MAX_PERIOD_MS;
+
+ req_ns = req_ms * NSEC_PER_MSEC;
+
+ /* Round to the nearest period unit... */
+ regval = req_ns + (AN8801_PERIOD_UNIT / 2);
+
+ /* ...and now divide by the full period */
+ regval >>= AN8801_PERIOD_SHIFT;
+
+ return regval;
+}
+
+static int an8801r_led_blink_set(struct phy_device *phydev, u8 index,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ u32 hw_delay_on, hw_delay_off;
+ u16 blink_dur;
+ bool blink;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ if (delay_on && delay_off) {
+ blink = true;
+
+ if (*delay_on == 0 || *delay_off == 0) {
+ *delay_on = 64;
+ *delay_off = 64;
+ }
+
+ hw_delay_on = an8801r_led_blink_ms_to_hw(*delay_on);
+ hw_delay_off = an8801r_led_blink_ms_to_hw(*delay_off);
+ } else {
+ blink = false;
+ }
+
+ if (blink) {
+ blink_dur = (u16)min(hw_delay_on + hw_delay_off,
+ LED_BLINK_DUR_MASK);
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR,
+ blink_dur);
+ if (ret)
+ goto error;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR,
+ hw_delay_on);
+ if (ret)
+ goto error;
+ }
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK,
+ blink ? LED_BLINK_EVT_FORCE : 0);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK,
+ 0);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, blink ? LED_ON_EN : 0);
+
+error:
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, 0);
+ return ret;
+}
+
+static int an8801r_led_brightness_set(struct phy_device *phydev, u8 index,
+ enum led_brightness value)
+{
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ /* Disable blink first if previously enabled */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK, 0);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK,
+ (value == LED_OFF) ? 0 : LED_ON_EVT_FORCE);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, (value == LED_OFF) ? 0 : LED_ON_EN);
+}
+
+static int an8801r_led_hw_control_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules)
+{
+ int on, blink;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index));
+ if (on < 0)
+ return on;
+
+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index));
+ if (blink < 0)
+ return blink;
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_10, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_100M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_100, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_100M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_RX, blink))
+ __set_bit(TRIGGER_NETDEV_RX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_TX, blink))
+ __set_bit(TRIGGER_NETDEV_TX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_RX_CRC_ERR, blink))
+ __set_bit(TRIGGER_NETDEV_RX_ERR, rules);
+
+ return 0;
+}
+
+static int an8801r_led_trig_to_hw(unsigned long rules, u16 *on, u16 *blink)
+{
+ /* All combinations of the supported triggers are allowed */
+ if (rules & ~an8801r_led_trig)
+ return -EOPNOTSUPP;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+ *on |= LED_ON_EVT_LINK_10M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+ *on |= LED_ON_EVT_LINK_100M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+ *on |= LED_ON_EVT_LINK_1000M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK, &rules)) {
+ *on |= LED_ON_EVT_LINK_10M;
+ *on |= LED_ON_EVT_LINK_100M;
+ *on |= LED_ON_EVT_LINK_1000M;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_RX;
+ *blink |= LED_BLINK_EVT_100M_RX;
+ *blink |= LED_BLINK_EVT_1000M_RX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_TX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_TX;
+ *blink |= LED_BLINK_EVT_100M_TX;
+ *blink |= LED_BLINK_EVT_1000M_TX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX_ERR, &rules))
+ *blink |= LED_BLINK_EVT_RX_CRC_ERR;
+
+ return 0;
+}
+
+static int an8801r_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ return an8801r_led_trig_to_hw(rules, &on, &blink);
+}
+
+static int an8801r_led_hw_control_set(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ ret = an8801r_led_trig_to_hw(rules, &on, &blink);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK, on);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK, blink);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, (on | blink) ? LED_ON_EN : 0);
+}
+
+static int an8801r_led_polarity_set(struct phy_device *phydev, int index,
+ unsigned long modes)
+{
+ bool active_high = true;
+ unsigned long mode;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ switch (mode) {
+ case PHY_LED_ACTIVE_HIGH:
+ break;
+ case PHY_LED_ACTIVE_LOW:
+ active_high = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_POL, active_high ? LED_ON_POL : 0);
+}
+
+static int an8801r_led_init(struct phy_device *phydev, u8 *led_cfg)
+{
+ int led_id, ret;
+
+ /* Set LED BCR Enable */
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LED_BCR,
+ LED_BCR_EXT_CTRL | LED_BCR_CLK_EN);
+ if (ret)
+ return ret;
+
+ for (led_id = 0; led_id < AN8801R_NUM_LEDS; led_id++) {
+ unsigned long led_trigger = 0;
+ u32 led_gpio = led_id + 1;
+
+ switch (led_cfg[led_id]) {
+ case AN8801R_LED_FN_LINK:
+ led_trigger = BIT(TRIGGER_NETDEV_LINK);
+ break;
+ case AN8801R_LED_FN_ACTIVITY:
+ led_trigger = BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_TX);
+ break;
+ default:
+ led_trigger = 0;
+ break;
+ }
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_LED_GPIO,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LED_ID_SEL,
+ LED_ID_GPIO_SEL_MASK(led_gpio),
+ LED_ID_GPIO_SEL(led_id,
+ led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_GPIO_MODE,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ if (!led_trigger)
+ continue;
+
+ ret = an8801r_led_hw_control_set(phydev, led_id, led_trigger);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int an8801r_reset_wake(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ u32 reg_val = 0;
+ int ret;
+
+ /* Enable wakeup clear and disable wake up output */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_PME_WAKEUP_CLR |
+ AN8801_WAKE_OUT_POLARITY_NEG);
+ if (ret)
+ return ret;
+
+ /* Clear WAKEUP_CTL1 register before enabling the wakeup events
+ * again
+ */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ 0);
+ if (ret)
+ return ret;
+
+ if (priv->wake_magic_enabled)
+ reg_val |= AN8801_WOL_WAKE_MAGIC_EN;
+
+ if (priv->wake_lnkchg_enabled)
+ reg_val |= AN8801_WOL_WAKE_LNKCHG_EN;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* Disable wake up clear and re-enable wake up output */
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_WAKE_OUT_POLARITY_NEG |
+ AN8801_WAKE_OUT_EN);
+}
+
+static int an8801r_ack_interrupt(struct phy_device *phydev)
+{
+ int ret;
+
+ /* Reset wake status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+
+ /* Clear the interrupts by writing the reg */
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ AN8801_IRQ_WAKE_ALL);
+}
+
+static int an8801r_config_intr(struct phy_device *phydev)
+{
+ int ret;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ u32 val = FIELD_PREP(AN8801_PHY_IRQ_GPIO_NUM_MASK,
+ AN8801_PHY_IRQ_GPIO_NUM);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ 0);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ return an8801r_ack_interrupt(phydev);
+}
+
+static irqreturn_t an8801r_handle_interrupt(struct phy_device *phydev)
+{
+ u32 irq_status = 0;
+ bool irq_handled = false;
+ int ret;
+
+ ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ &irq_status);
+ if (ret)
+ return IRQ_NONE;
+
+ ret = an8801r_ack_interrupt(phydev);
+ if (ret)
+ return IRQ_NONE;
+
+ if (irq_status & AN8801_IRQ_WAKE_MAGICPKT) {
+ pm_wakeup_event(&phydev->mdio.dev, 0);
+ irq_handled = true;
+ }
+
+ if (irq_status & AN8801_IRQ_WAKE_LNKCHG) {
+ phy_trigger_machine(phydev);
+ irq_handled = true;
+ }
+
+ return irq_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static void an8801r_get_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ u32 reg_val;
+ int ret;
+
+ /* If the PHY is not capable of waking the system, then WoL can not
+ * be supported.
+ */
+ if (!device_can_wakeup(&phydev->mdio.dev)) {
+ wol->supported = 0;
+ return;
+ }
+
+ wol->supported = WAKE_MAGIC;
+ wol->wolopts = 0;
+
+ ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ ®_val);
+ if (ret)
+ return;
+
+ if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
+ wol->wolopts |= WAKE_MAGIC;
+ else
+ wol->wolopts &= ~WAKE_MAGIC;
+}
+
+static int an8801r_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ struct net_device *attach_dev;
+ const u8 *macaddr;
+ u32 reg_val;
+ int ret;
+
+ if (!device_can_wakeup(&phydev->mdio.dev))
+ return -EOPNOTSUPP;
+
+ if (wol->wolopts & ~WAKE_MAGIC)
+ return -EINVAL;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ attach_dev = phydev->attached_dev;
+ if (!attach_dev)
+ return -ENODEV;
+
+ macaddr = (const u8 *)attach_dev->dev_addr;
+ if (!is_valid_ether_addr(macaddr))
+ return -EINVAL;
+
+ /* MAC bits 16..47 */
+ reg_val = (macaddr[2] << 24) | (macaddr[3] << 16);
+ reg_val |= (macaddr[4] << 8) | (macaddr[5]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_16_47,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* MAC bits 0..15 */
+ reg_val = (macaddr[0] << 8) | (macaddr[1]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_0_15,
+ reg_val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+ }
+
+ priv->wake_magic_enabled = !!(wol->wolopts & WAKE_MAGIC);
+
+ return device_set_wakeup_enable(&phydev->mdio.dev,
+ priv->wake_magic_enabled);
+}
+
+static int an8801r_of_init_leds(struct phy_device *phydev, u8 *led_cfg)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *leds;
+ u32 function_enum_idx;
+ int ret = 0;
+
+ if (!np)
+ return 0;
+
+ /* If devicetree is present, leds configuration is required */
+ leds = of_get_child_by_name(np, "leds");
+ if (!leds)
+ return 0;
+
+ for_each_available_child_of_node_scoped(leds, led) {
+ u32 led_idx;
+
+ ret = of_property_read_u32(led, "reg", &led_idx);
+ if (ret)
+ goto out;
+
+ if (led_idx >= AN8801R_NUM_LEDS) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = of_property_read_u32(led, "function-enumerator",
+ &function_enum_idx);
+ if (ret) {
+ function_enum_idx = AN8801R_LED_FN_NONE;
+ ret = 0;
+ }
+
+ if (function_enum_idx >= AN8801R_LED_FN_MAX) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ led_cfg[led_idx] = function_enum_idx;
+ }
+out:
+ of_node_put(leds);
+ return ret;
+}
+
+static int an8801r_rgmii_rxdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ /* Set force mode bit to enable RX delay insertion */
+ reg_val = delay_steps | RGMII_RXDELAY_FORCE_MODE;
+
+ /* Set align bit to add extra offset for RX delay */
+ reg_val |= RGMII_RXDELAY_ALIGN;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_txdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ /* Set force mode bit to enable TX delay insertion */
+ reg_val = delay_steps | RGMII_TXDELAY_FORCE_MODE;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_delay_config(struct phy_device *phydev)
+{
+ bool enable_delay;
+ u16 delay_step;
+ int ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_TXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ ret = an8801r_rgmii_txdelay(phydev, enable_delay, delay_step);
+ if (ret)
+ return ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_RXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ return an8801r_rgmii_rxdelay(phydev, enable_delay, delay_step);
+}
+
+static int an8801r_config_init(struct phy_device *phydev)
+{
+ u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
+ int ret;
+
+ ret = an8801r_of_init_leds(phydev, led_default_function);
+ if (ret)
+ return ret;
+
+ /* Disable Low Power Mode (LPM) */
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2));
+ if (ret)
+ return ret;
+
+ /* Set the PHY to perform auto-downshift after 3 auto-negotiation
+ * attempts
+ */
+ ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,
+ AN8801_EXT_REG_PHY,
+ FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
+ FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
+ AN8801_EXT_PHY_DOWNSHIFT_EN);
+ if (ret < 0)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP,
+ AN8801_BYP_PTP_RGMII_TO_GPHY);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0),
+ AN8801_EFIFO_RX_EN |
+ AN8801_EFIFO_TX_EN |
+ AN8801_EFIFO_RX_CLK_EN |
+ AN8801_EFIFO_TX_CLK_EN |
+ AN8801_EFIFO_RX_EEE_EN |
+ AN8801_EFIFO_TX_EEE_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ AN8801_PHY_TX_PAIR_DLY_SEL_GBE,
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_A_GBE, 4) |
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_C_GBE, 4));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_CTRL,
+ AN8801_PHY_RXADC_SAMP_PHSEL_A |
+ AN8801_PHY_RXADC_SAMP_PHSEL_C);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_A, 1));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_C, 1));
+ if (ret)
+ return ret;
+
+ ret = an8801r_rgmii_delay_config(phydev);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_CKO,
+ AN8801_CKO_OUTPUT_MODE_AUTO);
+ if (ret)
+ return ret;
+
+ ret = an8801r_led_init(phydev, led_default_function);
+ if (ret) {
+ phydev_err(phydev, "Cannot initialize LEDs: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int an8801r_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct an8801r_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->wake_lnkchg_enabled = true;
+
+ phydev->priv = priv;
+
+ /* Mark this PHY as wakeup capable and register the interrupt as a
+ * wakeup IRQ if the PHY is marked as a wakeup source in devicetree,
+ * and the interrupt is valid.
+ */
+ if (of_property_read_bool(dev->of_node, "wakeup-source") &&
+ phy_interrupt_is_valid(phydev)) {
+ device_set_wakeup_capable(dev, true);
+ devm_pm_set_wake_irq(dev, phydev->irq);
+ }
+
+ return 0;
+}
+
+static int an8801r_suspend(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ /* If the PHY may wake up by a Wake-on-LAN (WOL) event, disable the link
+ * interrupt to only keep the WOL magic interrupt enabled
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = false;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ /* Reset WOL status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+ }
+
+ if (!phydev->wol_enabled)
+ return genphy_suspend(phydev);
+
+ return 0;
+}
+
+static int an8801r_resume(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ ret = genphy_resume(phydev);
+ if (ret)
+ return ret;
+
+ /* Restore the interrupt enable so phylib can receive link
+ * state interrupts.
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = true;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_LNKCHG_EN);
+ if (ret)
+ return ret;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ }
+ }
+
+ return ret;
+}
+
+static struct phy_driver airoha_driver[] = {
+{
+ PHY_ID_MATCH_MODEL(AN8801R_PHY_ID),
+ .name = "Airoha AN8801R",
+ .probe = an8801r_probe,
+ .config_init = an8801r_config_init,
+ .suspend = an8801r_suspend,
+ .resume = an8801r_resume,
+ .config_aneg = genphy_config_aneg,
+ .config_intr = an8801r_config_intr,
+ .handle_interrupt = an8801r_handle_interrupt,
+ .set_wol = an8801r_set_wol,
+ .get_wol = an8801r_get_wol,
+ .read_page = air_phy_read_page,
+ .write_page = air_phy_write_page,
+ .flags = PHY_ALWAYS_CALL_SUSPEND,
+ .led_brightness_set = an8801r_led_brightness_set,
+ .led_blink_set = an8801r_led_blink_set,
+ .led_hw_is_supported = an8801r_led_hw_is_supported,
+ .led_hw_control_set = an8801r_led_hw_control_set,
+ .led_hw_control_get = an8801r_led_hw_control_get,
+ .led_polarity_set = an8801r_led_polarity_set,
+} };
+module_phy_driver(airoha_driver);
+
+static struct mdio_device_id __maybe_unused an8801_tbl[] = {
+ { PHY_ID_MATCH_MODEL(AN8801R_PHY_ID) },
+ { }
+};
+MODULE_DEVICE_TABLE(mdio, an8801_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8801 PHY driver");
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v5 6/6] net: phy: air_an8801: ensure maximum available speed link use
From: Louis-Alexis Eyraud @ 2026-05-26 14:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260526-add-airoha-an8801-support-v5-0-01aea8dee69b@collabora.com>
To ensure that the Airoha AN8801R PHY uses the maximum available link
speed, an additional register write is needed to configure the function
mode for either 1G or 100M/10M operation after link detection.
So, in air_an8801 driver, implement a custom read_status callback, that
after genphy_read_status determines the link speed, sets the bit 0 of
the link mode register (REG_LINK_MODE) if the detected speed is 1Gbps,
or unsets it otherwise.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_an8801.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
index aa24bb182d64..f97c78e43023 100644
--- a/drivers/net/phy/air_an8801.c
+++ b/drivers/net/phy/air_an8801.c
@@ -996,6 +996,41 @@ static int an8801r_config_init(struct phy_device *phydev)
return 0;
}
+static int an8801r_read_status(struct phy_device *phydev)
+{
+ int prev_speed, ret;
+ u32 val;
+
+ prev_speed = phydev->speed;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (!phydev->link) {
+ phydev->speed = SPEED_UNKNOWN;
+ return 0;
+ }
+
+ if (prev_speed != phydev->speed) {
+ /* Ensure that PHY switches to 1G speed when available,
+ * by configuring the function mode for either 1G or 100M/10M
+ * operation.
+ * Therefore, set the link mode register, after read_status
+ * determines the link speed.
+ */
+ val = phydev->speed == SPEED_1000 ?
+ AN8801_BPBUS_LINK_MODE_1000 : 0;
+
+ return an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LINK_MODE,
+ AN8801_BPBUS_LINK_MODE_1000,
+ val);
+ }
+
+ return 0;
+}
+
static int an8801r_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -1093,6 +1128,7 @@ static struct phy_driver airoha_driver[] = {
.suspend = an8801r_suspend,
.resume = an8801r_resume,
.config_aneg = genphy_config_aneg,
+ .read_status = an8801r_read_status,
.config_intr = an8801r_config_intr,
.handle_interrupt = an8801r_handle_interrupt,
.set_wol = an8801r_set_wol,
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v5 4/6] net: phy: Rename Airoha common BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-05-26 14:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260526-add-airoha-an8801-support-v5-0-01aea8dee69b@collabora.com>
Rename the BuckPBus register accessors functions present in air_phy_lib
and their calls in air_en8811h driver, so all exported functions start
with the same prefix.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 110 +++++++++++++++++++++---------------------
drivers/net/phy/air_phy_lib.c | 18 +++----
drivers/net/phy/air_phy_lib.h | 12 ++---
3 files changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 2498bd3f7993..a42898ae4135 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -287,8 +287,8 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev)
{
int ret, reg_value;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_FINISH);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_FINISH);
if (ret)
return ret;
@@ -313,28 +313,29 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 set1,
int ret;
/* Configure CRC */
- ret = air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN,
- AN8811HB_CRC_RD_EN);
+ ret = air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ AN8811HB_CRC_RD_EN);
if (ret < 0)
return ret;
- air_buckpbus_reg_read(phydev, set1, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, set1, &pbus_value);
do {
msleep(300);
- air_buckpbus_reg_read(phydev, mon2, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value);
/* We do not know what errors this check is supposed
* catch or what to do about a failure. So print the
* result and continue like the vendor driver does.
*/
if (pbus_value & AN8811HB_CRC_ST) {
- air_buckpbus_reg_read(phydev, mon3, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value);
phydev_dbg(phydev, "CRC Check %s!\n",
pbus_value & AN8811HB_CRC_CHECK_PASS ?
"PASS" : "FAIL");
- return air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN, 0);
+ return air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ 0);
}
} while (--retry);
@@ -346,8 +347,8 @@ static void en8811h_print_fw_version(struct phy_device *phydev)
{
struct en8811h_priv *priv = phydev->priv;
- air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
- &priv->firmware_version);
+ air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
+ &priv->firmware_version);
phydev_info(phydev, "MD32 firmware version: %08x\n",
priv->firmware_version);
}
@@ -372,8 +373,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -414,14 +415,14 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_rel1;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING,
- EN8811H_FW_CTRL_2_LOADING);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING,
+ EN8811H_FW_CTRL_2_LOADING);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -433,8 +434,8 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING, 0);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING, 0);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -460,8 +461,8 @@ static int en8811h_restart_mcu(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -755,7 +756,7 @@ static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
if (ret < 0)
return ret;
@@ -767,9 +768,9 @@ static int an8811hb_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK,
- AN8811HB_CLK_DRV_CKO_MASK);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK,
+ AN8811HB_CLK_DRV_CKO_MASK);
}
static void an8811hb_clk_disable(struct clk_hw *hw)
@@ -777,8 +778,8 @@ static void an8811hb_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK, 0);
+ air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK, 0);
}
static int an8811hb_clk_is_enabled(struct clk_hw *hw)
@@ -788,7 +789,7 @@ static int an8811hb_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
if (ret < 0)
return ret;
@@ -854,7 +855,7 @@ static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
if (ret < 0)
return ret;
@@ -866,9 +867,9 @@ static int en8811h_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO,
- EN8811H_CLK_CGM_CKO);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO,
+ EN8811H_CLK_CGM_CKO);
}
static void en8811h_clk_disable(struct clk_hw *hw)
@@ -876,8 +877,8 @@ static void en8811h_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO, 0);
+ air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO, 0);
}
static int en8811h_clk_is_enabled(struct clk_hw *hw)
@@ -887,7 +888,7 @@ static int en8811h_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
if (ret < 0)
return ret;
@@ -998,9 +999,9 @@ static int an8811hb_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
- AN8811HB_GPIO_OUTPUT_345,
- AN8811HB_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
+ AN8811HB_GPIO_OUTPUT_345,
+ AN8811HB_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1039,9 +1040,9 @@ static int en8811h_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
- EN8811H_GPIO_OUTPUT_345,
- EN8811H_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
+ EN8811H_GPIO_OUTPUT_345,
+ EN8811H_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1061,9 +1062,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
return ret;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
- AN8811HB_RX_POLARITY_NORMAL,
- pbus_value);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
+ AN8811HB_RX_POLARITY_NORMAL,
+ pbus_value);
if (ret < 0)
return ret;
@@ -1074,9 +1075,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
pbus_value = 0;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
- return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
- AN8811HB_TX_POLARITY_NORMAL,
- pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
+ AN8811HB_TX_POLARITY_NORMAL,
+ pbus_value);
}
static int en8811h_config_serdes_polarity(struct phy_device *phydev)
@@ -1110,9 +1111,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev)
if (pol == PHY_POL_NORMAL)
pbus_value |= EN8811H_POLARITY_TX_NORMAL;
- return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
- EN8811H_POLARITY_RX_REVERSE |
- EN8811H_POLARITY_TX_NORMAL, pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
+ EN8811H_POLARITY_RX_REVERSE |
+ EN8811H_POLARITY_TX_NORMAL,
+ pbus_value);
}
static int an8811hb_config_init(struct phy_device *phydev)
@@ -1264,8 +1266,8 @@ static int en8811h_read_status(struct phy_device *phydev)
val & MDIO_AN_10GBT_STAT_LP2_5G);
} else {
/* Get link partner 2.5GBASE-T ability from vendor register */
- ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
- &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
+ &pbus_value);
if (ret < 0)
return ret;
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index aba4f95fe9e6..859fa41406d1 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -137,8 +137,8 @@ static int __air_buckpbus_reg_modify(struct phy_device *phydev,
return 0;
}
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data)
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
{
int saved_page;
int ret = 0;
@@ -154,10 +154,10 @@ int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_read);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data)
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
{
int saved_page;
int ret = 0;
@@ -174,10 +174,10 @@ int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_write);
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set)
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
{
int saved_page;
int ret = 0;
@@ -194,7 +194,7 @@ int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_modify);
int air_phy_read_page(struct phy_device *phydev)
{
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index b637f3e0f2d5..a2f8b3725761 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -27,12 +27,12 @@
#define AIR_BPBUS_RD_DATA_HIGH 0x17
#define AIR_BPBUS_RD_DATA_LOW 0x18
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set);
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data);
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v5 3/6] net: phy: air_phy_lib: Factorize BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-05-26 14:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260526-add-airoha-an8801-support-v5-0-01aea8dee69b@collabora.com>
In preparation of Airoha AN8801R PHY support, move the BuckPBus
register accessors and definitions, present in air_en8811h driver,
into the Airoha PHY shared code (air_phy_lib), so they will be usable
by the new driver without duplicating them.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 193 ------------------------------------------
drivers/net/phy/air_phy_lib.c | 181 +++++++++++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 23 +++++
3 files changed, 204 insertions(+), 193 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index be7c3426182a..2498bd3f7993 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -42,22 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_PHY_PAGE_STANDARD 0x0000
-#define AIR_PHY_PAGE_EXTENDED_4 0x0004
-
-/* MII Registers Page 4*/
-#define AIR_BPBUS_MODE 0x10
-#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
-#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
-#define AIR_BPBUS_WR_ADDR_HIGH 0x11
-#define AIR_BPBUS_WR_ADDR_LOW 0x12
-#define AIR_BPBUS_WR_DATA_HIGH 0x13
-#define AIR_BPBUS_WR_DATA_LOW 0x14
-#define AIR_BPBUS_RD_ADDR_HIGH 0x15
-#define AIR_BPBUS_RD_ADDR_LOW 0x16
-#define AIR_BPBUS_RD_DATA_HIGH 0x17
-#define AIR_BPBUS_RD_DATA_LOW 0x18
-
/* Registers on MDIO_MMD_VEND1 */
#define EN8811H_PHY_FW_STATUS 0x8009
#define EN8811H_PHY_READY 0x02
@@ -245,183 +229,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int __air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_write(phydev, pbus_address,
- pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int pbus_data_low, pbus_data_high;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- *pbus_data = pbus_data_low | (pbus_data_high << 16);
- return 0;
-}
-
-static int air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int pbus_data_low, pbus_data_high;
- u32 pbus_data_old, pbus_data_new;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- pbus_data_old = pbus_data_low | (pbus_data_high << 16);
- pbus_data_new = (pbus_data_old & ~mask) | set;
- if (pbus_data_new == pbus_data_old)
- return 0;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
- set);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
static int __air_write_buf(struct phy_device *phydev, u32 address,
const struct firmware *fw)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index 8ef5af4becf0..aba4f95fe9e6 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -10,11 +10,192 @@
#include <linux/export.h>
#include <linux/module.h>
#include <linux/phy.h>
+#include <linux/wordpart.h>
#include "air_phy_lib.h"
#define AIR_EXT_PAGE_ACCESS 0x1f
+static int __air_buckpbus_reg_read(struct phy_device *phydev,
+ u32 pbus_address, u32 *pbus_data)
+{
+ int pbus_data_low, pbus_data_high;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ *pbus_data = pbus_data_low | (pbus_data_high << 16);
+ return 0;
+}
+
+static int __air_buckpbus_reg_write(struct phy_device *phydev,
+ u32 pbus_address, u32 pbus_data)
+{
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int __air_buckpbus_reg_modify(struct phy_device *phydev,
+ u32 pbus_address, u32 mask, u32 set)
+{
+ int pbus_data_low, pbus_data_high;
+ u32 pbus_data_old, pbus_data_new;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ pbus_data_new = (pbus_data_old & ~mask) | set;
+ if (pbus_data_new == pbus_data_old)
+ return 0;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
+
+int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_write(phydev, pbus_address,
+ pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
+
+int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
+ set);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
+
int air_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index 79367e8e5907..b637f3e0f2d5 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -10,6 +10,29 @@
#include <linux/phy.h>
+#define AIR_PHY_PAGE_STANDARD 0x0000
+#define AIR_PHY_PAGE_EXTENDED_1 0x0001
+#define AIR_PHY_PAGE_EXTENDED_4 0x0004
+
+/* MII Registers Page 4*/
+#define AIR_BPBUS_MODE 0x10
+#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
+#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
+#define AIR_BPBUS_WR_ADDR_HIGH 0x11
+#define AIR_BPBUS_WR_ADDR_LOW 0x12
+#define AIR_BPBUS_WR_DATA_HIGH 0x13
+#define AIR_BPBUS_WR_DATA_LOW 0x14
+#define AIR_BPBUS_RD_ADDR_HIGH 0x15
+#define AIR_BPBUS_RD_ADDR_LOW 0x16
+#define AIR_BPBUS_RD_DATA_HIGH 0x17
+#define AIR_BPBUS_RD_DATA_LOW 0x18
+
+int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v5 2/6] net: phy: Add Airoha phy library for shared code
From: Louis-Alexis Eyraud @ 2026-05-26 14:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260526-add-airoha-an8801-support-v5-0-01aea8dee69b@collabora.com>
In preparation of Airoha AN8801R PHY support, split out the interface
functions that will be common between the already present air_en8811h
driver and the new one, and put them into a new library named
air_phy_lib.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_en8811h.c | 13 ++-----------
drivers/net/phy/air_phy_lib.c | 32 ++++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 16 ++++++++++++++++
5 files changed, 57 insertions(+), 11 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 8b51bdc2e945..d969a792beb5 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -92,10 +92,16 @@ config AS21XXX_PHY
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ select AIR_NET_PHYLIB
select PHY_COMMON_PROPS
help
Currently supports the Airoha EN8811H PHY.
+config AIR_NET_PHYLIB
+ tristate
+ help
+ Airoha Ethernet PHY common library
+
config AMD_PHY
tristate "AMD and Altima PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 05e4878af27a..7cf1fa9e12cb 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,6 +30,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o
obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 29ae73e65caa..be7c3426182a 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -21,6 +21,8 @@
#include <linux/wordpart.h>
#include <linux/unaligned.h>
+#include "air_phy_lib.h"
+
#define EN8811H_PHY_ID 0x03a2a411
#define AN8811HB_PHY_ID 0xc0ff04a0
@@ -40,7 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_EXT_PAGE_ACCESS 0x1f
#define AIR_PHY_PAGE_STANDARD 0x0000
#define AIR_PHY_PAGE_EXTENDED_4 0x0004
@@ -244,16 +245,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int air_phy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-}
-
-static int air_phy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-}
-
static int __air_buckpbus_reg_write(struct phy_device *phydev,
u32 pbus_address, u32 pbus_data)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
new file mode 100644
index 000000000000..8ef5af4becf0
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Airoha Ethernet PHY common library
+ *
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+
+#include "air_phy_lib.h"
+
+#define AIR_EXT_PAGE_ACCESS 0x1f
+
+int air_phy_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
+}
+EXPORT_SYMBOL_GPL(air_phy_read_page);
+
+int air_phy_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
+}
+EXPORT_SYMBOL_GPL(air_phy_write_page);
+
+MODULE_DESCRIPTION("Airoha PHY Library");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Louis-Alexis Eyraud");
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
new file mode 100644
index 000000000000..79367e8e5907
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef __AIR_PHY_LIB_H
+#define __AIR_PHY_LIB_H
+
+#include <linux/phy.h>
+
+int air_phy_read_page(struct phy_device *phydev);
+int air_phy_write_page(struct phy_device *phydev, int page);
+
+#endif /* __AIR_PHY_LIB_H */
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v5 1/6] dt-bindings: net: Add support for Airoha AN8801R GbE PHY
From: Louis-Alexis Eyraud @ 2026-05-26 14:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260526-add-airoha-an8801-support-v5-0-01aea8dee69b@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add a new binding to support the Airoha AN8801R Series Gigabit
Ethernet PHY.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../devicetree/bindings/net/airoha,an8801.yaml | 120 +++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
new file mode 100644
index 000000000000..d6e5a60a6b20
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8801.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8801R Series PHY
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
+ with Single-port serdes interface for 1000Base-X/RGMII; this chip is
+ compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab)
+ and supports Energy Efficient Ethernet (802.3az), Full Duplex Control
+ Flow (802.3x), auto-negotiation, crossover detect and autocorrection,
+ Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes.
+ This PHY also supports up to three user-configurable LEDs, which are
+ usually used for LAN Activity, 100M, 1000M indication.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-idc0ff.0421
+
+ reg:
+ maxItems: 1
+
+ leds:
+ type: object
+ description:
+ Describes the LEDs associated to the PHY
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^led@[0-2]$":
+ type: object
+ description: PHY LEDs
+ $ref: /schemas/leds/common.yaml#
+
+ properties:
+ reg:
+ enum: [0, 1, 2]
+
+ function-enumerator:
+ enum: [0, 1, 2]
+ description: |
+ Specifies a function for offloading LED functionality to the PHY:
+ 0 - No offloading
+ 1 - Link Availability
+ 2 - Network Activity
+
+ required:
+ - reg
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enable Wake-on-LAN support
+
+required:
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-idc0ff.0421";
+ reg = <0>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ default-state = "keep";
+ };
+ };
+ };
+ };
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v5 0/6] Introduce Airoha AN8801R series Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-05-26 14:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
This series introduces the Airoha AN8801R Gigabit Ethernet PHY initial
support.
The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
with Single-port serdes interface for 1000Base-X/RGMII.
This chip is compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE
802.3(u,ab) and supports:
- Energy Efficient Ethernet (802.3az)
- Full Duplex Control Flow (802.3x)
- auto-negotiation
- crossover detect and autocorrection,
- Wake-on-LAN with Magic Packet
- Jumbo Frame up to 9 Kilobytes.
This PHY also supports up to three user-configurable LEDs, which are
usually used for LAN Activity, 100M, 1000M indication.
The series provides the devicetree binding and the driver that have been
written by AngeloGioacchino Del Regno, based on downstream
implementation ([1]). The driver allows setting up PHY LEDs, 10/100M,
1000M speeds, and Wake on LAN and PHY interrupts.
Since v2, the series also adds the air_phy_lib library, which goal is to
share common code between air_en8811h and air_an8801 drivers, and its use
in them. The first shared functions are the existing BuckPbus register
accessors and air_phy_read/write_page functions coming from air_en8811h
driver.
The series is based on net-next kernel tree (sha1: 90d03ee2c5dc) and
I have tested it on Mediatek Genio 720-EVK board (that integrates an
Airoha AN8801RIN/A Ethernet PHY) with early board hardware enablement
patches.
[1]: https://gitlab.com/mediatek/aiot/bsp/linux/-/blob/mtk-v6.6/drivers/net/phy/an8801.c
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Changes in v5:
- Rebased on net-next (90d03ee2c5dc)
- Fixed in patch 1 missing unevaluatedProperties/additionalProperties
to resolve dt_binding_check issues
- Reworked in patch 5 overflow handling when writing LED_BLINK_DUR
register value in an8801r_led_blink_set (sashiko-nipa and
sashiko.dev)
- Reworked an8801r_led_brightness_set to disable blinking first before
setting led state (sashiko-dev)
- Added led index validity check in an8801r_led_hw_control_get
(sashiko-nipa)
- Added attached_dev and mac adress validity check in
an8801r_set_wol (sashiko-nipa)
- Reworked ternary operation syntax to make it more explicit in
an8801r_led_hw_control_set (sashiko-nipa)
- Removed unused AN8801_LED_DURATION_UNIT_US definition (sashiko-nipa)
- Fixed AN8801_RGMII_RXDELAY_DEFAULT definition comment (sashiko-nipa)
- Fixed typo in an8801r_suspend (sashiko-nipa)
- Removed in patch 6 the speed restore action on an8801_buckpbus_reg_rmw
error to restore v3 behaviour in an8801r_read_status (sashiko-nipa and
sashiko-dev)
- Link to v4: https://lore.kernel.org/r/20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com
Changes in v4:
- Rebased on net-next (830d8771ae3c)
- Added in patch 1 the missing function-enumator property description,
that should already have been present in v3
- Modified patch 1 and patch 5 subjects to use AN8801R and not AN8801/R
(detected by sashiko-nipa)
- Modified patch 3 to add missing wordpath.h include (detected by
sashiko.dev)
- Modified patch 5 to use NSEC_PER_MSEC definition instead of hardcoded
value in an8801r_led_blink_ms_to_hw
- Removed unnecessary RGMII_DELAY_STEP_MASK mask operation in
an8801r_rgmii_rxdelay and an8801r_rgmii_txdelay
- Removed extra empty line in an8801r_led_hw_control_set
- Improved AN8801_RGMII_TX/RXDELAY_DEFAULT definition comments
- Fixed inverted GENMASK arguments in AN8801_WAKE_OUT_WIDTH
definition (detected by sashiko-nipa)
- Fixed possible overflow when writing LED_BLINK_DUR register value
in an8801r_led_blink_set (detected by sashiko-nipa and sashiko.dev)
- Modified the an8801r_handle_interrupt to allow the WAKE_MAGICPKT and
WAKE_LNKCHG interrupts handling in the same call
(detected by sashiko-nipa and sashiko.dev)
- Add extra check in an8801r_set_wol to reject unsupported modes
(detected by sashiko-nipa)
- Fixed supported led trigger detection in an8801r_led_trig_to_hw
(detected by sashiko.dev)
- Fixed possible uninitialized return value in an8801r_of_init_leds
(detected by sashiko-nipa and sashiko.dev)
- Modified patch 6 to fix possible cases where the link mode register value
might not be updated (detected by sashiko-nipa)
- Added new reviewed-by trailers
- Link to v3: https://lore.kernel.org/r/20260512-add-airoha-an8801-support-v3-0-1edb34e363ae@collabora.com
Changes in v3:
- Rebased on net-next (7e0cccae6b45)
- Updated patch 1 to describe the function-enumator property for the
LEDs and its possible values
- Modified patch 2 to add missing includes in air_phy_lib source and
header files
- Split patch 3 in two so that the api call renames in air_en8811h
driver is done in a separate patch
- Simplified return code handling in several functions
- Fixed return code handling in several functions detected by AI
peer-reviews (netdev-ai or sashiko)
- Added additional interrupt enabled check before enabling/disabling
link changed interrupt in an8801r_suspend/resume callbacks
- Fixed register mask for GPIO LED selection register in
an8801r_led_init function
- Fixed potential uninitialized variable in an8801r_led_polarity_set
function
- Fixed LED blink register settings in an8801r_led_blink_set function
- Split an8801r_read_status function implementation in a separate patch
as requested and add comment to describe why the link mode register
needed to be modified after reading the link speed.
- Link to v2: https://lore.kernel.org/r/20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com
Changes in v2:
- Rebased on net-next (d1e59a4697371)
- Fixed dt-bindings to remove the leds property from the required ones and
add wakeup-source as valid property
- Added new reviewed-by trailer for dt_bindings
- Added new patches (2 and 3) to create air_phy_lib, to share common code
between air_en8811h and air_an8801 drivers and use it in air_en8811h.
- Remove custom BuckPBus register accessor functions and definitions from
air_an8801 and use the ones from air_phy_lib. It also fixes a build
issue on v1 due to an uninitialized variable used in
__air_buckpbus_reg_read, that is now removed from driver code
- Added air_an8801_probe function to allocate the newly added private
data structure and detect if the PHY is wakeup capable and the interrupt
can be registered as a wakeup IRQ, and perform the needed actions
- Added an8801r_suspend and an8801r_resume functions to perform specific
actions when WoL is enabled (reset its status, enable/disable the Link
Changed interrupt) and call the genphy_suspend/resume functions if
needed
- Modified an8801r_get_wol to return WoL is not supported if the PHY
device is not wakeup capable
- Modified an8801r_set_wol to return EOPNOTSUPP error code if the PHY
device is not wakeup capable, and to update the wakeup flag according
to WoL mode
- Modified an8801r_config_init to remove EEE disabling and replace
__phy_write use by phy_write_paged
- Reworked an8801r_rgmii_delay_config and its subfunctions to fix a
double return use in PHY_INTERFACE_MODE_RGMII_ID case, replace the
magic value use for default TX and RX delay and handle better the
enable/disable the inserted delays for all RGMII modes
- Merged an8801r_did_interrupt function in an8801r_handle_interrupt
- Modified the an8801r_handle_interrupt processing to process differently
the Magic Packet (to notify system wakeup) and the Link Changed
interrupt (to notify PHY state machine)
- Splitted the reset WoL status part from an8801r_ack_interrupt and fix
an issue that in some random cases made WAKEUP_CTL1 register lose the
Magic Packet WoL settings
- Modified an8801r_of_init_leds function so it does not return an error
if the leds configuration is not present in devicetree
- Removed feature field and add PHY_ALWAYS_CALL_SUSPEND flag in
airoha_driver data structure
- Link to v1: https://lore.kernel.org/r/20260304-add-airoha-an8801-support-v1-0-0ae4ee5a2f9d@collabora.com
---
AngeloGioacchino Del Regno (2):
dt-bindings: net: Add support for Airoha AN8801R GbE PHY
net: phy: Introduce Airoha AN8801R Gigabit Ethernet PHY driver
Louis-Alexis Eyraud (4):
net: phy: Add Airoha phy library for shared code
net: phy: air_phy_lib: Factorize BuckPBus register accessors
net: phy: Rename Airoha common BuckPBus register accessors
net: phy: air_an8801: ensure maximum available speed link use
.../devicetree/bindings/net/airoha,an8801.yaml | 120 ++
drivers/net/phy/Kconfig | 12 +
drivers/net/phy/Makefile | 2 +
drivers/net/phy/air_an8801.c | 1156 ++++++++++++++++++++
drivers/net/phy/air_en8811h.c | 316 +-----
drivers/net/phy/air_phy_lib.c | 213 ++++
drivers/net/phy/air_phy_lib.h | 39 +
7 files changed, 1600 insertions(+), 258 deletions(-)
---
base-commit: 90d03ee2c5dc5f7ee11da90e8eb6868dcbee177b
change-id: 20260303-add-airoha-an8801-support-57d544a4afed
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply
* Re: [PATCH] mips: ralink: mt7621: add missing __iomem
From: Thomas Bogendoerfer @ 2026-05-26 14:50 UTC (permalink / raw)
To: Rosen Penev
Cc: linux-mips, John Crispin, Sergio Paracuellos, Matthias Brugger,
AngeloGioacchino Del Regno, Chuanhong Guo,
open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <20260508042724.1719688-1-rosenp@gmail.com>
On Thu, May 07, 2026 at 09:27:24PM -0700, Rosen Penev wrote:
> raw_readl and writel calls expect pointers annotated with __iomem.
>
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild/202211060456.cnV6IK6G-lkp@intel.com/
> Fixes: cc19db8b312a ("MIPS: ralink: mt7621: do memory detection on KSEG1")
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
> arch/mips/ralink/mt7621.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
> index a4bdda8541c0..ae7b8cfedd5f 100644
> --- a/arch/mips/ralink/mt7621.c
> +++ b/arch/mips/ralink/mt7621.c
> @@ -63,7 +63,7 @@ phys_addr_t mips_cpc_default_phys_base(void)
>
> static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
> {
> - void *dm = (void *)KSEG1ADDR(&detect_magic);
> + void __iomem *dm = (void __iomem *)KSEG1ADDR(&detect_magic);
>
> if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
> return true;
> --
> 2.54.0
applied to mips-next
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply
* Re: [PATCH RFC 00/12] arm64: mediatek: Add M.2 E-key slot on Chromebooks
From: Bartosz Golaszewski @ 2026-05-26 9:48 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
linux-pm, linux-usb, devicetree, linux-mediatek, linux-arm-kernel,
linux-kernel, Manivannan Sadhasivam
In-Reply-To: <CAGXv+5HC3dqgcE3KnKzakHHWFHB6m_X42orOkNUvZvp=SL_O8g@mail.gmail.com>
On Sun, May 24, 2026 at 10:06 AM Chen-Yu Tsai <wenst@chromium.org> wrote:
>
> > >
> > > I expect some discussion on this patch, because a) it adds some
> > > OF-specific code into an otherwise generic (core) driver, and
> > > b) it doesn't yet handle USB 2.0 / 3.x shared ports; it ends up powering
> > > on the port twice, which negates the port reset part.
> > >
> >
> > I understand that you do this because the port device has no OF node
> > assigned. If we wanted to call pwrseq_get() for the port device, is
> > there really no other way to associate it with the correct pwrseq
> > provider?
>
> I suppose we could tie the "port@X" node to the usb port device, but
> AFAIK no other subsystem does this so we would be introducing a new
> pattern.
>
> In the M.2 pwrseq driver, we would have to match by port node instead
> of its parent device node. We may end up with different behavior for
> the USB target vs the other targets.
>
I imagine, we can check the bus type of the parent device to know if
this is USB?
> Also, the "port@X" nodes only exist for the OF graph connections to
> connectors and/or muxes (this series doesn't deal with the latter).
> For directly connected devices, there is a "device@X" child node
> directly under the USB hub node. That node is what gets tied to the
> the USB device.
>
Is this a problem? I don't think I understand what you're saying here.
Bart
^ permalink raw reply
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