* [PATCH] wifi: mt76: mt7996: Fix possible token leak in mt7996_tx_prepare_skb()
From: Lorenzo Bianconi @ 2026-05-31 9:10 UTC (permalink / raw)
To: Felix Fietkau, Ryder Lee, Shayne Chen, Sean Wang,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-wireless, linux-arm-kernel, linux-mediatek,
Lorenzo Bianconi
If link_conf or link_sta lookup fails in mt7996_tx_prepare_skb routine,
mt7996 driver leaks an already allocated tx token. Fix the issue
releasing the token in case of error.
Fixes: 7ef0c7ad735b0 ("wifi: mt76: mt7996: Implement MLD address translation for EAPOL")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/wireless/mediatek/mt76/mt7996/mac.c | 8 ++++++--
drivers/net/wireless/mediatek/mt76/tx.c | 2 +-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index c98446057282..8c56344d211b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -1067,11 +1067,11 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
link_conf = rcu_dereference(vif->link_conf[wcid->link_id]);
if (!link_conf)
- return -EINVAL;
+ goto error_relase_token;
link_sta = rcu_dereference(sta->link[wcid->link_id]);
if (!link_sta)
- return -EINVAL;
+ goto error_relase_token;
dma_sync_single_for_cpu(mdev->dma_dev, tx_info->buf[1].addr,
tx_info->buf[1].len, DMA_TO_DEVICE);
@@ -1176,6 +1176,10 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
tx_info->nbuf = MT_CT_DMA_BUF_NUM;
return 0;
+
+error_relase_token:
+ mt76_token_release(mdev, id, NULL);
+ return -EINVAL;
}
u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
diff --git a/drivers/net/wireless/mediatek/mt76/tx.c b/drivers/net/wireless/mediatek/mt76/tx.c
index 22f9690634c9..f96d9c471853 100644
--- a/drivers/net/wireless/mediatek/mt76/tx.c
+++ b/drivers/net/wireless/mediatek/mt76/tx.c
@@ -933,7 +933,7 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
#endif
}
- if (dev->token_count < dev->token_size - MT76_TOKEN_FREE_THR &&
+ if (wake && dev->token_count < dev->token_size - MT76_TOKEN_FREE_THR &&
dev->phy.q_tx[0]->blocked)
*wake = true;
---
base-commit: 4913f44167cf35a9536e9eec7352e15b2de0c573
change-id: 20260531-mt7996_tx_prepare_skb-token-leack-82e240d8c66f
Best regards,
--
Lorenzo Bianconi <lorenzo@kernel.org>
^ permalink raw reply related
* [PATCH v2 3/4] regulator: Add driver for MediaTek MT6328 PMIC regulators
From: Yassine Oudjana via B4 Relay @ 2026-05-31 9:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Flora Fu, Alexandre Mergnat,
Liam Girdwood, Mark Brown, Dmitry Torokhov
Cc: Yassine Oudjana, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-input
In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add a driver for the regulators on the MT6328 PMIC.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6328-regulator.c | 500 +++++++++++++++++++++++++++++
include/linux/regulator/mt6328-regulator.h | 49 +++
4 files changed, 559 insertions(+)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index a54a549196fe..a4f0c21aa6ea 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -919,6 +919,15 @@ config REGULATOR_MT6323
This driver supports the control of different power rails of device
through regulator interface.
+config REGULATOR_MT6328
+ tristate "MediaTek MT6328 PMIC"
+ depends on MFD_MT6397
+ help
+ Say y here to select this option to enable the power regulator of
+ MediaTek MT6328 PMIC.
+ This driver supports the control of different power rails of device
+ through regulator interface.
+
config REGULATOR_MT6331
tristate "MediaTek MT6331 PMIC"
depends on MFD_MT6397
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 134eee274dbf..4d1e40f0f911 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -109,6 +109,7 @@ obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o
obj-$(CONFIG_REGULATOR_MT6315) += mt6316-regulator.o
obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
+obj-$(CONFIG_REGULATOR_MT6328) += mt6328-regulator.o
obj-$(CONFIG_REGULATOR_MT6331) += mt6331-regulator.o
obj-$(CONFIG_REGULATOR_MT6332) += mt6332-regulator.o
obj-$(CONFIG_REGULATOR_MT6357) += mt6357-regulator.o
diff --git a/drivers/regulator/mt6328-regulator.c b/drivers/regulator/mt6328-regulator.c
new file mode 100644
index 000000000000..a0e4226ffe37
--- /dev/null
+++ b/drivers/regulator/mt6328-regulator.c
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek MT6328 regulator driver
+ * Based on MT6323 driver.
+ *
+ * Copyright (c) 2016 MediaTek Inc.
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/mt6397/core.h>
+#include <linux/mfd/mt6328/registers.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/mt6328-regulator.h>
+#include <linux/regulator/of_regulator.h>
+
+#define MT6328_LDO_TABLE_MODE_NORMAL 0
+#define MT6328_LDO_TABLE_MODE_LP 1
+
+/*
+ * MT6328 regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ * @qi: Mask for query enable signal status of regulators
+ * @vselon_reg: Register sections for hardware control mode of bucks
+ * @vselctrl_reg: Register for controlling the buck control mode.
+ * @vselctrl_mask: Mask for query buck's voltage control mode.
+ */
+struct mt6328_regulator_info {
+ struct regulator_desc desc;
+ u32 qi;
+ u32 vselon_reg;
+ u32 vselctrl_reg;
+ u32 vselctrl_mask;
+ u32 modeset_reg;
+ u32 modeset_mask;
+};
+
+#define MT6328_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
+ vosel, vosel_mask, voselon, vosel_ctrl) \
+[MT6328_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6328_volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6328_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = (max - min)/step + 1, \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(0), \
+ }, \
+ .qi = BIT(13), \
+ .vselon_reg = voselon, \
+ .vselctrl_reg = vosel_ctrl, \
+ .vselctrl_mask = BIT(1), \
+}
+
+#define MT6328_LDO_RANGE(match, vreg, min, max, step, volt_ranges, \
+ enreg, enbit, vosel, vosel_mask, _modeset_reg, \
+ _modeset_mask) \
+[MT6328_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6328_volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6328_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = (max - min)/step + 1, \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(enbit), \
+ }, \
+ .qi = BIT(15), \
+ .modeset_reg = _modeset_reg, \
+ .modeset_mask = _modeset_mask, \
+}
+
+#define MT6328_LDO_TABLE(match, vreg, ldo_volt_table, enreg, enbit, \
+ vosel, vosel_mask, _modeset_reg, _modeset_mask)\
+[MT6328_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6328_volt_table_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6328_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ARRAY_SIZE(ldo_volt_table), \
+ .volt_table = ldo_volt_table, \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(enbit), \
+ }, \
+ .qi = BIT(15), \
+ .modeset_reg = _modeset_reg, \
+ .modeset_mask = _modeset_mask, \
+}
+
+#define MT6328_LDO_TABLE_SINGLE_MODE(match, vreg, ldo_volt_table, enreg,\
+ enbit, vosel, vosel_mask) \
+[MT6328_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6328_volt_table_single_mode_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6328_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ARRAY_SIZE(ldo_volt_table), \
+ .volt_table = ldo_volt_table, \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(enbit), \
+ }, \
+ .qi = BIT(15), \
+ .modeset_reg = 0, \
+ .modeset_mask = 0, \
+}
+
+#define MT6328_REG_FIXED(match, vreg, enreg, enbit, volt, \
+ _modeset_reg, _modeset_mask) \
+[MT6328_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6328_volt_fixed_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6328_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = 1, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(enbit), \
+ .min_uV = volt, \
+ }, \
+ .qi = BIT(15), \
+ .modeset_reg = _modeset_reg, \
+ .modeset_mask = _modeset_mask, \
+}
+
+#define MT6328_REG_FIXED_SINGLE_MODE(match, vreg, enreg, enbit, volt, \
+ _modeset_reg, _modeset_mask) \
+[MT6328_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6328_volt_fixed_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6328_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = 1, \
+ .enable_reg = enreg, \
+ .enable_mask = BIT(enbit), \
+ .min_uV = volt, \
+ }, \
+ .qi = BIT(15), \
+ .modeset_reg = _modeset_reg, \
+ .modeset_mask = _modeset_mask, \
+}
+
+static const struct linear_range buck_volt_range1[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000)
+};
+
+static const struct linear_range buck_volt_range2[] = {
+ REGULATOR_LINEAR_RANGE(600000, 0, 0x7f, 6250)
+};
+
+static const struct linear_range buck_volt_range3[] = {
+ REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 6250)
+};
+
+static const unsigned int ldo_volt_table1[] = {
+ 1500000, 1800000, 2500000, 2800000
+};
+
+static const unsigned int ldo_volt_table2[] = {
+ 3300000, 3400000, 3500000, 3600000
+};
+
+static const unsigned int ldo_volt_table3[] = {
+ 0, 0, 0, 1800000, 1900000, 2000000, 2100000, 2200000
+};
+
+static const unsigned int ldo_volt_table4[] = {
+ 1700000, 1800000, 1860000, 2760000, 3000000, 3100000
+};
+
+static const unsigned int ldo_volt_table5[] = {
+ 1800000, 2900000, 3000000, 3300000
+};
+
+static const unsigned int ldo_volt_table6[] = {
+ 2900000, 3000000, 3300000
+};
+
+static const unsigned int ldo_volt_table7[] = {
+ 2500000, 2900000, 3000000, 3300000
+};
+
+static const unsigned int ldo_volt_table8[] = {
+ 1300000, 1800000, 2900000, 3300000
+};
+
+static const unsigned int ldo_volt_table9[] = {
+ 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000
+};
+
+static const unsigned int ldo_volt_table10[] = {
+ 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000
+};
+
+static const unsigned int ldo_volt_table11[] = {
+ 900000, 1000000, 1100000, 1200000, 1300000, 1500000
+};
+
+static const unsigned int ldo_volt_table12[] = {
+ 1200000, 1300000, 1500000, 1800000, 1825000
+};
+
+static const unsigned int ldo_volt_table13[] = {
+ 1200000, 1300000, 1500000, 1800000
+};
+
+static const unsigned int ldo_volt_table14[] = {
+ 1240000, 1390000, 1540000
+};
+
+static const struct linear_range ldo_volt_range1[] = {
+ REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250)
+};
+
+static int mt6328_get_status(struct regulator_dev *rdev)
+{
+ int ret;
+ u32 regval;
+ struct mt6328_regulator_info *info = rdev_get_drvdata(rdev);
+
+ ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val);
+ if (ret != 0) {
+ dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
+ return ret;
+ }
+
+ return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
+}
+
+static int mt6328_ldo_table_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+ int ret, val = 0;
+ struct mt6328_regulator_info *info = rdev_get_drvdata(rdev);
+
+ switch (mode) {
+ case REGULATOR_MODE_STANDBY:
+ val = MT6328_LDO_TABLE_MODE_LP;
+ break;
+ case REGULATOR_MODE_NORMAL:
+ val = MT6328_LDO_TABLE_MODE_NORMAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ val <<= ffs(info->modeset_mask) - 1;
+
+ ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
+ info->modeset_mask, val);
+
+ return ret;
+}
+
+static unsigned int mt6328_ldo_table_get_mode(struct regulator_dev *rdev)
+{
+ unsigned int val;
+ unsigned int mode;
+ int ret;
+ struct mt6328_regulator_info *info = rdev_get_drvdata(rdev);
+
+ ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
+ if (ret < 0)
+ return ret;
+
+ val &= info->modeset_mask;
+ val >>= ffs(info->modeset_mask) - 1;
+
+ if (val & 0x1)
+ mode = REGULATOR_MODE_STANDBY;
+ else
+ mode = REGULATOR_MODE_NORMAL;
+
+ return mode;
+}
+
+static const struct regulator_ops mt6328_volt_range_ops = {
+ .list_voltage = regulator_list_voltage_linear_range,
+ .map_voltage = regulator_map_voltage_linear_range,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6328_get_status,
+};
+
+static const struct regulator_ops mt6328_volt_table_ops = {
+ .list_voltage = regulator_list_voltage_table,
+ .map_voltage = regulator_map_voltage_iterate,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6328_get_status,
+ .set_mode = mt6328_ldo_table_set_mode,
+ .get_mode = mt6328_ldo_table_get_mode,
+};
+
+static const struct regulator_ops mt6328_volt_table_single_mode_ops = {
+ .list_voltage = regulator_list_voltage_table,
+ .map_voltage = regulator_map_voltage_iterate,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6328_get_status,
+};
+
+static const struct regulator_ops mt6328_volt_fixed_ops = {
+ .list_voltage = regulator_list_voltage_linear,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6328_get_status,
+ .set_mode = mt6328_ldo_table_set_mode,
+ .get_mode = mt6328_ldo_table_get_mode,
+};
+
+/* The array is indexed by id(MT6328_ID_XXX) */
+static struct mt6328_regulator_info mt6328_regulators[] = {
+ MT6328_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, buck_volt_range1, MT6328_VPA_CON9,
+ MT6328_VPA_CON11, 0x3f, MT6328_VPA_CON12, MT6328_VPA_CON7),
+ MT6328_BUCK("buck_vproc", VPROC, 600000, 1393750, 6250, buck_volt_range2, MT6328_VPROC_CON9,
+ MT6328_VPA_CON11, 0x7f, MT6328_VPROC_CON12, MT6328_VPROC_CON7),
+ MT6328_BUCK("buck_vcore1", VCORE1, 600000, 1393750, 6250, buck_volt_range2,
+ MT6328_VCORE1_CON9, MT6328_VCORE1_CON11, 0x7f, MT6328_VCORE1_CON12,
+ MT6328_VCORE1_CON7),
+ MT6328_BUCK("buck_vsys22", VSYS22, 1200000, 1993750, 6250, buck_volt_range3,
+ MT6328_VSYS22_CON9, MT6328_VSYS22_CON11, 0x7f, MT6328_VSYS22_CON12,
+ MT6328_VSYS22_CON7),
+ MT6328_BUCK("buck_vlte", VLTE, 600000, 1393750, 6250, buck_volt_range2, MT6328_VLTE_CON9,
+ MT6328_VLTE_CON11, 0x7f, MT6328_VLTE_CON12, MT6328_VLTE_CON7),
+ MT6328_REG_FIXED("ldo_vaux18", VAUX18, MT6328_VAUX18_CON0, 1, 1800000, MT6328_VAUX18_CON0,
+ BIT(0)),
+ MT6328_REG_FIXED("ldo_vtcxo_0", VTCXO_0, MT6328_VTCXO_0_CON0, 1, 2800000,
+ MT6328_VTCXO_0_CON0, BIT(0)),
+ MT6328_REG_FIXED("ldo_vtcxo_1", VTCXO_1, MT6328_VTCXO_1_CON0, 1, 2800000,
+ MT6328_VTCXO_1_CON0, BIT(0)),
+ MT6328_REG_FIXED("ldo_vaud28", VAUD28, MT6328_VAUD28_CON0, 1, 2800000, MT6328_VAUD28_CON0,
+ BIT(0)),
+ MT6328_REG_FIXED("ldo_vcn28", VCN28, MT6328_VCN28_CON0, 1, 2800000, MT6328_VCN28_CON0,
+ BIT(0)),
+ MT6328_LDO_TABLE_SINGLE_MODE("ldo_vcama", VCAMA, ldo_volt_table1, MT6328_VCAMA_CON0, 1,
+ MT6328_ADLDO_ANA_CON5, 0x30),
+ MT6328_LDO_TABLE("ldo_vcn33_bt", VCN33_BT, ldo_volt_table2, MT6328_VCN33_CON2, 1,
+ MT6328_ADLDO_ANA_CON6, 0x70, MT6328_VCN33_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vcn33_wifi", VCN33_WIFI, ldo_volt_table2, MT6328_VCN33_CON1, 1,
+ MT6328_ADLDO_ANA_CON6, 0x70, MT6328_VCN33_CON0, BIT(0)),
+ MT6328_REG_FIXED("ldo_vusb33", VUSB33, MT6328_VUSB33_CON0, 1, 3300000, MT6328_VUSB33_CON0,
+ BIT(0)),
+ MT6328_LDO_TABLE("ldo_vefuse", VEFUSE, ldo_volt_table3, MT6328_VEFUSE_CON0, 1,
+ MT6328_ADLDO_ANA_CON8, 0x70, MT6328_VEFUSE_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vsim1", VSIM1, ldo_volt_table4, MT6328_VSIM1_CON0, 1,
+ MT6328_ADLDO_ANA_CON9, 0x70, MT6328_VSIM1_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vsim2", VSIM2, ldo_volt_table4, MT6328_VSIM2_CON0, 1,
+ MT6328_ADLDO_ANA_CON10, 0x70, MT6328_VSIM2_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vemc_3v3", VEMC_3V3, ldo_volt_table5, MT6328_VEMC_3V3_CON0, 1,
+ MT6328_ADLDO_ANA_CON11, 0x30, MT6328_VEMC_3V3_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vmch", VMCH, ldo_volt_table6, MT6328_VMCH_CON0, 1,
+ MT6328_ADLDO_ANA_CON12, 0x30, MT6328_VMCH_CON0, BIT(0)),
+ MT6328_REG_FIXED("ldo_vtref", VTREF, MT6328_VTREF_CON0, 1, 1800000, 0, 0),
+ MT6328_LDO_TABLE("ldo_vmc", VMC, ldo_volt_table5, MT6328_VMC_CON0, 1, MT6328_DLDO_ANA_CON0,
+ 0x30, MT6328_VMC_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vcamaf", VCAMAF, ldo_volt_table9, MT6328_VCAMAF_CON0, 1,
+ MT6328_DLDO_ANA_CON1, 0x70, MT6328_VCAMAF_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vibr", VIBR, ldo_volt_table9, MT6328_VIBR_CON0, 1,
+ MT6328_DLDO_ANA_CON2, 0x70, MT6328_VIBR_CON0, BIT(0)),
+ MT6328_REG_FIXED("ldo_vio28", VIO28, MT6328_VIO28_CON0, 1, 2800000, MT6328_VIO28_CON0,
+ BIT(0)),
+ MT6328_LDO_TABLE("ldo_vgp1", VGP1, ldo_volt_table10, MT6328_VGP1_CON0, 1,
+ MT6328_DLDO_ANA_CON4, 0x70, MT6328_VGP1_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vcamd", VCAMD, ldo_volt_table11, MT6328_VCAM_CON0, 1,
+ MT6328_SLDO_ANA_CON2, 0x70, MT6328_VCAM_CON0, BIT(0)),
+ MT6328_REG_FIXED("ldo_vrf18_0", VRF18_0, MT6328_VRF18_0_CON0, 1, 1825000,
+ MT6328_VRF18_0_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vrf18_1", VRF18_1, ldo_volt_table12, MT6328_VRF18_1_CON0, 1,
+ MT6328_SLDO_ANA_CON4, 0x30, MT6328_VRF18_1_CON0, BIT(0)),
+ MT6328_REG_FIXED("ldo_vio18", VIO18, MT6328_VIO18_CON0, 1, 1800000, MT6328_VIO18_CON0,
+ BIT(0)),
+ MT6328_REG_FIXED("ldo_vcn18", VCN18, MT6328_VCN18_CON0, 1, 1800000, MT6328_VCN18_CON0,
+ BIT(0)),
+ MT6328_LDO_TABLE("ldo_vcamio", VCAMIO, ldo_volt_table13, MT6328_VCAMIO_CON0, 1,
+ MT6328_SLDO_ANA_CON7, 0x30, MT6328_VCAMIO_CON0, BIT(0)),
+ MT6328_LDO_TABLE("ldo_vcamio", VCAMIO, ldo_volt_table13, MT6328_VCAMIO_CON0, 1,
+ MT6328_SLDO_ANA_CON7, 0x30, MT6328_VCAMIO_CON0, BIT(0)),
+ MT6328_LDO_RANGE("ldo_vsram", VSRAM, 700000, 1493750, 6250, ldo_volt_range1,
+ MT6328_VSRAM_CON9, 1, MT6328_SLDO_ANA_CON9, 0x7f, MT6328_LDO_VSRAM_CON0,
+ BIT(0)),
+ MT6328_LDO_TABLE("ldo_vm", VM, ldo_volt_table14, MT6328_VM_CON0, 1, MT6328_SLDO_ANA_CON0,
+ 0x3, MT6328_VM_CON0, BIT(0)),
+};
+
+static int mt6328_set_buck_vosel_reg(struct platform_device *pdev)
+{
+ struct mt6397_chip *mt6328 = dev_get_drvdata(pdev->dev.parent);
+ int i;
+ u32 regval;
+
+ for (i = 0; i < MT6328_MAX_REGULATOR; i++) {
+ if (mt6328_regulators[i].vselctrl_reg) {
+ if (regmap_read(mt6328->regmap,
+ mt6328_regulators[i].vselctrl_reg,
+ ®val) < 0) {
+ dev_err(&pdev->dev,
+ "Failed to read buck ctrl\n");
+ return -EIO;
+ }
+
+ if (regval & mt6328_regulators[i].vselctrl_mask) {
+ mt6328_regulators[i].desc.vsel_reg =
+ mt6328_regulators[i].vselon_reg;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int mt6328_regulator_probe(struct platform_device *pdev)
+{
+ struct mt6397_chip *mt6328 = dev_get_drvdata(pdev->dev.parent);
+ struct regulator_config config = {};
+ struct regulator_dev *rdev;
+ int i;
+
+ /* Query buck controller to select activated voltage register part */
+ if (mt6328_set_buck_vosel_reg(pdev))
+ return -EIO;
+
+ for (i = 0; i < MT6328_MAX_REGULATOR; i++) {
+ config.dev = &pdev->dev;
+ config.driver_data = &mt6328_regulators[i];
+ config.regmap = mt6328->regmap;
+ rdev = devm_regulator_register(&pdev->dev,
+ &mt6328_regulators[i].desc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "failed to register %s\n",
+ mt6328_regulators[i].desc.name);
+ return PTR_ERR(rdev);
+ }
+ }
+ return 0;
+}
+
+static const struct platform_device_id mt6328_platform_ids[] = {
+ { "mt6328-regulator" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(platform, mt6328_platform_ids);
+
+static struct platform_driver mt6328_regulator_driver = {
+ .driver = {
+ .name = "mt6328-regulator",
+ },
+ .probe = mt6328_regulator_probe,
+ .id_table = mt6328_platform_ids,
+};
+
+module_platform_driver(mt6328_regulator_driver);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6328 PMIC");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/regulator/mt6328-regulator.h b/include/linux/regulator/mt6328-regulator.h
new file mode 100644
index 000000000000..0f82aa88493b
--- /dev/null
+++ b/include/linux/regulator/mt6328-regulator.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#ifndef __LINUX_REGULATOR_MT6328_H
+#define __LINUX_REGULATOR_MT6328_H
+
+enum {
+ MT6328_ID_VPA = 0,
+ MT6328_ID_VPROC,
+ MT6328_ID_VCORE1,
+ MT6328_ID_VSYS22,
+ MT6328_ID_VLTE,
+ MT6328_ID_VAUX18,
+ MT6328_ID_VTCXO_0,
+ MT6328_ID_VTCXO_1,
+ MT6328_ID_VAUD28,
+ MT6328_ID_VCN28,
+ MT6328_ID_VCAMA,
+ MT6328_ID_VCN33_BT,
+ MT6328_ID_VCN33_WIFI,
+ MT6328_ID_VUSB33,
+ MT6328_ID_VEFUSE,
+ MT6328_ID_VSIM1,
+ MT6328_ID_VSIM2,
+ MT6328_ID_VEMC_3V3,
+ MT6328_ID_VMCH,
+ MT6328_ID_VTREF,
+ MT6328_ID_VMC,
+ MT6328_ID_VCAMAF,
+ MT6328_ID_VIBR,
+ MT6328_ID_VIO28,
+ MT6328_ID_VGP1,
+ MT6328_ID_VCAMD,
+ MT6328_ID_VRF18_0,
+ MT6328_ID_VRF18_1,
+ MT6328_ID_VIO18,
+ MT6328_ID_VCN18,
+ MT6328_ID_VCAMIO,
+ MT6328_ID_VSRAM,
+ MT6328_ID_VM,
+ MT6328_ID_RG_MAX,
+};
+
+#define MT6328_MAX_REGULATOR MT6328_ID_RG_MAX
+
+#endif /* __LINUX_REGULATOR_MT6328_H */
--
2.54.0
^ permalink raw reply related
* [PATCH v2 4/4] Input: mtk-pmic-keys - Add support for MT6328
From: Yassine Oudjana via B4 Relay @ 2026-05-31 9:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Flora Fu, Alexandre Mergnat,
Liam Girdwood, Mark Brown, Dmitry Torokhov
Cc: Yassine Oudjana, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-input
In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add a compatible string and related data for the PMIC keys on the
MT6328 PMIC.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/input/keyboard/mtk-pmic-keys.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboard/mtk-pmic-keys.c
index c78d9f6d97c4..6aaca67e7703 100644
--- a/drivers/input/keyboard/mtk-pmic-keys.c
+++ b/drivers/input/keyboard/mtk-pmic-keys.c
@@ -9,6 +9,7 @@
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/mt6323/registers.h>
+#include <linux/mfd/mt6328/registers.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6357/registers.h>
#include <linux/mfd/mt6358/registers.h>
@@ -80,6 +81,17 @@ static const struct mtk_pmic_regs mt6323_regs = {
.rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
};
+static const struct mtk_pmic_regs mt6328_regs = {
+ .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
+ MTK_PMIC_KEYS_REGS(MT6328_TOPSTATUS,
+ 0x2, MT6328_INT_MISC_CON, 0x4, MTK_PMIC_PWRKEY_RST),
+ .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
+ MTK_PMIC_KEYS_REGS(MT6328_TOPSTATUS,
+ 0x4, MT6328_INT_MISC_CON, 0x2, MTK_PMIC_HOMEKEY_RST),
+ .pmic_rst_reg = MT6328_TOP_RST_MISC,
+ .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
+};
+
static const struct mtk_pmic_regs mt6331_regs = {
.keys_regs[MTK_PMIC_PWRKEY_INDEX] =
MTK_PMIC_KEYS_REGS(MT6331_TOPSTATUS, 0x2,
@@ -304,6 +316,9 @@ static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = {
}, {
.compatible = "mediatek,mt6323-keys",
.data = &mt6323_regs,
+ }, {
+ .compatible = "mediatek,mt6328-keys",
+ .data = &mt6328_regs,
}, {
.compatible = "mediatek,mt6331-keys",
.data = &mt6331_regs,
--
2.54.0
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: mediatek: pwrap: Add MT6735 compatible
From: Yassine Oudjana via B4 Relay @ 2026-05-31 9:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Flora Fu, Alexandre Mergnat,
Liam Girdwood, Mark Brown, Dmitry Torokhov
Cc: Yassine Oudjana, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-input
In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add a compatible string for MT6735 PMIC wrapper.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
index e7c4a3984c60..3a5fd46ce282 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
@@ -31,6 +31,7 @@ properties:
- items:
- enum:
- mediatek,mt2701-pwrap
+ - mediatek,mt6735-pwrap
- mediatek,mt6765-pwrap
- mediatek,mt6779-pwrap
- mediatek,mt6795-pwrap
--
2.54.0
^ permalink raw reply related
* [PATCH v2 2/4] soc: mediatek: pwrap: Add support for MT6735 and MT6328 SoC/PMIC pair
From: Yassine Oudjana via B4 Relay @ 2026-05-31 9:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Flora Fu, Alexandre Mergnat,
Liam Girdwood, Mark Brown, Dmitry Torokhov
Cc: Yassine Oudjana, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-input
In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add register definitions and configuration for the MT6735 SoC and the
MT6328 PMIC which are commonly paired and communicate through the PMIC
wrapper.
Note that the PMIC wrapper on MT6735M has a slightly different register
map and is therefore NOT compatible with MT6735.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 177 ++++++++++++++++++++++++++++++++++-
1 file changed, 174 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 0bcd85826375..0f14dca5609d 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -3,6 +3,7 @@
* Copyright (c) 2014 MediaTek Inc.
* Author: Flora Fu, MediaTek
*/
+
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -100,7 +101,7 @@ enum dew_regs {
PWRAP_DEW_CIPHER_MODE,
PWRAP_DEW_CIPHER_SWRST,
- /* MT6323 only regs */
+ /* MT6323 and MT6328 only regs */
PWRAP_DEW_CIPHER_EN,
PWRAP_DEW_RDDMY_NO,
@@ -121,8 +122,10 @@ enum dew_regs {
PWRAP_RG_SPI_CON13,
PWRAP_SPISLV_KEY,
- /* MT6359 only regs */
+ /* MT6359 and MT6328 only regs */
PWRAP_DEW_CRC_SWRST,
+
+ /* MT6359 only regs */
PWRAP_DEW_RG_EN_RECORD,
PWRAP_DEW_RECORD_CMD0,
PWRAP_DEW_RECORD_CMD1,
@@ -171,6 +174,23 @@ static const u32 mt6323_regs[] = {
[PWRAP_DEW_RDDMY_NO] = 0x01a4,
};
+static const u32 mt6328_regs[] = {
+ [PWRAP_DEW_DIO_EN] = 0x02d4,
+ [PWRAP_DEW_READ_TEST] = 0x02d6,
+ [PWRAP_DEW_WRITE_TEST] = 0x02d8,
+ [PWRAP_DEW_CRC_SWRST] = 0x02da,
+ [PWRAP_DEW_CRC_EN] = 0x02dc,
+ [PWRAP_DEW_CRC_VAL] = 0x02de,
+ [PWRAP_DEW_MON_GRP_SEL] = 0x02e0,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x02e2,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x02e4,
+ [PWRAP_DEW_CIPHER_EN] = 0x02e6,
+ [PWRAP_DEW_CIPHER_RDY] = 0x02e8,
+ [PWRAP_DEW_CIPHER_MODE] = 0x02ea,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x02ec,
+ [PWRAP_DEW_RDDMY_NO] = 0x02ee,
+};
+
static const u32 mt6331_regs[] = {
[PWRAP_DEW_DIO_EN] = 0x018c,
[PWRAP_DEW_READ_TEST] = 0x018e,
@@ -394,7 +414,7 @@ enum pwrap_regs {
PWRAP_ADC_RDATA_ADDR1,
PWRAP_ADC_RDATA_ADDR2,
- /* MT7622 only regs */
+ /* MT7622 and MT6735 only regs */
PWRAP_STA,
PWRAP_CLR,
PWRAP_DVFS_ADR8,
@@ -417,6 +437,8 @@ enum pwrap_regs {
PWRAP_ADC_RDATA_ADDR,
PWRAP_GPS_STA,
PWRAP_SW_RST,
+
+ /* MT7622 only regs */
PWRAP_DVFS_STEP_CTRL0,
PWRAP_DVFS_STEP_CTRL1,
PWRAP_DVFS_STEP_CTRL2,
@@ -481,6 +503,13 @@ enum pwrap_regs {
/* MT8516 only regs */
PWRAP_OP_TYPE,
PWRAP_MSB_FIRST,
+
+ /* MT6735 only regs */
+ PWRAP_WACS3_EN,
+ PWRAP_INIT_DONE3,
+ PWRAP_WACS3_CMD,
+ PWRAP_WACS3_RDATA,
+ PWRAP_WACS3_VLDCLR,
};
static const int mt2701_regs[] = {
@@ -569,6 +598,119 @@ static const int mt2701_regs[] = {
[PWRAP_ADC_RDATA_ADDR2] = 0x154,
};
+static const int mt6735_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SIDLY] = 0xc,
+ [PWRAP_RDDMY] = 0x10,
+ [PWRAP_SI_CK_CON] = 0x14,
+ [PWRAP_CSHEXT_WRITE] = 0x18,
+ [PWRAP_CSHEXT_READ] = 0x1c,
+ [PWRAP_CSLEXT_START] = 0x20,
+ [PWRAP_CSLEXT_END] = 0x24,
+ [PWRAP_STAUPD_PRD] = 0x28,
+ [PWRAP_STAUPD_GRPEN] = 0x2c,
+ [PWRAP_EINT_STA0_ADR] = 0x30,
+ [PWRAP_EINT_STA1_ADR] = 0x34,
+ [PWRAP_STA] = 0x38,
+ [PWRAP_CLR] = 0x3c,
+ [PWRAP_STAUPD_MAN_TRIG] = 0x40,
+ [PWRAP_STAUPD_STA] = 0x44,
+ [PWRAP_WRAP_STA] = 0x48,
+ [PWRAP_HARB_INIT] = 0x4c,
+ [PWRAP_HARB_HPRIO] = 0x50,
+ [PWRAP_HIPRIO_ARB_EN] = 0x54,
+ [PWRAP_HARB_STA0] = 0x58,
+ [PWRAP_HARB_STA1] = 0x5c,
+ [PWRAP_MAN_EN] = 0x60,
+ [PWRAP_MAN_CMD] = 0x64,
+ [PWRAP_MAN_RDATA] = 0x68,
+ [PWRAP_MAN_VLDCLR] = 0x6c,
+ [PWRAP_WACS0_EN] = 0x70,
+ [PWRAP_INIT_DONE0] = 0x74,
+ [PWRAP_WACS0_CMD] = 0x78,
+ [PWRAP_WACS0_RDATA] = 0x7c,
+ [PWRAP_WACS0_VLDCLR] = 0x80,
+ [PWRAP_WACS1_EN] = 0x84,
+ [PWRAP_INIT_DONE1] = 0x88,
+ [PWRAP_WACS1_CMD] = 0x8c,
+ [PWRAP_WACS1_RDATA] = 0x90,
+ [PWRAP_WACS1_VLDCLR] = 0x94,
+ [PWRAP_WACS2_EN] = 0x98,
+ [PWRAP_INIT_DONE2] = 0x9c,
+ [PWRAP_WACS2_CMD] = 0xa0,
+ [PWRAP_WACS2_RDATA] = 0xa4,
+ [PWRAP_WACS2_VLDCLR] = 0xa8,
+ [PWRAP_WACS3_EN] = 0xac,
+ [PWRAP_INIT_DONE3] = 0xb0,
+ [PWRAP_WACS3_CMD] = 0xb4,
+ [PWRAP_WACS3_RDATA] = 0xb8,
+ [PWRAP_WACS3_VLDCLR] = 0xbc,
+ [PWRAP_INT_EN] = 0xc0,
+ [PWRAP_INT_FLG_RAW] = 0xc4,
+ [PWRAP_INT_FLG] = 0xc8,
+ [PWRAP_INT_CLR] = 0xcc,
+ [PWRAP_SIG_ADR] = 0xd0,
+ [PWRAP_SIG_MODE] = 0xd4,
+ [PWRAP_SIG_VALUE] = 0xd8,
+ [PWRAP_SIG_ERRVAL] = 0xdc,
+ [PWRAP_CRC_EN] = 0xe0,
+ [PWRAP_TIMER_EN] = 0xe4,
+ [PWRAP_TIMER_STA] = 0xe8,
+ [PWRAP_WDT_UNIT] = 0xec,
+ [PWRAP_WDT_SRC_EN] = 0xf0,
+ [PWRAP_WDT_FLG] = 0xf4,
+ [PWRAP_DEBUG_INT_SEL] = 0xf8,
+ [PWRAP_DVFS_ADR0] = 0xfc,
+ [PWRAP_DVFS_WDATA0] = 0x100,
+ [PWRAP_DVFS_ADR1] = 0x104,
+ [PWRAP_DVFS_WDATA1] = 0x108,
+ [PWRAP_DVFS_ADR2] = 0x10c,
+ [PWRAP_DVFS_WDATA2] = 0x110,
+ [PWRAP_DVFS_ADR3] = 0x114,
+ [PWRAP_DVFS_WDATA3] = 0x118,
+ [PWRAP_DVFS_ADR4] = 0x11c,
+ [PWRAP_DVFS_WDATA4] = 0x120,
+ [PWRAP_DVFS_ADR5] = 0x124,
+ [PWRAP_DVFS_WDATA5] = 0x128,
+ [PWRAP_DVFS_ADR6] = 0x12c,
+ [PWRAP_DVFS_WDATA6] = 0x130,
+ [PWRAP_DVFS_ADR7] = 0x134,
+ [PWRAP_DVFS_WDATA7] = 0x138,
+ [PWRAP_DVFS_ADR8] = 0x13c,
+ [PWRAP_DVFS_WDATA8] = 0x140,
+ [PWRAP_DVFS_ADR9] = 0x144,
+ [PWRAP_DVFS_WDATA9] = 0x148,
+ [PWRAP_DVFS_ADR10] = 0x14c,
+ [PWRAP_DVFS_WDATA10] = 0x150,
+ [PWRAP_DVFS_ADR11] = 0x154,
+ [PWRAP_DVFS_WDATA11] = 0x158,
+ [PWRAP_DVFS_ADR12] = 0x15c,
+ [PWRAP_DVFS_WDATA12] = 0x160,
+ [PWRAP_DVFS_ADR13] = 0x164,
+ [PWRAP_DVFS_WDATA13] = 0x168,
+ [PWRAP_DVFS_ADR14] = 0x16c,
+ [PWRAP_DVFS_WDATA14] = 0x170,
+ [PWRAP_DVFS_ADR15] = 0x174,
+ [PWRAP_DVFS_WDATA15] = 0x178,
+ [PWRAP_SPMINF_STA] = 0x17c,
+ [PWRAP_CIPHER_KEY_SEL] = 0x180,
+ [PWRAP_CIPHER_IV_SEL] = 0x184,
+ [PWRAP_CIPHER_EN] = 0x188,
+ [PWRAP_CIPHER_RDY] = 0x18c,
+ [PWRAP_CIPHER_MODE] = 0x190,
+ [PWRAP_CIPHER_SWRST] = 0x194,
+ [PWRAP_DCM_EN] = 0x198,
+ [PWRAP_DCM_DBC_PRD] = 0x19c,
+ [PWRAP_EXT_CK] = 0x1a0,
+ [PWRAP_ADC_CMD_ADDR] = 0x1a4,
+ [PWRAP_PWRAP_ADC_CMD] = 0x1a8,
+ [PWRAP_ADC_RDATA_ADDR] = 0x1ac,
+ [PWRAP_GPS_STA] = 0x1b0,
+ [PWRAP_SW_RST] = 0x1b4,
+};
+
static const int mt6765_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
@@ -1302,6 +1444,7 @@ static const int mt8186_regs[] = {
enum pmic_type {
PMIC_MT6323,
+ PMIC_MT6328,
PMIC_MT6331,
PMIC_MT6332,
PMIC_MT6351,
@@ -1314,6 +1457,7 @@ enum pmic_type {
enum pwrap_type {
PWRAP_MT2701,
+ PWRAP_MT6735,
PWRAP_MT6765,
PWRAP_MT6779,
PWRAP_MT6795,
@@ -1733,6 +1877,10 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
{
switch (wrp->master->type) {
+ case PWRAP_MT6735:
+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
+ pwrap_init_chip_select_ext(wrp, 0, 6, 0, 0);
+ break;
case PWRAP_MT6795:
if (wrp->slave->type == PMIC_MT6331) {
const u32 *dew_regs = wrp->slave->dew_regs;
@@ -1839,6 +1987,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
break;
case PWRAP_MT2701:
+ case PWRAP_MT6735:
case PWRAP_MT6765:
case PWRAP_MT6779:
case PWRAP_MT6795:
@@ -2194,6 +2343,14 @@ static const struct pwrap_slv_type pmic_mt6323 = {
PWRAP_SLV_CAP_SECURITY,
};
+static const struct pwrap_slv_type pmic_mt6328 = {
+ .dew_regs = mt6328_regs,
+ .type = PMIC_MT6328,
+ .regops = &pwrap_regops16,
+ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+ PWRAP_SLV_CAP_SECURITY,
+};
+
static const struct pwrap_slv_type pmic_mt6331 = {
.dew_regs = mt6331_regs,
.type = PMIC_MT6331,
@@ -2249,6 +2406,7 @@ static const struct pwrap_slv_type pmic_mt6397 = {
static const struct of_device_id of_slave_match_tbl[] = {
{ .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },
+ { .compatible = "mediatek,mt6328", .data = &pmic_mt6328 },
{ .compatible = "mediatek,mt6331", .data = &pmic_mt6331 },
{ .compatible = "mediatek,mt6351", .data = &pmic_mt6351 },
{ .compatible = "mediatek,mt6357", .data = &pmic_mt6357 },
@@ -2277,6 +2435,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
.init_soc_specific = pwrap_mt2701_init_soc_specific,
};
+static const struct pmic_wrapper_type pwrap_mt6735 = {
+ .regs = mt6735_regs,
+ .type = PWRAP_MT6735,
+ .arb_en_all = GENMASK(9, 0),
+ .int_en_all = GENMASK(31, 0),
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+ .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = NULL,
+};
+
static const struct pmic_wrapper_type pwrap_mt6765 = {
.regs = mt6765_regs,
.type = PWRAP_MT6765,
@@ -2446,6 +2616,7 @@ static const struct pmic_wrapper_type pwrap_mt8186 = {
static const struct of_device_id of_pwrap_match_tbl[] = {
{ .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },
+ { .compatible = "mediatek,mt6735-pwrap", .data = &pwrap_mt6735 },
{ .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },
{ .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },
{ .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 },
--
2.54.0
^ permalink raw reply related
* [PATCH v2 0/4] MediaTek MT6735+MT6328 SoC/PMIC pair base support
From: Yassine Oudjana via B4 Relay @ 2026-05-31 9:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Flora Fu, Alexandre Mergnat,
Liam Girdwood, Mark Brown, Dmitry Torokhov
Cc: Yassine Oudjana, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-input
These patches are part of a larger effort to support the MT6735 SoC family in
mainline Linux. More patches (unsent or sent and pending review or revision)
can be found here[1].
This series adds base support for the MediaTek MT6735 SoC and MT6328 PMIC pair.
This includes PMIC wrapper support on the SoC side and regulators and keys on
the PMIC side. The PMIC has other blocks such as an audio codec and battery
charger which can be supported in the future.
Changes since v1:
- Fit regulator definitions in 2 lines and 100 characters whenever possible.
- Remove get_mode and set_mode ops for regulators that don't support them.
[1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
Yassine Oudjana (4):
dt-bindings: mediatek: pwrap: Add MT6735 compatible
soc: mediatek: pwrap: Add support for MT6735 and MT6328 SoC/PMIC pair
regulator: Add driver for MediaTek MT6328 PMIC regulators
Input: mtk-pmic-keys - Add support for MT6328
.../bindings/soc/mediatek/mediatek,pwrap.yaml | 1 +
drivers/input/keyboard/mtk-pmic-keys.c | 15 +
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6328-regulator.c | 500 +++++++++++++++++++++
drivers/soc/mediatek/mtk-pmic-wrap.c | 177 +++++++-
include/linux/regulator/mt6328-regulator.h | 49 ++
7 files changed, 749 insertions(+), 3 deletions(-)
---
base-commit: 7da7f07112610a520567421dd2ffcb51beaefbcc
change-id: 20260531-mt6735-pwrap-mt6328-pmic-de481d5c5e89
Best regards,
--
Yassine Oudjana <y.oudjana@protonmail.com>
^ permalink raw reply
* [PATCH v2] wifi: mt76: mt7996: fix reading zeroed info->control.flags after mt76_tx_status_skb_add()
From: Lorenzo Bianconi @ 2026-05-31 8:55 UTC (permalink / raw)
To: Felix Fietkau, Ryder Lee, Shayne Chen, Sean Wang,
Matthias Brugger, AngeloGioacchino Del Regno, Bo Jiao, Peter Chiu,
Lorenzo Bianconi
Cc: Roy Luo, linux-wireless, linux-arm-kernel, linux-mediatek,
linux-kernel
mt76_tx_status_skb_add() zeroes the mt76_tx_cb struct stored at
info->status.status_driver_data via memset(). Since info->control and
info->status are members of the same union in ieee80211_tx_info,
this overwrites info->control.flags.
In mt7996_tx_prepare_skb(), mt76_tx_status_skb_add() is called before
mt7996_mac_write_txwi(), which re-reads info->control.flags to extract
IEEE80211_TX_CTRL_MLO_LINK. Because the field has been zeroed, the
link_id always resolves to 0 for frames using global_wcid, leading to
incorrect TXWI configuration.
Fix this by passing link_id as an explicit parameter to
mt7996_mac_write_txwi(). In mt7996_tx_prepare_skb(), the link_id is
already extracted from info->control.flags before the destructive
mt76_tx_status_skb_add() call. For the beacon and inband discovery
callers in mcu.c, use link_conf->link_id directly.
Fixes: f0b0b239b8f36 ("wifi: mt76: mt7996: rework mt7996_mac_write_txwi() for MLO support")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
Changes in v2:
- Do not use link_id in mt7996_mac_write_txwi if it is IEEE80211_LINK_UNSPECIFIED
- In mt7996_mac_write_txwi() rely on link_id calculated in
mt7996_tx_prepare_skb().
- Link to v1: https://lore.kernel.org/r/20260530-mt76_tx_status_skb_add-overwrite-fix-v1-1-e2c3151c391a@kernel.org
---
drivers/net/wireless/mediatek/mt76/mt7996/mac.c | 14 ++++----------
drivers/net/wireless/mediatek/mt76/mt7996/mcu.c | 5 +++--
drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h | 3 ++-
3 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index c98446057282..95b3078d9667 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -856,7 +856,8 @@ mt7996_mac_write_txwi_80211(struct mt7996_dev *dev, __le32 *txwi,
void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
struct sk_buff *skb, struct mt76_wcid *wcid,
struct ieee80211_key_conf *key, int pid,
- enum mt76_txq_id qid, u32 changed)
+ enum mt76_txq_id qid, u32 changed,
+ unsigned int link_id)
{
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
@@ -866,7 +867,6 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
struct mt76_vif_link *mlink = NULL;
struct mt7996_vif *mvif;
- unsigned int link_id;
u16 tx_count = 15;
u32 val;
bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP |
@@ -874,17 +874,11 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
bool beacon = !!(changed & (BSS_CHANGED_BEACON |
BSS_CHANGED_BEACON_ENABLED)) && (!inband_disc);
- if (wcid != &dev->mt76.global_wcid)
- link_id = wcid->link_id;
- else
- link_id = u32_get_bits(info->control.flags,
- IEEE80211_TX_CTRL_MLO_LINK);
-
mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL;
if (mvif) {
if (wcid->offchannel)
mlink = rcu_dereference(mvif->mt76.offchannel_link);
- if (!mlink)
+ if (!mlink && link_id != IEEE80211_LINK_UNSPECIFIED)
mlink = rcu_dereference(mvif->mt76.link[link_id]);
}
@@ -1096,7 +1090,7 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
/* Transmit non qos data by 802.11 header and need to fill txd by host*/
if (!is_8023 || pid >= MT_PACKET_ID_FIRST)
mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key,
- pid, qid, 0);
+ pid, qid, 0, link_id);
/* MT7996 and MT7992 require driver to provide the MAC TXP for AddBA
* req
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
index 8be40d60ad29..a14c63438923 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
@@ -3103,7 +3103,7 @@ mt7996_mcu_beacon_cont(struct mt7996_dev *dev,
buf = (u8 *)bcn + sizeof(*bcn);
mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL, 0, 0,
- BSS_CHANGED_BEACON);
+ BSS_CHANGED_BEACON, link_conf->link_id);
memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
}
@@ -3249,7 +3249,8 @@ int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
buf = (u8 *)tlv + sizeof(*discov);
- mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL, 0, 0, changed);
+ mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL, 0, 0,
+ changed, link_conf->link_id);
memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
index 0dc4198fcf8b..0d6488522ba7 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
@@ -874,7 +874,8 @@ void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
struct sk_buff *skb, struct mt76_wcid *wcid,
struct ieee80211_key_conf *key, int pid,
- enum mt76_txq_id qid, u32 changed);
+ enum mt76_txq_id qid, u32 changed,
+ unsigned int link_id);
void mt7996_mac_update_beacons(struct mt7996_phy *phy);
void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
void mt7996_mac_work(struct work_struct *work);
---
base-commit: 4913f44167cf35a9536e9eec7352e15b2de0c573
change-id: 20260530-mt76_tx_status_skb_add-overwrite-fix-85818a9bb31f
Best regards,
--
Lorenzo Bianconi <lorenzo@kernel.org>
^ permalink raw reply related
* Re: [PATCH] wifi: mt76: mt7996: fix reading zeroed info->control.flags after mt76_tx_status_skb_add()
From: lorenzo @ 2026-05-31 7:09 UTC (permalink / raw)
To: Ryder Lee
Cc: Shayne Chen (陳軒丞), nbd@nbd.name,
AngeloGioacchino Del Regno,
Chui-hao Chiu (邱垂浩), Sean Wang,
Bo Jiao (焦波), matthias.bgg@gmail.com,
linux-wireless@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Roy-CH Luo,
linux-mediatek@lists.infradead.org
In-Reply-To: <6be1d6e67bcb5500c9d1e92449ce7757f6166d22.camel@mediatek.com>
[-- Attachment #1: Type: text/plain, Size: 6203 bytes --]
> On Sat, 2026-05-30 at 17:25 +0200, Lorenzo Bianconi wrote:
> > mt76_tx_status_skb_add() zeroes the mt76_tx_cb struct stored at
> > info->status.status_driver_data via memset(). Since info->control and
> > info->status are members of the same union in ieee80211_tx_info,
> > this overwrites info->control.flags.
> > In mt7996_tx_prepare_skb(), mt76_tx_status_skb_add() is called before
> > mt7996_mac_write_txwi(), which re-reads info->control.flags to
> > extract
> > IEEE80211_TX_CTRL_MLO_LINK. Because the field has been zeroed, the
> > link_id always resolves to 0 for frames using global_wcid, leading to
> > incorrect TXWI configuration.
> > Fix this by passing link_id as an explicit parameter to
> > mt7996_mac_write_txwi(). In mt7996_tx_prepare_skb(), the link_id is
> > already extracted from info->control.flags before the destructive
> > mt76_tx_status_skb_add() call. For the beacon and inband discovery
> > callers in mcu.c, use link_conf->link_id directly.
> >
> > Fixes: f0b0b239b8f36 ("wifi: mt76: mt7996: rework
> > mt7996_mac_write_txwi() for MLO support")
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> > drivers/net/wireless/mediatek/mt76/mt7996/mac.c | 9 +++------
> > drivers/net/wireless/mediatek/mt76/mt7996/mcu.c | 5 +++--
> > drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h | 3 ++-
> > 3 files changed, 8 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> > b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> > index c98446057282..2d3f80b3e41a 100644
> > --- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> > +++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> > @@ -856,7 +856,8 @@ mt7996_mac_write_txwi_80211(struct mt7996_dev
> > *dev, __le32 *txwi,
> > void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
> > struct sk_buff *skb, struct mt76_wcid
> > *wcid,
> > struct ieee80211_key_conf *key, int pid,
> > - enum mt76_txq_id qid, u32 changed)
> > + enum mt76_txq_id qid, u32 changed,
> > + unsigned int link_id)
> > {
> > struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb-
> > >data;
> > struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
> > @@ -866,7 +867,6 @@ void mt7996_mac_write_txwi(struct mt7996_dev
> > *dev, __le32 *txwi,
> > bool is_8023 = info->flags &
> > IEEE80211_TX_CTL_HW_80211_ENCAP;
> > struct mt76_vif_link *mlink = NULL;
> > struct mt7996_vif *mvif;
> > - unsigned int link_id;
> > u16 tx_count = 15;
> > u32 val;
> > bool inband_disc = !!(changed &
> > (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP |
> > @@ -876,9 +876,6 @@ void mt7996_mac_write_txwi(struct mt7996_dev
> > *dev, __le32 *txwi,
> >
> > if (wcid != &dev->mt76.global_wcid)
> > link_id = wcid->link_id;
> > - else
> > - link_id = u32_get_bits(info->control.flags,
> > - IEEE80211_TX_CTRL_MLO_LINK);
> >
> > mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL;
> > if (mvif) {
> > @@ -1096,7 +1093,7 @@ int mt7996_tx_prepare_skb(struct mt76_dev
> > *mdev, void *txwi_ptr,
> > /* Transmit non qos data by 802.11 header and need to fill
> > txd by host*/
> > if (!is_8023 || pid >= MT_PACKET_ID_FIRST)
> > mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb,
> > wcid, key,
> > - pid, qid, 0);
> > + pid, qid, 0, link_id);
> >
> > /* MT7996 and MT7992 require driver to provide the MAC TXP
> > for AddBA
> > * req
> > diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> > b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> > index 8be40d60ad29..a14c63438923 100644
> > --- a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> > +++ b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> > @@ -3103,7 +3103,7 @@ mt7996_mcu_beacon_cont(struct mt7996_dev *dev,
> >
> > buf = (u8 *)bcn + sizeof(*bcn);
> > mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL,
> > 0, 0,
> > - BSS_CHANGED_BEACON);
> > + BSS_CHANGED_BEACON, link_conf-
> > >link_id);
> >
> > memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
> > }
> > @@ -3249,7 +3249,8 @@ int mt7996_mcu_beacon_inband_discov(struct
> > mt7996_dev *dev,
> >
> > buf = (u8 *)tlv + sizeof(*discov);
> >
> > - mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL,
> > 0, 0, changed);
> > + mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL,
> > 0, 0,
> > + changed, link_conf->link_id);
> >
> > memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
> >
> > diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> > b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> > index 0dc4198fcf8b..0d6488522ba7 100644
> > --- a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> > +++ b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> > @@ -874,7 +874,8 @@ void mt7996_mac_enable_nf(struct mt7996_dev *dev,
> > u8 band);
> > void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
> > struct sk_buff *skb, struct mt76_wcid
> > *wcid,
> > struct ieee80211_key_conf *key, int pid,
> > - enum mt76_txq_id qid, u32 changed);
> > + enum mt76_txq_id qid, u32 changed,
> > + unsigned int link_id);
> > void mt7996_mac_update_beacons(struct mt7996_phy *phy);
> > void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
> > void mt7996_mac_work(struct work_struct *work);
>
> The reason we didn't make the same change is because we use other
> control flags (IEEE80211_TX_CTRL*) of info->control.flags not just MLO
> one. So with this change we still need to copy over the other flags and
> pass them in as well.
Do you mean you are using info->control.flags in mt7996_mac_write_txwi() in
some downstream code? If so, I guess you can use a similar approach and
just pass the required field. Copy the full ieee80211_tx_info struct on
per-packet basis seems unnecessary.
Regards,
Lorenzo
>
> Ryder
> >
> > ---
> > base-commit: 4913f44167cf35a9536e9eec7352e15b2de0c573
> > change-id: 20260530-mt76_tx_status_skb_add-overwrite-fix-85818a9bb31f
> >
> > Best regards,
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v6 1/2] dt-bindings: ufs: Document static TX Equalization settings properties
From: Can Guo @ 2026-05-31 4:48 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: bvanassche, beanhuo, peter.wang, martin.petersen, mani,
linux-scsi, Alim Akhtar, Avri Altman, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Zhaoming Luo, Ram Kumar Dwivedi,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek
In-Reply-To: <7d49742a-7602-4f58-8dce-7e02664b783c@oss.qualcomm.com>
On 5/31/2026 9:41 AM, Can Guo wrote:
>
>
> On 5/31/2026 1:33 AM, Krzysztof Kozlowski wrote:
>> On 30/05/2026 14:45, Can Guo wrote:
>>>
>>> On 5/30/2026 12:58 AM, Krzysztof Kozlowski wrote:
>>>> On Fri, May 29, 2026 at 04:33:37AM -0700, Can Guo wrote:
>>>>> UFS v5.0/UFSHCI v5.0 add HS-G6 support (46.6 Gbps/lane) via UniPro
>>>>> v3.0
>>>>> and M-PHY v6.0. In these specs, TX Equalization is defined for all
>>>>> High
>>>>> Speed Gears (not only HS-G6) to compensate channel loss and
>>>>> improve signal
>>>>> integrity at high speed operation.
>>>>>
>>>>> For HS-G6, M-PHY uses PAM4 1b1b line coding, Pre-Coding may also be
>>>>> required depending on channel characteristics.
>>>>>
>>>>> Add vendor-neutral DT properties:
>>>>>
>>>>> - patternProperties for txeq-preshoot-g[1-6] and
>>>>> txeq-deemphasis-g[1-6]
>>>>> - fixed property tx-precode-enable-g6
>>>>>
>>>>> Each property is a uint32 array of per-lane tuples:
>>>>> <Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>]
>>>>>
>>>>> Accept 2 or 4 values (x1/x2 lane configs). PreShoot and DeEmphasis
>>>>> values
>>>>> are 0..7. Precode enable values are 0/1 and only applicable to HS-G6.
>>>>>
>>>>> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
>>>>> Reviewed-by: Bean Huo <beanhuo@micron.com>
>>>>> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
>>>>> Signed-off-by: Can Guo <can.guo@oss.qualcomm.com>
>>>>> ---
>>>>> .../devicetree/bindings/ufs/ufs-common.yaml | 45
>>>>> +++++++++++++++++++
>>>>> 1 file changed, 45 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>>>> b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>>>> index ed97f5682509..d90cf25adfa5 100644
>>>>> --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>>>> +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>>>> @@ -105,6 +105,51 @@ properties:
>>>>> Restricts the UFS controller to rate-a or rate-b for both
>>>>> TX and
>>>>> RX directions.
>>>>> + tx-precode-enable-g6:
>>>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>>>> + oneOf:
>>>>> + - minItems: 2
>>>>> + maxItems: 2
>>>>> + - minItems: 4
>>>>> + maxItems: 4
>>>>> + items:
>>>>> + enum: [0, 1]
>>>>> + description: |
>>>>> + Static TX Precode enable values for HS-G6 only.
>>>>> + Values are specified as per-lane tuples:
>>>>> + <Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>].
>>>> You need to include them in any of applicable examples, otherwise
>>>> nothing here is validated.
>>> Hi Krzysztof,
>>>
>>> Thanks for the review.
>>>
>>> Since no UFS5-capable SoC binding exists upstream yet (the target
>>> SoC is
>> I would imagine cover letter or commit msg would briefly mention that.
> Thanks for the clarification. Will do.
>>
>>> still pre-CS), there is no vendor-specific YAML to attach the
>>> example to.
>>>
>>> Is a synthetic example directly in ufs-common.yaml OK to you?
>> Skip example in such case.
>>
>>>> Why values cannot be on or off? Or even better: why you cannot just
>>>> list
>>>> all the lanes which has it enabled, assuming disabled is by default?
>>> Thanks for the suggestions.
>>>
>>> For the "just list enabled lanes" suggestion: precode must be
>>> configured
>>> independently for the Host-side TX and Device-side TX transceivers
>>> within
>>> the same physical lane. A lane index list alone cannot capture this
>>> two-dimensional per-lane state. The tuple format <Host_LaneN
>>> Device_LaneN>
>>> is the minimal encoding that covers both.
>> Again, why do you need to encode '0'?
> The tuple is still needed because Precoding is configured per
> transmitter-receiver pair,
> so each lane has two independent states:
> - Host_TX -> Device_RX
> - Device_TX -> Host_RX
> A lane-only enabled list cannot represent directional combinations
> like lane0 =
> (on, off) vs (off, on).
How about we split into two properties, something like below?
tx-precode-enable-g6-host-lanes = <0 1>
tx-precode-enable-g6-device-lanes = <1>
Only listed lanes are enabled; unlisted lanes are disabled by default.
Are you OK with this approach?
Thanks,
Can Guo.
>>
>>> For the "on/off" suggestion: the on/off string pattern is used with
>>> single-value properties (e.g. LED default-state) read via
>>> of_property_read_string(). I am not aware of precedent for on/off as a
>>> string array for per-lane tuples.
>> git grep string-array. Plenty of precedents.
> I will keep the per-lane tuple model but switch tx-precode-enable-g6
> from 0/1 to
> "on"/"off" (string array) in v7.
>
> Thanks,
> Can Guo.
>>
>> Best regards,
>> Krzysztof
>
^ permalink raw reply
* Re: [PATCH] wifi: mt76: mt7996: fix reading zeroed info->control.flags after mt76_tx_status_skb_add()
From: Ryder Lee @ 2026-05-31 2:03 UTC (permalink / raw)
To: Shayne Chen (陳軒丞), lorenzo@kernel.org,
nbd@nbd.name, AngeloGioacchino Del Regno,
Chui-hao Chiu (邱垂浩), Sean Wang,
Bo Jiao (焦波), matthias.bgg@gmail.com
Cc: linux-wireless@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Roy-CH Luo,
linux-mediatek@lists.infradead.org
In-Reply-To: <20260530-mt76_tx_status_skb_add-overwrite-fix-v1-1-e2c3151c391a@kernel.org>
On Sat, 2026-05-30 at 17:25 +0200, Lorenzo Bianconi wrote:
> mt76_tx_status_skb_add() zeroes the mt76_tx_cb struct stored at
> info->status.status_driver_data via memset(). Since info->control and
> info->status are members of the same union in ieee80211_tx_info,
> this overwrites info->control.flags.
> In mt7996_tx_prepare_skb(), mt76_tx_status_skb_add() is called before
> mt7996_mac_write_txwi(), which re-reads info->control.flags to
> extract
> IEEE80211_TX_CTRL_MLO_LINK. Because the field has been zeroed, the
> link_id always resolves to 0 for frames using global_wcid, leading to
> incorrect TXWI configuration.
> Fix this by passing link_id as an explicit parameter to
> mt7996_mac_write_txwi(). In mt7996_tx_prepare_skb(), the link_id is
> already extracted from info->control.flags before the destructive
> mt76_tx_status_skb_add() call. For the beacon and inband discovery
> callers in mcu.c, use link_conf->link_id directly.
>
> Fixes: f0b0b239b8f36 ("wifi: mt76: mt7996: rework
> mt7996_mac_write_txwi() for MLO support")
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> drivers/net/wireless/mediatek/mt76/mt7996/mac.c | 9 +++------
> drivers/net/wireless/mediatek/mt76/mt7996/mcu.c | 5 +++--
> drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h | 3 ++-
> 3 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> index c98446057282..2d3f80b3e41a 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
> @@ -856,7 +856,8 @@ mt7996_mac_write_txwi_80211(struct mt7996_dev
> *dev, __le32 *txwi,
> void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
> struct sk_buff *skb, struct mt76_wcid
> *wcid,
> struct ieee80211_key_conf *key, int pid,
> - enum mt76_txq_id qid, u32 changed)
> + enum mt76_txq_id qid, u32 changed,
> + unsigned int link_id)
> {
> struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb-
> >data;
> struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
> @@ -866,7 +867,6 @@ void mt7996_mac_write_txwi(struct mt7996_dev
> *dev, __le32 *txwi,
> bool is_8023 = info->flags &
> IEEE80211_TX_CTL_HW_80211_ENCAP;
> struct mt76_vif_link *mlink = NULL;
> struct mt7996_vif *mvif;
> - unsigned int link_id;
> u16 tx_count = 15;
> u32 val;
> bool inband_disc = !!(changed &
> (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP |
> @@ -876,9 +876,6 @@ void mt7996_mac_write_txwi(struct mt7996_dev
> *dev, __le32 *txwi,
>
> if (wcid != &dev->mt76.global_wcid)
> link_id = wcid->link_id;
> - else
> - link_id = u32_get_bits(info->control.flags,
> - IEEE80211_TX_CTRL_MLO_LINK);
>
> mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL;
> if (mvif) {
> @@ -1096,7 +1093,7 @@ int mt7996_tx_prepare_skb(struct mt76_dev
> *mdev, void *txwi_ptr,
> /* Transmit non qos data by 802.11 header and need to fill
> txd by host*/
> if (!is_8023 || pid >= MT_PACKET_ID_FIRST)
> mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb,
> wcid, key,
> - pid, qid, 0);
> + pid, qid, 0, link_id);
>
> /* MT7996 and MT7992 require driver to provide the MAC TXP
> for AddBA
> * req
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> index 8be40d60ad29..a14c63438923 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
> @@ -3103,7 +3103,7 @@ mt7996_mcu_beacon_cont(struct mt7996_dev *dev,
>
> buf = (u8 *)bcn + sizeof(*bcn);
> mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL,
> 0, 0,
> - BSS_CHANGED_BEACON);
> + BSS_CHANGED_BEACON, link_conf-
> >link_id);
>
> memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
> }
> @@ -3249,7 +3249,8 @@ int mt7996_mcu_beacon_inband_discov(struct
> mt7996_dev *dev,
>
> buf = (u8 *)tlv + sizeof(*discov);
>
> - mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL,
> 0, 0, changed);
> + mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL,
> 0, 0,
> + changed, link_conf->link_id);
>
> memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> index 0dc4198fcf8b..0d6488522ba7 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
> @@ -874,7 +874,8 @@ void mt7996_mac_enable_nf(struct mt7996_dev *dev,
> u8 band);
> void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
> struct sk_buff *skb, struct mt76_wcid
> *wcid,
> struct ieee80211_key_conf *key, int pid,
> - enum mt76_txq_id qid, u32 changed);
> + enum mt76_txq_id qid, u32 changed,
> + unsigned int link_id);
> void mt7996_mac_update_beacons(struct mt7996_phy *phy);
> void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
> void mt7996_mac_work(struct work_struct *work);
The reason we didn't make the same change is because we use other
control flags (IEEE80211_TX_CTRL*) of info->control.flags not just MLO
one. So with this change we still need to copy over the other flags and
pass them in as well.
Ryder
>
> ---
> base-commit: 4913f44167cf35a9536e9eec7352e15b2de0c573
> change-id: 20260530-mt76_tx_status_skb_add-overwrite-fix-85818a9bb31f
>
> Best regards,
^ permalink raw reply
* Re: [PATCH v6 1/2] dt-bindings: ufs: Document static TX Equalization settings properties
From: Can Guo @ 2026-05-31 1:41 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: bvanassche, beanhuo, peter.wang, martin.petersen, mani,
linux-scsi, Alim Akhtar, Avri Altman, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Zhaoming Luo, Ram Kumar Dwivedi,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek
In-Reply-To: <b445e9e3-dfda-45d6-bafb-a2deb3357144@kernel.org>
On 5/31/2026 1:33 AM, Krzysztof Kozlowski wrote:
> On 30/05/2026 14:45, Can Guo wrote:
>>
>> On 5/30/2026 12:58 AM, Krzysztof Kozlowski wrote:
>>> On Fri, May 29, 2026 at 04:33:37AM -0700, Can Guo wrote:
>>>> UFS v5.0/UFSHCI v5.0 add HS-G6 support (46.6 Gbps/lane) via UniPro v3.0
>>>> and M-PHY v6.0. In these specs, TX Equalization is defined for all High
>>>> Speed Gears (not only HS-G6) to compensate channel loss and improve signal
>>>> integrity at high speed operation.
>>>>
>>>> For HS-G6, M-PHY uses PAM4 1b1b line coding, Pre-Coding may also be
>>>> required depending on channel characteristics.
>>>>
>>>> Add vendor-neutral DT properties:
>>>>
>>>> - patternProperties for txeq-preshoot-g[1-6] and txeq-deemphasis-g[1-6]
>>>> - fixed property tx-precode-enable-g6
>>>>
>>>> Each property is a uint32 array of per-lane tuples:
>>>> <Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>]
>>>>
>>>> Accept 2 or 4 values (x1/x2 lane configs). PreShoot and DeEmphasis values
>>>> are 0..7. Precode enable values are 0/1 and only applicable to HS-G6.
>>>>
>>>> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
>>>> Reviewed-by: Bean Huo <beanhuo@micron.com>
>>>> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
>>>> Signed-off-by: Can Guo <can.guo@oss.qualcomm.com>
>>>> ---
>>>> .../devicetree/bindings/ufs/ufs-common.yaml | 45 +++++++++++++++++++
>>>> 1 file changed, 45 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>>> index ed97f5682509..d90cf25adfa5 100644
>>>> --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>>> +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>>> @@ -105,6 +105,51 @@ properties:
>>>> Restricts the UFS controller to rate-a or rate-b for both TX and
>>>> RX directions.
>>>>
>>>> + tx-precode-enable-g6:
>>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>>> + oneOf:
>>>> + - minItems: 2
>>>> + maxItems: 2
>>>> + - minItems: 4
>>>> + maxItems: 4
>>>> + items:
>>>> + enum: [0, 1]
>>>> + description: |
>>>> + Static TX Precode enable values for HS-G6 only.
>>>> + Values are specified as per-lane tuples:
>>>> + <Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>].
>>> You need to include them in any of applicable examples, otherwise
>>> nothing here is validated.
>> Hi Krzysztof,
>>
>> Thanks for the review.
>>
>> Since no UFS5-capable SoC binding exists upstream yet (the target SoC is
> I would imagine cover letter or commit msg would briefly mention that.
Thanks for the clarification. Will do.
>
>> still pre-CS), there is no vendor-specific YAML to attach the example to.
>>
>> Is a synthetic example directly in ufs-common.yaml OK to you?
> Skip example in such case.
>
>>> Why values cannot be on or off? Or even better: why you cannot just list
>>> all the lanes which has it enabled, assuming disabled is by default?
>> Thanks for the suggestions.
>>
>> For the "just list enabled lanes" suggestion: precode must be configured
>> independently for the Host-side TX and Device-side TX transceivers within
>> the same physical lane. A lane index list alone cannot capture this
>> two-dimensional per-lane state. The tuple format <Host_LaneN Device_LaneN>
>> is the minimal encoding that covers both.
> Again, why do you need to encode '0'?
The tuple is still needed because Precoding is configured per
transmitter-receiver pair,
so each lane has two independent states:
- Host_TX -> Device_RX
- Device_TX -> Host_RX
A lane-only enabled list cannot represent directional combinations like
lane0 =
(on, off) vs (off, on).
>
>> For the "on/off" suggestion: the on/off string pattern is used with
>> single-value properties (e.g. LED default-state) read via
>> of_property_read_string(). I am not aware of precedent for on/off as a
>> string array for per-lane tuples.
> git grep string-array. Plenty of precedents.
I will keep the per-lane tuple model but switch tx-precode-enable-g6
from 0/1 to
"on"/"off" (string array) in v7.
Thanks,
Can Guo.
>
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH v6 1/2] dt-bindings: ufs: Document static TX Equalization settings properties
From: Krzysztof Kozlowski @ 2026-05-30 17:33 UTC (permalink / raw)
To: Can Guo
Cc: bvanassche, beanhuo, peter.wang, martin.petersen, mani,
linux-scsi, Alim Akhtar, Avri Altman, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Zhaoming Luo, Ram Kumar Dwivedi,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek
In-Reply-To: <ada65ce2-6736-44fe-9396-d3ed632274ce@oss.qualcomm.com>
On 30/05/2026 14:45, Can Guo wrote:
>
>
> On 5/30/2026 12:58 AM, Krzysztof Kozlowski wrote:
>> On Fri, May 29, 2026 at 04:33:37AM -0700, Can Guo wrote:
>>> UFS v5.0/UFSHCI v5.0 add HS-G6 support (46.6 Gbps/lane) via UniPro v3.0
>>> and M-PHY v6.0. In these specs, TX Equalization is defined for all High
>>> Speed Gears (not only HS-G6) to compensate channel loss and improve signal
>>> integrity at high speed operation.
>>>
>>> For HS-G6, M-PHY uses PAM4 1b1b line coding, Pre-Coding may also be
>>> required depending on channel characteristics.
>>>
>>> Add vendor-neutral DT properties:
>>>
>>> - patternProperties for txeq-preshoot-g[1-6] and txeq-deemphasis-g[1-6]
>>> - fixed property tx-precode-enable-g6
>>>
>>> Each property is a uint32 array of per-lane tuples:
>>> <Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>]
>>>
>>> Accept 2 or 4 values (x1/x2 lane configs). PreShoot and DeEmphasis values
>>> are 0..7. Precode enable values are 0/1 and only applicable to HS-G6.
>>>
>>> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
>>> Reviewed-by: Bean Huo <beanhuo@micron.com>
>>> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
>>> Signed-off-by: Can Guo <can.guo@oss.qualcomm.com>
>>> ---
>>> .../devicetree/bindings/ufs/ufs-common.yaml | 45 +++++++++++++++++++
>>> 1 file changed, 45 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>> index ed97f5682509..d90cf25adfa5 100644
>>> --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>> +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
>>> @@ -105,6 +105,51 @@ properties:
>>> Restricts the UFS controller to rate-a or rate-b for both TX and
>>> RX directions.
>>>
>>> + tx-precode-enable-g6:
>>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>>> + oneOf:
>>> + - minItems: 2
>>> + maxItems: 2
>>> + - minItems: 4
>>> + maxItems: 4
>>> + items:
>>> + enum: [0, 1]
>>> + description: |
>>> + Static TX Precode enable values for HS-G6 only.
>>> + Values are specified as per-lane tuples:
>>> + <Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>].
>> You need to include them in any of applicable examples, otherwise
>> nothing here is validated.
> Hi Krzysztof,
>
> Thanks for the review.
>
> Since no UFS5-capable SoC binding exists upstream yet (the target SoC is
I would imagine cover letter or commit msg would briefly mention that.
> still pre-CS), there is no vendor-specific YAML to attach the example to.
>
> Is a synthetic example directly in ufs-common.yaml OK to you?
Skip example in such case.
>>
>> Why values cannot be on or off? Or even better: why you cannot just list
>> all the lanes which has it enabled, assuming disabled is by default?
> Thanks for the suggestions.
>
> For the "just list enabled lanes" suggestion: precode must be configured
> independently for the Host-side TX and Device-side TX transceivers within
> the same physical lane. A lane index list alone cannot capture this
> two-dimensional per-lane state. The tuple format <Host_LaneN Device_LaneN>
> is the minimal encoding that covers both.
Again, why do you need to encode '0'?
>
> For the "on/off" suggestion: the on/off string pattern is used with
> single-value properties (e.g. LED default-state) read via
> of_property_read_string(). I am not aware of precedent for on/off as a
> string array for per-lane tuples.
git grep string-array. Plenty of precedents.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH] wifi: mt76: mt7996: fix reading zeroed info->control.flags after mt76_tx_status_skb_add()
From: Lorenzo Bianconi @ 2026-05-30 15:25 UTC (permalink / raw)
To: Felix Fietkau, Ryder Lee, Shayne Chen, Sean Wang,
Matthias Brugger, AngeloGioacchino Del Regno, Bo Jiao, Peter Chiu,
Lorenzo Bianconi
Cc: Roy Luo, linux-wireless, linux-arm-kernel, linux-mediatek
mt76_tx_status_skb_add() zeroes the mt76_tx_cb struct stored at
info->status.status_driver_data via memset(). Since info->control and
info->status are members of the same union in ieee80211_tx_info,
this overwrites info->control.flags.
In mt7996_tx_prepare_skb(), mt76_tx_status_skb_add() is called before
mt7996_mac_write_txwi(), which re-reads info->control.flags to extract
IEEE80211_TX_CTRL_MLO_LINK. Because the field has been zeroed, the
link_id always resolves to 0 for frames using global_wcid, leading to
incorrect TXWI configuration.
Fix this by passing link_id as an explicit parameter to
mt7996_mac_write_txwi(). In mt7996_tx_prepare_skb(), the link_id is
already extracted from info->control.flags before the destructive
mt76_tx_status_skb_add() call. For the beacon and inband discovery
callers in mcu.c, use link_conf->link_id directly.
Fixes: f0b0b239b8f36 ("wifi: mt76: mt7996: rework mt7996_mac_write_txwi() for MLO support")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/wireless/mediatek/mt76/mt7996/mac.c | 9 +++------
drivers/net/wireless/mediatek/mt76/mt7996/mcu.c | 5 +++--
drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h | 3 ++-
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
index c98446057282..2d3f80b3e41a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mac.c
@@ -856,7 +856,8 @@ mt7996_mac_write_txwi_80211(struct mt7996_dev *dev, __le32 *txwi,
void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
struct sk_buff *skb, struct mt76_wcid *wcid,
struct ieee80211_key_conf *key, int pid,
- enum mt76_txq_id qid, u32 changed)
+ enum mt76_txq_id qid, u32 changed,
+ unsigned int link_id)
{
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
@@ -866,7 +867,6 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
struct mt76_vif_link *mlink = NULL;
struct mt7996_vif *mvif;
- unsigned int link_id;
u16 tx_count = 15;
u32 val;
bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP |
@@ -876,9 +876,6 @@ void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
if (wcid != &dev->mt76.global_wcid)
link_id = wcid->link_id;
- else
- link_id = u32_get_bits(info->control.flags,
- IEEE80211_TX_CTRL_MLO_LINK);
mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL;
if (mvif) {
@@ -1096,7 +1093,7 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
/* Transmit non qos data by 802.11 header and need to fill txd by host*/
if (!is_8023 || pid >= MT_PACKET_ID_FIRST)
mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key,
- pid, qid, 0);
+ pid, qid, 0, link_id);
/* MT7996 and MT7992 require driver to provide the MAC TXP for AddBA
* req
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
index 8be40d60ad29..a14c63438923 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
@@ -3103,7 +3103,7 @@ mt7996_mcu_beacon_cont(struct mt7996_dev *dev,
buf = (u8 *)bcn + sizeof(*bcn);
mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL, 0, 0,
- BSS_CHANGED_BEACON);
+ BSS_CHANGED_BEACON, link_conf->link_id);
memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
}
@@ -3249,7 +3249,8 @@ int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
buf = (u8 *)tlv + sizeof(*discov);
- mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL, 0, 0, changed);
+ mt7996_mac_write_txwi(dev, (__le32 *)buf, skb, wcid, NULL, 0, 0,
+ changed, link_conf->link_id);
memcpy(buf + MT_TXD_SIZE, skb->data, skb->len);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
index 0dc4198fcf8b..0d6488522ba7 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
@@ -874,7 +874,8 @@ void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
struct sk_buff *skb, struct mt76_wcid *wcid,
struct ieee80211_key_conf *key, int pid,
- enum mt76_txq_id qid, u32 changed);
+ enum mt76_txq_id qid, u32 changed,
+ unsigned int link_id);
void mt7996_mac_update_beacons(struct mt7996_phy *phy);
void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
void mt7996_mac_work(struct work_struct *work);
---
base-commit: 4913f44167cf35a9536e9eec7352e15b2de0c573
change-id: 20260530-mt76_tx_status_skb_add-overwrite-fix-85818a9bb31f
Best regards,
--
Lorenzo Bianconi <lorenzo@kernel.org>
^ permalink raw reply related
* [PATCH v8 6/6] pinctrl: mediatek: Add MT6735 pinctrl driver
From: Yassine Oudjana @ 2026-05-30 14:57 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng
Cc: Yassine Oudjana, linux-mediatek, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260530145800.1029920-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add a driver for the MediaTek MT6735 SoC pin controller. This driver
also supports the pin controller on MT6735M, which lacks 6 physical
pins (198-203) used for MSDC2 on MT6735.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
MAINTAINERS | 3 +
drivers/pinctrl/mediatek/Kconfig | 6 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt6735.c | 880 ++++
drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h | 3993 +++++++++++++++++
5 files changed, 4883 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6735.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 315feb314732..6d4b69663b6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21287,6 +21287,9 @@ PIN CONTROLLER - MEDIATEK MT6735
M: Yassine Oudjana <y.oudjana@protonmail.com>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
+F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
+F: drivers/pinctrl/mediatek/pinctrl-mt6735.c
+F: drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h
F: include/dt-bindings/pinctrl/mediatek,mt6735-pinctrl.h
PIN CONTROLLER - MICROCHIP AT91
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 4819617d9368..3bbf56d4b4e6 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -148,6 +148,12 @@ config PINCTRL_MT2712
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK
+config PINCTRL_MT6735
+ bool "MediaTek MT6735(M) pin control"
+ depends on OF
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+
config PINCTRL_MT6765
tristate "MediaTek MT6765 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index ae765bd99965..98efce76d9fe 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
+obj-$(CONFIG_PINCTRL_MT6735) += pinctrl-mt6735.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6735.c b/drivers/pinctrl/mediatek/pinctrl-mt6735.c
new file mode 100644
index 000000000000..290ef6a95fa1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6735.c
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "pinctrl-mtk-mt6735.h"
+#include "pinctrl-paris.h"
+
+/* Common registers */
+#define GPIO_DIR 0x000
+#define GPIO_DOUT 0x100
+#define GPIO_DIN 0x200
+#define GPIO_MODE1 0x300
+#define GPIO_MODE2 0x310
+#define GPIO_MODE3 0x320
+#define GPIO_MODE4 0x330
+#define GPIO_MODE5 0x340
+#define GPIO_MODE6 0x350
+#define GPIO_MODE7 0x360
+#define GPIO_MODE8 0x370
+#define GPIO_MODE9 0x380
+#define GPIO_MODE10 0x390
+#define GPIO_MODE11 0x3a0
+#define GPIO_MODE12 0x3b0
+#define GPIO_MODE13 0x3c0
+#define GPIO_MODE14 0x3d0
+#define GPIO_MODE15 0x3e0
+#define GPIO_MODE16 0x3f0
+#define GPIO_MODE17 0x400
+#define GPIO_MODE18 0x410
+#define GPIO_MODE19 0x420
+#define GPIO_MODE20 0x430
+#define GPIO_MODE21 0x440
+
+/* Pin group registers */
+#define GPIO_IES 0x000 /* 16-bit */
+#define GPIO_SMT 0x010 /* 16-bit */
+#define GPIO_TDSEL 0x020 /* 32-bit */
+#define GPIO_RDSEL 0x028 /* 32-bit */
+#define GPIO_PULLEN 0x030 /* 32-bit */
+#define GPIO_PULLSEL 0x050 /* 32-bit */
+#define GPIO_DRV 0x070 /* 32-bit */
+#define GPIO_PUPD 0x080 /* 32-bit */
+
+/* Every pin has its own bit(s) */
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _s_width, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, _s_width, 0)
+
+/* All pins in the range share the same bit(s) */
+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _s_width, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, _s_width, 1)
+
+static const struct mtk_pin_field_calc mt6735_pin_dir_range[] = {
+ PIN_FIELD(0, 203, GPIO_DIR, 0x10, 0, 1)
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_di_range[] = {
+ PIN_FIELD(0, 203, GPIO_DIN, 0x10, 0, 1)
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_do_range[] = {
+ PIN_FIELD(0, 203, GPIO_DOUT, 0x10, 0, 1)
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_mode_range[] = {
+ PIN_FIELD(0, 4, GPIO_MODE1, 0, 0, 3),
+ PIN_FIELD(5, 9, GPIO_MODE1, 0, 16, 3),
+ PIN_FIELD(10, 14, GPIO_MODE2, 0, 0, 3),
+ PIN_FIELD(15, 19, GPIO_MODE2, 0, 16, 3),
+ PIN_FIELD(20, 24, GPIO_MODE3, 0, 0, 3),
+ PIN_FIELD(25, 29, GPIO_MODE3, 0, 16, 3),
+ PIN_FIELD(30, 34, GPIO_MODE4, 0, 0, 3),
+ PIN_FIELD(35, 39, GPIO_MODE4, 0, 16, 3),
+ PIN_FIELD(40, 44, GPIO_MODE5, 0, 0, 3),
+ PIN_FIELD(45, 49, GPIO_MODE5, 0, 16, 3),
+ PIN_FIELD(50, 54, GPIO_MODE6, 0, 0, 3),
+ PIN_FIELD(55, 59, GPIO_MODE6, 0, 16, 3),
+ PIN_FIELD(60, 64, GPIO_MODE7, 0, 0, 3),
+ PIN_FIELD(65, 69, GPIO_MODE7, 0, 16, 3),
+ PIN_FIELD(70, 74, GPIO_MODE8, 0, 0, 3),
+ PIN_FIELD(75, 79, GPIO_MODE8, 0, 16, 3),
+ PIN_FIELD(80, 84, GPIO_MODE9, 0, 0, 3),
+ PIN_FIELD(85, 89, GPIO_MODE9, 0, 16, 3),
+ PIN_FIELD(90, 94, GPIO_MODE10, 0, 0, 3),
+ PIN_FIELD(95, 99, GPIO_MODE10, 0, 16, 3),
+ PIN_FIELD(100, 104, GPIO_MODE11, 0, 0, 3),
+ PIN_FIELD(105, 109, GPIO_MODE11, 0, 16, 3),
+ PIN_FIELD(110, 114, GPIO_MODE12, 0, 0, 3),
+ PIN_FIELD(115, 119, GPIO_MODE12, 0, 16, 3),
+ PIN_FIELD(120, 124, GPIO_MODE13, 0, 0, 3),
+ PIN_FIELD(125, 129, GPIO_MODE13, 0, 16, 3),
+ PIN_FIELD(130, 134, GPIO_MODE14, 0, 0, 3),
+ PIN_FIELD(135, 139, GPIO_MODE14, 0, 16, 3),
+ PIN_FIELD(140, 144, GPIO_MODE15, 0, 0, 3),
+ PIN_FIELD(145, 149, GPIO_MODE15, 0, 16, 3),
+ PIN_FIELD(150, 154, GPIO_MODE16, 0, 0, 3),
+ PIN_FIELD(155, 159, GPIO_MODE16, 0, 16, 3),
+ PIN_FIELD(160, 164, GPIO_MODE17, 0, 0, 3),
+ PIN_FIELD(165, 169, GPIO_MODE17, 0, 16, 3),
+ PIN_FIELD(170, 174, GPIO_MODE18, 0, 0, 3),
+ PIN_FIELD(175, 179, GPIO_MODE18, 0, 16, 3),
+ PIN_FIELD(180, 184, GPIO_MODE19, 0, 0, 3),
+ PIN_FIELD(185, 189, GPIO_MODE19, 0, 16, 3),
+ PIN_FIELD(190, 194, GPIO_MODE20, 0, 0, 3),
+ PIN_FIELD(195, 199, GPIO_MODE20, 0, 16, 3),
+ PIN_FIELD(200, 203, GPIO_MODE21, 0, 0, 3),
+};
+
+
+static const struct mtk_pin_field_calc mt6735_pin_smt_range[] = {
+ PINS_FIELD_BASE(0, 4, 2, GPIO_SMT, 16, 0, 10, 1), /* EINT0~4 */
+ PINS_FIELD_BASE(5, 8, 3, GPIO_SMT, 16, 0, 3, 1), /* EINT5~8 */
+ PINS_FIELD_BASE(9, 12, 3, GPIO_SMT, 16, 0, 6, 1), /* EINT9~12 */
+ PINS_FIELD_BASE(13, 18, 1, GPIO_SMT, 16, 0, 0, 1), /* WB_CTRL */
+ PINS_FIELD_BASE(19, 21, 1, GPIO_SMT, 16, 0, 1, 1), /* ANTSEL */
+ PINS_FIELD_BASE(45, 46, 2, GPIO_SMT, 16, 0, 1, 1), /* CMMCLK */
+ PINS_FIELD_BASE(47, 48, 2, GPIO_SMT, 16, 0, 2, 1), /* I2C0 */
+ PINS_FIELD_BASE(49, 50, 2, GPIO_SMT, 16, 0, 3, 1), /* I2C1 */
+ PINS_FIELD_BASE(51, 52, 2, GPIO_SMT, 16, 0, 4, 1), /* I2C2 */
+ PINS_FIELD_BASE(53, 54, 2, GPIO_SMT, 16, 0, 5, 1), /* I2C3 */
+ PINS_FIELD_BASE(55, 55, 2, GPIO_SMT, 16, 0, 6, 1), /* SRCLKENAI */
+ PINS_FIELD_BASE(56, 56, 2, GPIO_SMT, 16, 0, 7, 1), /* SRCLKENA1 */
+ PINS_FIELD_BASE(57, 60, 2, GPIO_SMT, 16, 0, 8, 1), /* UART2/3 */
+ PINS_FIELD_BASE(61, 64, 2, GPIO_SMT, 16, 0, 9, 1), /* PCM */
+ PINS_FIELD_BASE(65, 68, 3, GPIO_SMT, 16, 0, 0, 1), /* SPI */
+ PINS_FIELD_BASE(69, 69, 3, GPIO_SMT, 16, 0, 1, 1), /* DISP_PWM */
+ PINS_FIELD_BASE(70, 73, 3, GPIO_SMT, 16, 0, 2, 1), /* JTAG */
+ PINS_FIELD_BASE(74, 77, 3, GPIO_SMT, 16, 0, 4, 1), /* UART0/1 */
+ PINS_FIELD_BASE(78, 80, 3, GPIO_SMT, 16, 0, 5, 1), /* I2S */
+ PINS_FIELD_BASE(81, 86, 3, GPIO_SMT, 16, 0, 7, 1), /* KEYPAD */
+ PINS_FIELD_BASE(87, 103, 3, GPIO_SMT, 16, 0, 8, 1), /* BPI5~20, C2K_TKBPI */
+ PINS_FIELD_BASE(104, 114, 3, GPIO_SMT, 16, 0, 9, 1), /* RFIC0/1 */
+ PINS_FIELD_BASE(118, 136, 4, GPIO_SMT, 16, 0, 0, 1), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */
+ PINS_FIELD_BASE(137, 137, 4, GPIO_SMT, 16, 0, 1, 1), /* RTC32K */
+ PINS_FIELD_BASE(138, 142, 4, GPIO_SMT, 16, 0, 2, 1), /* PWRAP */
+ PINS_FIELD_BASE(143, 145, 4, GPIO_SMT, 16, 0, 3, 1), /* AUD */
+ PINS_FIELD_BASE(146, 147, 4, GPIO_SMT, 16, 0, 4, 1), /* LCM_RST, DSI_TE */
+ PINS_FIELD_BASE(148, 148, 4, GPIO_SMT, 16, 0, 5, 1), /* SRCLKENA0 */
+ PINS_FIELD_BASE(149, 149, 4, GPIO_SMT, 16, 0, 1, 1), /* WATCHDOG */
+ PINS_FIELD_BASE(160, 162, 5, GPIO_SMT, 16, 0, 0, 1), /* SIM2 */
+ PINS_FIELD_BASE(163, 165, 4, GPIO_SMT, 16, 0, 1, 1), /* SIM1 */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_SMT, 16, 0, 2, 1), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_SMT, 16, 0, 3, 1), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 171, 5, GPIO_SMT, 16, 0, 4, 1), /* MSDC1_DAT */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_SMT, 16, 0, 0, 1), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_SMT, 16, 0, 1, 1), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_SMT, 16, 0, 2, 1), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 182, 6, GPIO_SMT, 16, 0, 3, 1), /* MSDC0_DAT */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_SMT, 16, 0, 4, 1), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(184, 185, 6, GPIO_SMT, 16, 0, 5, 1), /* FM */
+ PINS_FIELD_BASE(186, 189, 6, GPIO_SMT, 16, 0, 6, 1), /* WB SPI */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_SMT, 16, 0, 2, 1), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_SMT, 16, 0, 3, 1), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 203, 1, GPIO_SMT, 16, 0, 4, 1), /* MSDC2_DAT */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_ies_range[] = {
+ PINS_FIELD_BASE(0, 4, 2, GPIO_IES, 16, 0, 10, 1), /* EINT0~4 */
+ PINS_FIELD_BASE(5, 8, 3, GPIO_IES, 16, 0, 3, 1), /* EINT5~8 */
+ PINS_FIELD_BASE(9, 12, 3, GPIO_IES, 16, 0, 6, 1), /* EINT9~12 */
+ PINS_FIELD_BASE(13, 18, 1, GPIO_IES, 16, 0, 0, 1), /* WB_CTRL */
+ PINS_FIELD_BASE(19, 21, 1, GPIO_IES, 16, 0, 1, 1), /* ANTSEL */
+ PINS_FIELD_BASE(45, 46, 2, GPIO_IES, 16, 0, 1, 1), /* CMMCLK */
+ PINS_FIELD_BASE(47, 48, 2, GPIO_IES, 16, 0, 2, 1), /* I2C0 */
+ PINS_FIELD_BASE(49, 50, 2, GPIO_IES, 16, 0, 3, 1), /* I2C1 */
+ PINS_FIELD_BASE(51, 52, 2, GPIO_IES, 16, 0, 4, 1), /* I2C2 */
+ PINS_FIELD_BASE(53, 54, 2, GPIO_IES, 16, 0, 5, 1), /* I2C3 */
+ PINS_FIELD_BASE(55, 55, 2, GPIO_IES, 16, 0, 6, 1), /* SRCLKENAI */
+ PINS_FIELD_BASE(56, 56, 2, GPIO_IES, 16, 0, 7, 1), /* SRCLKENA1 */
+ PINS_FIELD_BASE(57, 60, 2, GPIO_IES, 16, 0, 8, 1), /* UART2/3 */
+ PINS_FIELD_BASE(61, 64, 2, GPIO_IES, 16, 0, 9, 1), /* PCM */
+ PINS_FIELD_BASE(65, 68, 3, GPIO_IES, 16, 0, 0, 1), /* SPI */
+ PINS_FIELD_BASE(69, 69, 3, GPIO_IES, 16, 0, 1, 1), /* DISP_PWM */
+ PINS_FIELD_BASE(70, 73, 3, GPIO_IES, 16, 0, 2, 1), /* JTAG */
+ PINS_FIELD_BASE(74, 77, 3, GPIO_IES, 16, 0, 4, 1), /* UART0/1 */
+ PINS_FIELD_BASE(78, 80, 3, GPIO_IES, 16, 0, 5, 1), /* I2S */
+ PINS_FIELD_BASE(81, 86, 3, GPIO_IES, 16, 0, 7, 1), /* KEYPAD */
+ PINS_FIELD_BASE(87, 103, 3, GPIO_IES, 16, 0, 8, 1), /* BPI5~20, C2K_TKBPI */
+ PINS_FIELD_BASE(104, 114, 3, GPIO_IES, 16, 0, 9, 1), /* RFIC0/1 */
+ PINS_FIELD_BASE(118, 136, 4, GPIO_IES, 16, 0, 0, 1), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */
+ PINS_FIELD_BASE(137, 137, 4, GPIO_IES, 16, 0, 1, 1), /* RTC32K */
+ PINS_FIELD_BASE(138, 142, 4, GPIO_IES, 16, 0, 2, 1), /* PWRAP */
+ PINS_FIELD_BASE(143, 145, 4, GPIO_IES, 16, 0, 3, 1), /* AUD */
+ PINS_FIELD_BASE(146, 147, 4, GPIO_IES, 16, 0, 4, 1), /* LCM_RST, DSI_TE */
+ PINS_FIELD_BASE(148, 148, 4, GPIO_IES, 16, 0, 5, 1), /* SRCLKENA0 */
+ PINS_FIELD_BASE(149, 149, 4, GPIO_IES, 16, 0, 1, 1), /* WATCHDOG */
+ PINS_FIELD_BASE(160, 162, 5, GPIO_IES, 16, 0, 0, 1), /* SIM2 */
+ PINS_FIELD_BASE(163, 165, 4, GPIO_IES, 16, 0, 1, 1), /* SIM1 */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_IES, 16, 0, 2, 1), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_IES, 16, 0, 3, 1), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 171, 5, GPIO_IES, 16, 0, 4, 1), /* MSDC1_DAT */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_IES, 16, 0, 0, 1), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_IES, 16, 0, 1, 1), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_IES, 16, 0, 2, 1), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 182, 6, GPIO_IES, 16, 0, 3, 1), /* MSDC0_DAT */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_IES, 16, 0, 4, 1), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(184, 185, 6, GPIO_IES, 16, 0, 5, 1), /* FM */
+ PINS_FIELD_BASE(186, 189, 6, GPIO_IES, 16, 0, 6, 1), /* WB SPI */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_IES, 16, 0, 2, 1), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_IES, 16, 0, 3, 1), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 203, 1, GPIO_IES, 16, 0, 4, 1) /* MSDC2_DAT */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_tdsel_range[] = {
+ PINS_FIELD_BASE(0, 4, 2, GPIO_TDSEL, 32, 0x04, 40, 4), /* EINT0~4 */
+ PINS_FIELD_BASE(5, 8, 3, GPIO_TDSEL, 32, 0x04, 12, 4), /* EINT5~8 */
+ PINS_FIELD_BASE(9, 12, 3, GPIO_TDSEL, 32, 0x04, 24, 4), /* EINT9~12 */
+ PINS_FIELD_BASE(13, 18, 1, GPIO_TDSEL, 32, 0, 0, 4), /* WB_CTRL */
+ PINS_FIELD_BASE(19, 21, 1, GPIO_TDSEL, 32, 0, 4, 4), /* ANTSEL */
+ PINS_FIELD_BASE(45, 46, 2, GPIO_TDSEL, 32, 0x04, 4, 4), /* CMMCLK */
+ PINS_FIELD_BASE(47, 48, 2, GPIO_TDSEL, 32, 0x04, 8, 4), /* I2C0 */
+ PINS_FIELD_BASE(49, 50, 2, GPIO_TDSEL, 32, 0x04, 12, 4), /* I2C1 */
+ PINS_FIELD_BASE(51, 52, 2, GPIO_TDSEL, 32, 0x04, 16, 4), /* I2C2 */
+ PINS_FIELD_BASE(53, 54, 2, GPIO_TDSEL, 32, 0x04, 20, 4), /* I2C3 */
+ PINS_FIELD_BASE(55, 55, 2, GPIO_TDSEL, 32, 0x04, 24, 4), /* SRCLKENAI */
+ PINS_FIELD_BASE(56, 56, 2, GPIO_TDSEL, 32, 0x04, 28, 4), /* SRCLKENA1 */
+ PINS_FIELD_BASE(57, 60, 2, GPIO_TDSEL, 32, 0x04, 32, 4), /* UART2/3 */
+ PINS_FIELD_BASE(61, 64, 2, GPIO_TDSEL, 32, 0x04, 36, 4), /* PCM */
+ PINS_FIELD_BASE(65, 68, 3, GPIO_TDSEL, 32, 0x04, 0, 4), /* SPI */
+ PINS_FIELD_BASE(69, 69, 3, GPIO_TDSEL, 32, 0x04, 4, 4), /* DISP_PWM */
+ PINS_FIELD_BASE(70, 73, 3, GPIO_TDSEL, 32, 0x04, 8, 4), /* JTAG */
+ PINS_FIELD_BASE(74, 77, 3, GPIO_TDSEL, 32, 0x04, 16, 4), /* UART0/1 */
+ PINS_FIELD_BASE(78, 80, 3, GPIO_TDSEL, 32, 0x04, 20, 4), /* I2S */
+ PINS_FIELD_BASE(81, 86, 3, GPIO_TDSEL, 32, 0x04, 28, 4), /* KEYPAD */
+ PINS_FIELD_BASE(87, 103, 3, GPIO_TDSEL, 32, 0x04, 32, 4), /* BPI5~20, C2K_TKBPI */
+ PINS_FIELD_BASE(104, 114, 3, GPIO_TDSEL, 32, 0x04, 36, 4), /* RFIC0/1 */
+ PINS_FIELD_BASE(118, 136, 4, GPIO_TDSEL, 32, 0, 0, 4), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */
+ PINS_FIELD_BASE(137, 137, 4, GPIO_TDSEL, 32, 0, 4, 4), /* RTC32K */
+ PINS_FIELD_BASE(138, 142, 4, GPIO_TDSEL, 32, 0, 8, 4), /* PWRAP */
+ PINS_FIELD_BASE(143, 145, 4, GPIO_TDSEL, 32, 0, 12, 4), /* AUD */
+ PINS_FIELD_BASE(146, 147, 4, GPIO_TDSEL, 32, 0, 16, 4), /* LCM_RST, DSI_TE */
+ PINS_FIELD_BASE(148, 148, 4, GPIO_TDSEL, 32, 0, 20, 4), /* SRCLKENA0 */
+ PINS_FIELD_BASE(149, 149, 4, GPIO_TDSEL, 32, 0, 4, 4), /* WATCHDOG */
+ PINS_FIELD_BASE(160, 162, 5, GPIO_TDSEL, 32, 0, 0, 4), /* SIM2 */
+ PINS_FIELD_BASE(163, 165, 5, GPIO_TDSEL, 32, 0, 4, 4), /* SIM1 */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 171, 5, GPIO_TDSEL, 32, 0, 16, 4), /* MSDC1_DAT */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_TDSEL, 32, 0, 0, 4), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_TDSEL, 32, 0, 4, 4), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 182, 6, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC0_DAT */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_TDSEL, 32, 0, 16, 4), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(184, 185, 6, GPIO_TDSEL, 32, 0, 20, 4), /* FM */
+ PINS_FIELD_BASE(186, 189, 6, GPIO_TDSEL, 32, 0, 24, 4), /* WB SPI */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_TDSEL, 32, 0, 8, 4), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_TDSEL, 32, 0, 12, 4), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 203, 1, GPIO_TDSEL, 32, 0, 16, 4) /* MSDC2_DAT */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_rdsel_range[] = {
+ PINS_FIELD_BASE(0, 4, 2, GPIO_RDSEL, 32, 0x04, 24, 2), /* EINT0~4 */
+ PINS_FIELD_BASE(5, 8, 3, GPIO_RDSEL, 32, 0, 6, 2), /* EINT5~8 */
+ PINS_FIELD_BASE(9, 12, 3, GPIO_RDSEL, 32, 0, 12, 2), /* EINT9~12 */
+ PINS_FIELD_BASE(13, 18, 1, GPIO_RDSEL, 32, 0, 0, 2), /* WB_CTRL */
+ PINS_FIELD_BASE(19, 21, 1, GPIO_RDSEL, 32, 0, 2, 2), /* ANTSEL */
+ PINS_FIELD_BASE(45, 46, 2, GPIO_RDSEL, 32, 0x04, 2, 6), /* CMMCLK */
+ PINS_FIELD_BASE(47, 48, 2, GPIO_RDSEL, 32, 0x04, 8, 2), /* I2C0 */
+ PINS_FIELD_BASE(49, 50, 2, GPIO_RDSEL, 32, 0x04, 10, 2), /* I2C1 */
+ PINS_FIELD_BASE(51, 52, 2, GPIO_RDSEL, 32, 0x04, 12, 2), /* I2C2 */
+ PINS_FIELD_BASE(53, 54, 2, GPIO_RDSEL, 32, 0x04, 14, 2), /* I2C3 */
+ PINS_FIELD_BASE(55, 55, 2, GPIO_RDSEL, 32, 0x04, 16, 2), /* SRCLKENAI */
+ PINS_FIELD_BASE(56, 56, 2, GPIO_RDSEL, 32, 0x04, 18, 2), /* SRCLKENA1 */
+ PINS_FIELD_BASE(57, 60, 2, GPIO_RDSEL, 32, 0x04, 20, 2), /* UART2/3 */
+ PINS_FIELD_BASE(61, 64, 2, GPIO_RDSEL, 32, 0x04, 22, 2), /* PCM */
+ PINS_FIELD_BASE(65, 68, 3, GPIO_RDSEL, 32, 0, 0, 2), /* SPI */
+ PINS_FIELD_BASE(69, 69, 3, GPIO_RDSEL, 32, 0, 2, 2), /* DISP_PWM */
+ PINS_FIELD_BASE(70, 73, 3, GPIO_RDSEL, 32, 0, 4, 2), /* JTAG */
+ PINS_FIELD_BASE(74, 77, 3, GPIO_RDSEL, 32, 0, 8, 2), /* UART0/1 */
+ PINS_FIELD_BASE(78, 80, 3, GPIO_RDSEL, 32, 0, 10, 2), /* I2S */
+ PINS_FIELD_BASE(81, 86, 3, GPIO_RDSEL, 32, 0, 14, 2), /* KEYPAD */
+ PINS_FIELD_BASE(87, 103, 3, GPIO_RDSEL, 32, 0, 16, 2), /* BPI5~20, C2K_TKBPI */
+ PINS_FIELD_BASE(104, 114, 3, GPIO_RDSEL, 32, 0, 18, 2), /* RFIC0/1 */
+ PINS_FIELD_BASE(118, 136, 4, GPIO_RDSEL, 32, 0, 0, 2), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */
+ PINS_FIELD_BASE(137, 137, 4, GPIO_RDSEL, 32, 0, 4, 2), /* RTC32K */
+ PINS_FIELD_BASE(138, 142, 4, GPIO_RDSEL, 32, 0, 6, 2), /* PWRAP */
+ PINS_FIELD_BASE(143, 145, 4, GPIO_RDSEL, 32, 0, 8, 2), /* AUD */
+ PINS_FIELD_BASE(146, 147, 4, GPIO_RDSEL, 32, 0, 10, 2), /* LCM_RST, DSI_TE */
+ PINS_FIELD_BASE(148, 148, 4, GPIO_RDSEL, 32, 0, 12, 2), /* SRCLKENA0 */
+ PINS_FIELD_BASE(149, 149, 4, GPIO_RDSEL, 32, 0, 4, 2), /* WATCHDOG */
+ PINS_FIELD_BASE(160, 162, 5, GPIO_RDSEL, 32, 0, 0, 6), /* SIM2 */
+ PINS_FIELD_BASE(163, 165, 5, GPIO_RDSEL, 32, 0, 6, 6), /* SIM1 */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_RDSEL, 32, 0, 12, 6), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_RDSEL, 32, 0, 18, 6), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 171, 5, GPIO_RDSEL, 32, 0, 24, 6), /* MSDC1_DAT */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_RDSEL, 32, 0, 0, 6), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_RDSEL, 32, 0, 6, 6), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_RDSEL, 32, 0, 12, 6), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 182, 6, GPIO_RDSEL, 32, 0, 18, 6), /* MSDC0_DAT */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_RDSEL, 32, 0, 24, 6), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(184, 185, 6, GPIO_RDSEL, 32, 0, 30, 2), /* FM */
+ PINS_FIELD_BASE(186, 189, 6, GPIO_RDSEL, 32, 0, 32, 2), /* WB SPI */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_RDSEL, 32, 0, 4, 6), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_RDSEL, 32, 0, 10, 6), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 203, 1, GPIO_RDSEL, 32, 0, 16, 6) /* MSDC2_DAT */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_drv_range[] = {
+ PINS_FIELD_BASE(0, 4, 2, GPIO_DRV, 32, 0x04, 41, 2), /* EINT0~4 */
+ PINS_FIELD_BASE(5, 8, 3, GPIO_DRV, 32, 0x04, 13, 2), /* EINT5~8 */
+ PINS_FIELD_BASE(9, 12, 3, GPIO_DRV, 32, 0x04, 25, 2), /* EINT9~12 */
+ PINS_FIELD_BASE(13, 18, 1, GPIO_DRV, 32, 0, 1, 2), /* WB_CTRL */
+ PINS_FIELD_BASE(19, 21, 1, GPIO_DRV, 32, 0, 5, 2), /* ANTSEL */
+ PINS_FIELD_BASE(45, 46, 2, GPIO_DRV, 32, 0x04, 4, 3), /* CMMCLK */
+ PINS_FIELD_BASE(55, 55, 2, GPIO_DRV, 32, 0x04, 25, 2), /* SRCLKENAI */
+ PINS_FIELD_BASE(56, 56, 2, GPIO_DRV, 32, 0x04, 29, 2), /* SRCLKENA1 */
+ PINS_FIELD_BASE(57, 60, 2, GPIO_DRV, 32, 0x04, 33, 2), /* UART2/3 */
+ PINS_FIELD_BASE(61, 64, 2, GPIO_DRV, 32, 0x04, 37, 2), /* PCM */
+ PINS_FIELD_BASE(65, 68, 3, GPIO_DRV, 32, 0x04, 1, 2), /* SPI */
+ PINS_FIELD_BASE(69, 69, 3, GPIO_DRV, 32, 0x04, 5, 2), /* DISP_PWM */
+ PINS_FIELD_BASE(70, 73, 3, GPIO_DRV, 32, 0x04, 9, 2), /* JTAG */
+ PINS_FIELD_BASE(74, 77, 3, GPIO_DRV, 32, 0x04, 17, 2), /* UART0/1 */
+ PINS_FIELD_BASE(78, 80, 3, GPIO_DRV, 32, 0x04, 21, 2), /* I2S */
+ PINS_FIELD_BASE(81, 86, 3, GPIO_DRV, 32, 0x04, 29, 2), /* KEYPAD */
+ PINS_FIELD_BASE(87, 103, 3, GPIO_DRV, 32, 0x04, 33, 2), /* BPI5~20, C2K_TKBPI */
+ PINS_FIELD_BASE(104, 114, 3, GPIO_DRV, 32, 0x04, 37, 2), /* RFIC0/1 */
+ PINS_FIELD_BASE(118, 136, 4, GPIO_DRV, 32, 0, 1, 2), /* LTE_TXBPI, BPI0~4, BPI21~27, PAVM */
+ PINS_FIELD_BASE(137, 137, 4, GPIO_DRV, 32, 0, 5, 2), /* RTC32K */
+ PINS_FIELD_BASE(138, 142, 4, GPIO_DRV, 32, 0, 9, 2), /* PWRAP */
+ PINS_FIELD_BASE(143, 145, 4, GPIO_DRV, 32, 0, 13, 2), /* AUD */
+ PINS_FIELD_BASE(146, 147, 4, GPIO_DRV, 32, 0, 17, 2), /* LCM_RST, DSI_TE */
+ PINS_FIELD_BASE(148, 148, 4, GPIO_DRV, 32, 0, 21, 2), /* SRCLKENA0 */
+ PINS_FIELD_BASE(149, 149, 4, GPIO_DRV, 32, 0, 5, 2), /* WATCHDOG */
+ PINS_FIELD_BASE(160, 162, 5, GPIO_DRV, 32, 0, 1, 2), /* SIM2 */
+ PINS_FIELD_BASE(163, 165, 5, GPIO_DRV, 32, 0, 5, 2), /* SIM1 */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_DRV, 32, 0, 9, 3), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_DRV, 32, 0, 12, 3), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 171, 5, GPIO_DRV, 32, 0, 16, 3), /* MSDC1_DAT */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_DRV, 32, 0, 0, 3), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_DRV, 32, 0, 4, 3), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_DRV, 32, 0, 8, 3), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 182, 6, GPIO_DRV, 32, 0, 12, 3), /* MSDC0_DAT */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_DRV, 32, 0, 16, 3), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(184, 185, 6, GPIO_DRV, 32, 0, 21, 2), /* FM */
+ PINS_FIELD_BASE(186, 189, 6, GPIO_DRV, 32, 0, 25, 2), /* WB SPI */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_DRV, 32, 0, 8, 3), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_DRV, 32, 0, 12, 3), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 203, 1, GPIO_DRV, 32, 0, 16, 3) /* MSDC2_DAT */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_r0_range[] = {
+ PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 0, 1), /* CMMCLK0 */
+ PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 4, 1), /* CMMCLK1 */
+ PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 0, 1), /* KPROW0 */
+ PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 4, 1), /* KPROW1 */
+ PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 8, 1), /* KPROW2 */
+ PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 16, 1), /* KPCOL0 */
+ PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 20, 1), /* KPCOL1 */
+ PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 24, 1), /* KPCOL2 */
+ PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 32, 1), /* SIM2_SCLK */
+ PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 36, 1), /* SIM2_SRST */
+ PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 44, 1), /* SIM2_SDAT */
+ PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 48, 1), /* SIM1_SCLK */
+ PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 52, 1), /* SIM1_SRST */
+ PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 56, 1), /* SIM1_SDAT */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 0, 1), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 4, 1), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 8, 1), /* MSDC1_DAT0 */
+ PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 12, 1), /* MSDC1_DAT1 */
+ PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 16, 1), /* MSDC1_DAT2 */
+ PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 20, 1), /* MSDC1_DAT3 */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 0, 1), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 8, 1), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 4, 1), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 12, 1), /* MSDC0_DAT0 */
+ PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 16, 1), /* MSDC0_DAT1 */
+ PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 20, 1), /* MSDC0_DAT2 */
+ PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 24, 1), /* MSDC0_DAT3 */
+ PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 28, 1), /* MSDC0_DAT4 */
+ PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 32, 1), /* MSDC0_DAT5 */
+ PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 36, 1), /* MSDC0_DAT6 */
+ PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 40, 1), /* MSDC0_DAT7 */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 44, 1), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 0, 1), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 4, 1), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 8, 1), /* MSDC2_DAT0 */
+ PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 12, 1), /* MSDC2_DAT1 */
+ PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 16, 1), /* MSDC2_DAT2 */
+ PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 20, 1) /* MSDC2_DAT3 */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_r1_range[] = {
+ PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 1, 1), /* CMMCLK0 */
+ PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 5, 1), /* CMMCLK1 */
+ PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 1, 1), /* KPROW0 */
+ PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 5, 1), /* KPROW1 */
+ PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 9, 1), /* KPROW2 */
+ PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 17, 1), /* KPCOL0 */
+ PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 21, 1), /* KPCOL1 */
+ PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 25, 1), /* KPCOL2 */
+ PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 33, 1), /* SIM2_SCLK */
+ PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 37, 1), /* SIM2_SRST */
+ PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 45, 1), /* SIM2_SDAT */
+ PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 49, 1), /* SIM1_SCLK */
+ PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 53, 1), /* SIM1_SRST */
+ PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 57, 1), /* SIM1_SDAT */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 1, 1), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 5, 1), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 9, 1), /* MSDC1_DAT0 */
+ PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 13, 1), /* MSDC1_DAT1 */
+ PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 17, 1), /* MSDC1_DAT2 */
+ PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 21, 1), /* MSDC1_DAT3 */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 1, 1), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 9, 1), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 5, 1), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 13, 1), /* MSDC0_DAT0 */
+ PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 17, 1), /* MSDC0_DAT1 */
+ PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 21, 1), /* MSDC0_DAT2 */
+ PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 25, 1), /* MSDC0_DAT3 */
+ PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 29, 1), /* MSDC0_DAT4 */
+ PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 33, 1), /* MSDC0_DAT5 */
+ PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 37, 1), /* MSDC0_DAT6 */
+ PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 41, 1), /* MSDC0_DAT7 */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 45, 1), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 1, 1), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 5, 1), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 9, 1), /* MSDC2_DAT0 */
+ PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 13, 1), /* MSDC2_DAT1 */
+ PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 17, 1), /* MSDC2_DAT2 */
+ PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 21, 1) /* MSDC2_DAT3 */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_pupd_range[] = {
+ PINS_FIELD_BASE(45, 45, 2, GPIO_PUPD, 32, 0, 2, 1), /* CMMCLK0 */
+ PINS_FIELD_BASE(46, 46, 2, GPIO_PUPD, 32, 0, 6, 1), /* CMMCLK1 */
+ PINS_FIELD_BASE(81, 81, 3, GPIO_PUPD, 32, 0, 2, 1), /* KPROW0 */
+ PINS_FIELD_BASE(82, 82, 3, GPIO_PUPD, 32, 0, 6, 1), /* KPROW1 */
+ PINS_FIELD_BASE(83, 83, 3, GPIO_PUPD, 32, 0, 10, 1), /* KPROW2 */
+ PINS_FIELD_BASE(84, 84, 3, GPIO_PUPD, 32, 0, 18, 1), /* KPCOL0 */
+ PINS_FIELD_BASE(85, 85, 3, GPIO_PUPD, 32, 0, 22, 1), /* KPCOL1 */
+ PINS_FIELD_BASE(86, 86, 3, GPIO_PUPD, 32, 0, 26, 1), /* KPCOL2 */
+ PINS_FIELD_BASE(160, 160, 5, GPIO_PUPD, 32, 0x10, 34, 1), /* SIM2_SCLK */
+ PINS_FIELD_BASE(161, 161, 5, GPIO_PUPD, 32, 0x10, 38, 1), /* SIM2_SRST */
+ PINS_FIELD_BASE(162, 162, 5, GPIO_PUPD, 32, 0x10, 46, 1), /* SIM2_SDAT */
+ PINS_FIELD_BASE(163, 163, 5, GPIO_PUPD, 32, 0x10, 50, 1), /* SIM1_SCLK */
+ PINS_FIELD_BASE(164, 164, 5, GPIO_PUPD, 32, 0x10, 54, 1), /* SIM1_SRST */
+ PINS_FIELD_BASE(165, 165, 5, GPIO_PUPD, 32, 0x10, 58, 1), /* SIM1_SDAT */
+ PINS_FIELD_BASE(166, 166, 5, GPIO_PUPD, 32, 0x10, 2, 1), /* MSDC1_CMD */
+ PINS_FIELD_BASE(167, 167, 5, GPIO_PUPD, 32, 0x10, 6, 1), /* MSDC1_CLK */
+ PINS_FIELD_BASE(168, 168, 5, GPIO_PUPD, 32, 0x10, 10, 1), /* MSDC1_DAT0 */
+ PINS_FIELD_BASE(169, 169, 5, GPIO_PUPD, 32, 0x10, 14, 1), /* MSDC1_DAT1 */
+ PINS_FIELD_BASE(170, 170, 5, GPIO_PUPD, 32, 0x10, 18, 1), /* MSDC1_DAT2 */
+ PINS_FIELD_BASE(171, 171, 5, GPIO_PUPD, 32, 0x10, 22, 1), /* MSDC1_DAT3 */
+ PINS_FIELD_BASE(172, 172, 6, GPIO_PUPD, 32, 0x10, 2, 1), /* MSDC0_CMD */
+ PINS_FIELD_BASE(173, 173, 6, GPIO_PUPD, 32, 0x10, 10, 1), /* MSDC0_DSL */
+ PINS_FIELD_BASE(174, 174, 6, GPIO_PUPD, 32, 0x10, 6, 1), /* MSDC0_CLK */
+ PINS_FIELD_BASE(175, 175, 6, GPIO_PUPD, 32, 0x10, 14, 1), /* MSDC0_DAT0 */
+ PINS_FIELD_BASE(176, 176, 6, GPIO_PUPD, 32, 0x10, 18, 1), /* MSDC0_DAT1 */
+ PINS_FIELD_BASE(177, 177, 6, GPIO_PUPD, 32, 0x10, 22, 1), /* MSDC0_DAT2 */
+ PINS_FIELD_BASE(178, 178, 6, GPIO_PUPD, 32, 0x10, 26, 1), /* MSDC0_DAT3 */
+ PINS_FIELD_BASE(179, 179, 6, GPIO_PUPD, 32, 0x10, 30, 1), /* MSDC0_DAT4 */
+ PINS_FIELD_BASE(180, 180, 6, GPIO_PUPD, 32, 0x10, 34, 1), /* MSDC0_DAT5 */
+ PINS_FIELD_BASE(181, 181, 6, GPIO_PUPD, 32, 0x10, 38, 1), /* MSDC0_DAT6 */
+ PINS_FIELD_BASE(182, 182, 6, GPIO_PUPD, 32, 0x10, 42, 1), /* MSDC0_DAT7 */
+ PINS_FIELD_BASE(183, 183, 6, GPIO_PUPD, 32, 0x10, 46, 1), /* MSDC0_RSTB */
+ PINS_FIELD_BASE(198, 198, 1, GPIO_PUPD, 32, 0, 2, 1), /* MSDC2_CMD */
+ PINS_FIELD_BASE(199, 199, 1, GPIO_PUPD, 32, 0, 6, 1), /* MSDC2_CLK */
+ PINS_FIELD_BASE(200, 200, 1, GPIO_PUPD, 32, 0, 10, 1), /* MSDC2_DAT0 */
+ PINS_FIELD_BASE(201, 201, 1, GPIO_PUPD, 32, 0, 14, 1), /* MSDC2_DAT1 */
+ PINS_FIELD_BASE(202, 202, 1, GPIO_PUPD, 32, 0, 18, 1), /* MSDC2_DAT2 */
+ PINS_FIELD_BASE(203, 203, 1, GPIO_PUPD, 32, 0, 22, 1) /* MSDC2_DAT3 */
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_pullen_range[] = {
+ PIN_FIELD_BASE(0, 4, 2, GPIO_PULLEN, 32, 0, 23, 1),
+ PIN_FIELD_BASE(5, 8, 3, GPIO_PULLEN, 32, 0x10, 9, 1),
+ PIN_FIELD_BASE(9, 12, 3, GPIO_PULLEN, 32, 0x10, 20, 1),
+ PIN_FIELD_BASE(13, 21, 1, GPIO_PULLEN, 32, 0, 0, 1),
+ PIN_FIELD_BASE(42, 44, 2, GPIO_PULLEN, 32, 0, 0, 1),
+ PIN_FIELD_BASE(47, 64, 2, GPIO_PULLEN, 32, 0, 5, 1),
+ PIN_FIELD_BASE(65, 73, 3, GPIO_PULLEN, 32, 0x10, 0, 1),
+ PIN_FIELD_BASE(74, 80, 3, GPIO_PULLEN, 32, 0x10, 13, 1),
+ PIN_FIELD_BASE(87, 114, 3, GPIO_PULLEN, 32, 0x10, 30, 1),
+ PIN_FIELD_BASE(118, 149, 4, GPIO_PULLEN, 32, 0, 0, 1),
+ PIN_FIELD_BASE(184, 189, 6, GPIO_PULLEN, 32, 0x10, 12, 1)
+};
+
+static const struct mtk_pin_field_calc mt6735_pin_pullsel_range[] = {
+ PIN_FIELD_BASE(0, 4, 2, GPIO_PULLSEL, 32, 0, 23, 1),
+ PIN_FIELD_BASE(5, 8, 3, GPIO_PULLSEL, 32, 0x10, 9, 1),
+ PIN_FIELD_BASE(9, 12, 3, GPIO_PULLSEL, 32, 0x10, 20, 1),
+ PIN_FIELD_BASE(13, 21, 1, GPIO_PULLSEL, 32, 0, 0, 1),
+ PIN_FIELD_BASE(42, 44, 2, GPIO_PULLSEL, 32, 0, 0, 1),
+ PIN_FIELD_BASE(47, 64, 2, GPIO_PULLSEL, 32, 0, 5, 1),
+ PIN_FIELD_BASE(65, 73, 3, GPIO_PULLSEL, 32, 0x10, 0, 1),
+ PIN_FIELD_BASE(74, 80, 3, GPIO_PULLSEL, 32, 0x10, 13, 1),
+ PIN_FIELD_BASE(87, 114, 3, GPIO_PULLSEL, 32, 0x10, 30, 1),
+ PIN_FIELD_BASE(118, 149, 4, GPIO_PULLSEL, 32, 0, 0, 1),
+ PIN_FIELD_BASE(184, 189, 6, GPIO_PULLSEL, 32, 0x10, 12, 1)
+};
+
+static const struct mtk_pin_reg_calc mt6735_reg_cals[] = {
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6735_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6735_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6735_pin_do_range),
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6735_pin_mode_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6735_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6735_pin_ies_range),
+ [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6735_pin_tdsel_range),
+ [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6735_pin_rdsel_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6735_pin_drv_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6735_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6735_pin_r1_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6735_pin_pupd_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6735_pin_pullen_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6735_pin_pullsel_range),
+};
+
+static const struct mtk_pin_field_calc mt6735m_pin_dir_range[] = {
+ PIN_FIELD(0, 197, GPIO_DIR, 0x10, 0, 1)
+};
+
+static const struct mtk_pin_field_calc mt6735m_pin_di_range[] = {
+ PIN_FIELD(0, 197, GPIO_DIN, 0x10, 0, 1)
+};
+
+static const struct mtk_pin_field_calc mt6735m_pin_do_range[] = {
+ PIN_FIELD(0, 197, GPIO_DOUT, 0x10, 0, 1)
+};
+
+static const struct mtk_pin_field_calc mt6735m_pin_mode_range[] = {
+ PIN_FIELD(0, 4, GPIO_MODE1, 0, 0, 3),
+ PIN_FIELD(5, 9, GPIO_MODE1, 0, 16, 3),
+ PIN_FIELD(10, 14, GPIO_MODE2, 0, 0, 3),
+ PIN_FIELD(15, 19, GPIO_MODE2, 0, 16, 3),
+ PIN_FIELD(20, 24, GPIO_MODE3, 0, 0, 3),
+ PIN_FIELD(25, 29, GPIO_MODE3, 0, 16, 3),
+ PIN_FIELD(30, 34, GPIO_MODE4, 0, 0, 3),
+ PIN_FIELD(35, 39, GPIO_MODE4, 0, 16, 3),
+ PIN_FIELD(40, 44, GPIO_MODE5, 0, 0, 3),
+ PIN_FIELD(45, 49, GPIO_MODE5, 0, 16, 3),
+ PIN_FIELD(50, 54, GPIO_MODE6, 0, 0, 3),
+ PIN_FIELD(55, 59, GPIO_MODE6, 0, 16, 3),
+ PIN_FIELD(60, 64, GPIO_MODE7, 0, 0, 3),
+ PIN_FIELD(65, 69, GPIO_MODE7, 0, 16, 3),
+ PIN_FIELD(70, 74, GPIO_MODE8, 0, 0, 3),
+ PIN_FIELD(75, 79, GPIO_MODE8, 0, 16, 3),
+ PIN_FIELD(80, 84, GPIO_MODE9, 0, 0, 3),
+ PIN_FIELD(85, 89, GPIO_MODE9, 0, 16, 3),
+ PIN_FIELD(90, 94, GPIO_MODE10, 0, 0, 3),
+ PIN_FIELD(95, 99, GPIO_MODE10, 0, 16, 3),
+ PIN_FIELD(100, 104, GPIO_MODE11, 0, 0, 3),
+ PIN_FIELD(105, 109, GPIO_MODE11, 0, 16, 3),
+ PIN_FIELD(110, 114, GPIO_MODE12, 0, 0, 3),
+ PIN_FIELD(115, 119, GPIO_MODE12, 0, 16, 3),
+ PIN_FIELD(120, 124, GPIO_MODE13, 0, 0, 3),
+ PIN_FIELD(125, 129, GPIO_MODE13, 0, 16, 3),
+ PIN_FIELD(130, 134, GPIO_MODE14, 0, 0, 3),
+ PIN_FIELD(135, 139, GPIO_MODE14, 0, 16, 3),
+ PIN_FIELD(140, 144, GPIO_MODE15, 0, 0, 3),
+ PIN_FIELD(145, 149, GPIO_MODE15, 0, 16, 3),
+ PIN_FIELD(150, 154, GPIO_MODE16, 0, 0, 3),
+ PIN_FIELD(155, 159, GPIO_MODE16, 0, 16, 3),
+ PIN_FIELD(160, 164, GPIO_MODE17, 0, 0, 3),
+ PIN_FIELD(165, 169, GPIO_MODE17, 0, 16, 3),
+ PIN_FIELD(170, 174, GPIO_MODE18, 0, 0, 3),
+ PIN_FIELD(175, 179, GPIO_MODE18, 0, 16, 3),
+ PIN_FIELD(180, 184, GPIO_MODE19, 0, 0, 3),
+ PIN_FIELD(185, 189, GPIO_MODE19, 0, 16, 3),
+ PIN_FIELD(190, 194, GPIO_MODE20, 0, 0, 3),
+ PIN_FIELD(195, 197, GPIO_MODE20, 0, 16, 3),
+};
+
+/*
+ * Rather than redefining all tables for MT6735M just to remove the 6 MSDC2
+ * pins at the end, reuse the MT6735 tables and exclude the MSDC2 pin fields
+ * by subtracting their count from the array size when possible
+ */
+static const struct mtk_pin_reg_calc mt6735m_reg_cals[] = {
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6735m_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6735m_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6735m_pin_do_range),
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6735m_pin_mode_range),
+ [PINCTRL_PIN_REG_SMT] = { mt6735_pin_smt_range,
+ ARRAY_SIZE(mt6735_pin_smt_range) - 3 },
+ [PINCTRL_PIN_REG_IES] = { mt6735_pin_ies_range,
+ ARRAY_SIZE(mt6735_pin_ies_range) - 3 },
+ [PINCTRL_PIN_REG_TDSEL] = { mt6735_pin_tdsel_range,
+ ARRAY_SIZE(mt6735_pin_tdsel_range) - 3 },
+ [PINCTRL_PIN_REG_RDSEL] = { mt6735_pin_rdsel_range,
+ ARRAY_SIZE(mt6735_pin_rdsel_range) - 3 },
+ [PINCTRL_PIN_REG_DRV] = { mt6735_pin_drv_range,
+ ARRAY_SIZE(mt6735_pin_drv_range) - 3 },
+ [PINCTRL_PIN_REG_R0] = { mt6735_pin_r0_range,
+ ARRAY_SIZE(mt6735_pin_r0_range) - 6 },
+ [PINCTRL_PIN_REG_R1] = { mt6735_pin_r1_range,
+ ARRAY_SIZE(mt6735_pin_r1_range) - 6 },
+ [PINCTRL_PIN_REG_PUPD] = { mt6735_pin_pupd_range,
+ ARRAY_SIZE(mt6735_pin_pupd_range) - 6 },
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6735_pin_pullen_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6735_pin_pullsel_range),
+};
+
+static const unsigned int mt6735_pull_type[] = {
+ MTK_PULL_PULLSEL_TYPE, /* 0 */
+ MTK_PULL_PULLSEL_TYPE, /* 1 */
+ MTK_PULL_PULLSEL_TYPE, /* 2 */
+ MTK_PULL_PULLSEL_TYPE, /* 3 */
+ MTK_PULL_PULLSEL_TYPE, /* 4 */
+ MTK_PULL_PULLSEL_TYPE, /* 5 */
+ MTK_PULL_PULLSEL_TYPE, /* 6 */
+ MTK_PULL_PULLSEL_TYPE, /* 7 */
+ MTK_PULL_PULLSEL_TYPE, /* 8 */
+ MTK_PULL_PULLSEL_TYPE, /* 9 */
+ MTK_PULL_PULLSEL_TYPE, /* 10 */
+ MTK_PULL_PULLSEL_TYPE, /* 11 */
+ MTK_PULL_PULLSEL_TYPE, /* 12 */
+ MTK_PULL_PULLSEL_TYPE, /* 13 */
+ MTK_PULL_PULLSEL_TYPE, /* 14 */
+ MTK_PULL_PULLSEL_TYPE, /* 15 */
+ MTK_PULL_PULLSEL_TYPE, /* 16 */
+ MTK_PULL_PULLSEL_TYPE, /* 17 */
+ MTK_PULL_PULLSEL_TYPE, /* 18 */
+ MTK_PULL_PULLSEL_TYPE, /* 19 */
+ MTK_PULL_PULLSEL_TYPE, /* 20 */
+ MTK_PULL_PULLSEL_TYPE, /* 21 */
+ /* MIPI CSI pins have no configurable pull resistors */
+ 0, /* 22 RDN0 */
+ 0, /* 23 RDP0 */
+ 0, /* 24 RDN1 */
+ 0, /* 25 RDP1 */
+ 0, /* 26 RCN */
+ 0, /* 27 RCP */
+ 0, /* 28 RDN2 */
+ 0, /* 29 RDP2 */
+ 0, /* 30 RDN3 */
+ 0, /* 31 RDP3 */
+ 0, /* 32 RDN0_A */
+ 0, /* 33 RDP0_A */
+ 0, /* 34 RDN1_A */
+ 0, /* 35 RDP1_A */
+ 0, /* 36 RCN_A */
+ 0, /* 37 RCP_A */
+ 0, /* 38 RDN2_A */
+ 0, /* 39 RDP2_A */
+ 0, /* 40 RDN3_A */
+ 0, /* 41 RDP3_A */
+ MTK_PULL_PULLSEL_TYPE, /* 42 */
+ MTK_PULL_PULLSEL_TYPE, /* 43 */
+ MTK_PULL_PULLSEL_TYPE, /* 44 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 45 CMMCLK0 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 46 CMMCLK1 */
+ MTK_PULL_PULLSEL_TYPE, /* 47 */
+ MTK_PULL_PULLSEL_TYPE, /* 48 */
+ MTK_PULL_PULLSEL_TYPE, /* 49 */
+ MTK_PULL_PULLSEL_TYPE, /* 50 */
+ MTK_PULL_PULLSEL_TYPE, /* 51 */
+ MTK_PULL_PULLSEL_TYPE, /* 52 */
+ MTK_PULL_PULLSEL_TYPE, /* 53 */
+ MTK_PULL_PULLSEL_TYPE, /* 54 */
+ MTK_PULL_PULLSEL_TYPE, /* 55 */
+ MTK_PULL_PULLSEL_TYPE, /* 56 */
+ MTK_PULL_PULLSEL_TYPE, /* 57 */
+ MTK_PULL_PULLSEL_TYPE, /* 58 */
+ MTK_PULL_PULLSEL_TYPE, /* 60 */
+ MTK_PULL_PULLSEL_TYPE, /* 61 */
+ MTK_PULL_PULLSEL_TYPE, /* 62 */
+ MTK_PULL_PULLSEL_TYPE, /* 63 */
+ MTK_PULL_PULLSEL_TYPE, /* 64 */
+ MTK_PULL_PULLSEL_TYPE, /* 65 */
+ MTK_PULL_PULLSEL_TYPE, /* 66 */
+ MTK_PULL_PULLSEL_TYPE, /* 67 */
+ MTK_PULL_PULLSEL_TYPE, /* 68 */
+ MTK_PULL_PULLSEL_TYPE, /* 69 */
+ MTK_PULL_PULLSEL_TYPE, /* 70 */
+ MTK_PULL_PULLSEL_TYPE, /* 71 */
+ MTK_PULL_PULLSEL_TYPE, /* 72 */
+ MTK_PULL_PULLSEL_TYPE, /* 73 */
+ MTK_PULL_PULLSEL_TYPE, /* 74 */
+ MTK_PULL_PULLSEL_TYPE, /* 75 */
+ MTK_PULL_PULLSEL_TYPE, /* 76 */
+ MTK_PULL_PULLSEL_TYPE, /* 77 */
+ MTK_PULL_PULLSEL_TYPE, /* 78 */
+ MTK_PULL_PULLSEL_TYPE, /* 79 */
+ MTK_PULL_PULLSEL_TYPE, /* 80 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 81 KROW0 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 82 KROW1 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 83 KROW2 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 84 KCOL0 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 85 KCOL1 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 86 KCOL2 */
+ MTK_PULL_PULLSEL_TYPE, /* 87 */
+ MTK_PULL_PULLSEL_TYPE, /* 88 */
+ MTK_PULL_PULLSEL_TYPE, /* 89 */
+ MTK_PULL_PULLSEL_TYPE, /* 90 */
+ MTK_PULL_PULLSEL_TYPE, /* 91 */
+ MTK_PULL_PULLSEL_TYPE, /* 92 */
+ MTK_PULL_PULLSEL_TYPE, /* 93 */
+ MTK_PULL_PULLSEL_TYPE, /* 94 */
+ MTK_PULL_PULLSEL_TYPE, /* 95 */
+ MTK_PULL_PULLSEL_TYPE, /* 96 */
+ MTK_PULL_PULLSEL_TYPE, /* 97 */
+ MTK_PULL_PULLSEL_TYPE, /* 98 */
+ MTK_PULL_PULLSEL_TYPE, /* 99 */
+ MTK_PULL_PULLSEL_TYPE, /* 100 */
+ MTK_PULL_PULLSEL_TYPE, /* 101 */
+ MTK_PULL_PULLSEL_TYPE, /* 102 */
+ MTK_PULL_PULLSEL_TYPE, /* 103 */
+ MTK_PULL_PULLSEL_TYPE, /* 104 */
+ MTK_PULL_PULLSEL_TYPE, /* 105 */
+ MTK_PULL_PULLSEL_TYPE, /* 106 */
+ MTK_PULL_PULLSEL_TYPE, /* 107 */
+ MTK_PULL_PULLSEL_TYPE, /* 108 */
+ MTK_PULL_PULLSEL_TYPE, /* 109 */
+ MTK_PULL_PULLSEL_TYPE, /* 110 */
+ MTK_PULL_PULLSEL_TYPE, /* 111 */
+ MTK_PULL_PULLSEL_TYPE, /* 112 */
+ MTK_PULL_PULLSEL_TYPE, /* 113 */
+ MTK_PULL_PULLSEL_TYPE, /* 114 */
+ /* Configuration for AUXADC pins is set by APMIXEDSYS */
+ 0, /* 115 AUXIN0 */
+ 0, /* 116 AUXIN1 */
+ 0, /* 117 AUXIN2 */
+ MTK_PULL_PULLSEL_TYPE, /* 118 */
+ MTK_PULL_PULLSEL_TYPE, /* 119 */
+ MTK_PULL_PULLSEL_TYPE, /* 120 */
+ MTK_PULL_PULLSEL_TYPE, /* 121 */
+ MTK_PULL_PULLSEL_TYPE, /* 122 */
+ MTK_PULL_PULLSEL_TYPE, /* 123 */
+ MTK_PULL_PULLSEL_TYPE, /* 124 */
+ MTK_PULL_PULLSEL_TYPE, /* 125 */
+ MTK_PULL_PULLSEL_TYPE, /* 126 */
+ MTK_PULL_PULLSEL_TYPE, /* 127 */
+ MTK_PULL_PULLSEL_TYPE, /* 128 */
+ MTK_PULL_PULLSEL_TYPE, /* 129 */
+ MTK_PULL_PULLSEL_TYPE, /* 130 */
+ MTK_PULL_PULLSEL_TYPE, /* 131 */
+ MTK_PULL_PULLSEL_TYPE, /* 132 */
+ MTK_PULL_PULLSEL_TYPE, /* 133 */
+ MTK_PULL_PULLSEL_TYPE, /* 134 */
+ MTK_PULL_PULLSEL_TYPE, /* 135 */
+ MTK_PULL_PULLSEL_TYPE, /* 136 */
+ MTK_PULL_PULLSEL_TYPE, /* 137 */
+ MTK_PULL_PULLSEL_TYPE, /* 138 */
+ MTK_PULL_PULLSEL_TYPE, /* 139 */
+ MTK_PULL_PULLSEL_TYPE, /* 140 */
+ MTK_PULL_PULLSEL_TYPE, /* 141 */
+ MTK_PULL_PULLSEL_TYPE, /* 142 */
+ MTK_PULL_PULLSEL_TYPE, /* 143 */
+ MTK_PULL_PULLSEL_TYPE, /* 144 */
+ MTK_PULL_PULLSEL_TYPE, /* 145 */
+ MTK_PULL_PULLSEL_TYPE, /* 146 */
+ MTK_PULL_PULLSEL_TYPE, /* 147 */
+ MTK_PULL_PULLSEL_TYPE, /* 148 */
+ MTK_PULL_PULLSEL_TYPE, /* 149 */
+ /* MIPI DSI pins have no configurable pull resistors */
+ 0, /* 150 TDP0 */
+ 0, /* 151 TDN0 */
+ 0, /* 152 TDP1 */
+ 0, /* 153 TDN1 */
+ 0, /* 154 TCP */
+ 0, /* 155 TCN */
+ 0, /* 156 TDP2 */
+ 0, /* 157 TDN2 */
+ 0, /* 158 TDP3 */
+ 0, /* 159 TDN3 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 160 MD_SIM2_SCLK */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 161 MD_SIM2_SRST */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 162 MD_SIM2_SDAT */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 163 MD_SIM1_SCLK */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 164 MD_SIM1_SRST */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 165 MD_SIM1_SDAT */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 166 MSDC1_CMD */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 167 MSDC1_CLK */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 168 MSDC1_DAT0 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 169 MSDC1_DAT1 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 170 MSDC1_DAT2 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 171 MSDC1_DAT3 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 172 MSDC0_CMD */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 173 MSDC0_DSL */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 174 MSDC0_CLK */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 175 MSDC0_DAT0 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 176 MSDC0_DAT1 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 177 MSDC0_DAT2 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 178 MSDC0_DAT3 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 179 MSDC0_DAT4 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 180 MSDC0_DAT5 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 181 MSDC0_DAT6 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 182 MSDC0_DAT7 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 183 MSDC0_RSTB */
+ MTK_PULL_PULLSEL_TYPE, /* 184 */
+ MTK_PULL_PULLSEL_TYPE, /* 185 */
+ MTK_PULL_PULLSEL_TYPE, /* 186 */
+ MTK_PULL_PULLSEL_TYPE, /* 187 */
+ MTK_PULL_PULLSEL_TYPE, /* 188 */
+ MTK_PULL_PULLSEL_TYPE, /* 189 */
+ /*
+ * GPS/WIFI/BT pins have no pull resistors configurable by the GPIO
+ * controller. They might be configured by CONSYS but we can't know
+ * for sure due to lack of documentation.
+ */
+ 0, /* 190 GPS_RXQN */
+ 0, /* 191 GPS_RXQP */
+ 0, /* 192 GPS_RXIN */
+ 0, /* 193 GPS_RXIP */
+ 0, /* 194 WB_RXQN */
+ 0, /* 195 WB_RXQP */
+ 0, /* 196 WB_RXIN */
+ 0, /* 197 WB_RXIP */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 198 MSDC2_CMD */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 199 MSDC2_CLK */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 200 MSDC2_DAT0 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 201 MSDC2_DAT1 */
+ MTK_PULL_PUPD_R1R0_TYPE, /* 202 MSDC2_DAT2 */
+ MTK_PULL_PUPD_R1R0_TYPE /* 203 MSDC2_DAT3 */
+};
+
+static const char * const mt6735_pinctrl_register_base_names[] = {
+ "gpio", "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5"
+};
+
+static const struct mtk_eint_hw mt6735_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num = 224,
+ .db_cnt = 16,
+};
+
+static const struct mtk_pin_soc mt6735_data = {
+ .reg_cal = mt6735_reg_cals,
+ .pins = mtk_pins_mt6735,
+ .npins = ARRAY_SIZE(mtk_pins_mt6735),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt6735),
+ .eint_hw = &mt6735_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mt6735_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt6735_pinctrl_register_base_names),
+ .pull_type = mt6735_pull_type,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct mtk_pin_soc mt6735m_data = {
+ .reg_cal = mt6735m_reg_cals,
+ .pins = mtk_pins_mt6735m,
+ .npins = ARRAY_SIZE(mtk_pins_mt6735m),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt6735m),
+ .eint_hw = &mt6735_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mt6735_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt6735_pinctrl_register_base_names),
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct of_device_id mt6735_pinctrl_match[] = {
+ { .compatible = "mediatek,mt6735-pinctrl", .data = &mt6735_data },
+ { .compatible = "mediatek,mt6735m-pinctrl", .data = &mt6735m_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mt6735_pinctrl_match);
+
+static struct platform_driver mt6735_pinctrl_driver = {
+ .probe = mtk_paris_pinctrl_probe,
+ .driver = {
+ .name = "mt6735-pinctrl",
+ .of_match_table = mt6735_pinctrl_match,
+ .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops),
+ },
+};
+module_platform_driver(mt6735_pinctrl_driver);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("MediaTek MT6735 pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h
new file mode 100644
index 000000000000..6662dadb5b1b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h
@@ -0,0 +1,3993 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#ifndef __PINCTRL_MTK_MT6735_H
+#define __PINCTRL_MTK_MT6735_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt6735[] = {
+ MTK_PIN(
+ 0, "GPIO0",
+ MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "DPI_D4"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "KCOL2"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT0")
+ ),
+ MTK_PIN(
+ 1, "GPIO1",
+ MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "DPI_D5"),
+ MTK_FUNCTION(3, "MD_EINT0"),
+ MTK_FUNCTION(4, "TDD_TDO"),
+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT1")
+ ),
+ MTK_PIN(
+ 2, "GPIO2",
+ MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "CLKM0"),
+ MTK_FUNCTION(2, "DPI_D6"),
+ MTK_FUNCTION(3, "MD_EINT0"),
+ MTK_FUNCTION(4, "USB_DRVVBUS"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(6, "PTA_TXD"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT2")
+ ),
+ MTK_PIN(
+ 3, "GPIO3",
+ MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "CLKM1"),
+ MTK_FUNCTION(2, "DPI_D7"),
+ MTK_FUNCTION(3, "SPI_MIB"),
+ MTK_FUNCTION(4, "MD_EINT0"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT3")
+ ),
+ MTK_PIN(
+ 4, "GPIO4",
+ MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "CLKM2"),
+ MTK_FUNCTION(2, "DPI_D8"),
+ MTK_FUNCTION(3, "SPI_MOB"),
+ MTK_FUNCTION(4, "TDD_TCK"),
+ MTK_FUNCTION(5, "CONN_MCU_TCK[0]"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(7, "C2K_DM_EINT0")
+ ),
+ MTK_PIN(
+ 5, "GPIO5",
+ MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION(2, "DPI_D9"),
+ MTK_FUNCTION(3, "SPI_CSB"),
+ MTK_FUNCTION(4, "TDD_TDI"),
+ MTK_FUNCTION(5, "CONN_MCU_TDI"),
+ MTK_FUNCTION(6, "I2S1_DO"),
+ MTK_FUNCTION(7, "MD_URXD")
+ ),
+ MTK_PIN(
+ 6, "GPIO6",
+ MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION(2, "DPI_D10"),
+ MTK_FUNCTION(3, "SPI_CKB"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "I2S1_LRCK"),
+ MTK_FUNCTION(7, "MD_UTXD")
+ ),
+ MTK_PIN(
+ 7, "GPIO7",
+ MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "UCTS3"),
+ MTK_FUNCTION(2, "DPI_D11"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "TDD_TMS"),
+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
+ MTK_FUNCTION(6, "I2S1_BCK"),
+ MTK_FUNCTION(7, "TDD_TXD")
+ ),
+ MTK_PIN(
+ 8, "GPIO8",
+ MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "URTS3"),
+ MTK_FUNCTION(2, "C2K_UIM0_HOT_PLUG_IN"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "PCM1_DO1"),
+ MTK_FUNCTION(5, "MD_EINT1"),
+ MTK_FUNCTION(6, "KCOL4"),
+ MTK_FUNCTION(7, "UTXD0")
+ ),
+ MTK_PIN(
+ 9, "GPIO9",
+ MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(2, "PCM1_DO0"),
+ MTK_FUNCTION(3, "I2S3_MCK"),
+ MTK_FUNCTION(4, "MD_EINT2"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, "I2S1_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_A29")
+ ),
+ MTK_PIN(
+ 10, "GPIO10",
+ MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "KROW2"),
+ MTK_FUNCTION(4, "MD_EINT0"),
+ MTK_FUNCTION(5, "I2S1_MCK"),
+ MTK_FUNCTION(6, "SDA3"),
+ MTK_FUNCTION(7, "DBG_MON_A30")
+ ),
+ MTK_PIN(
+ 11, "GPIO11",
+ MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "MD_EINT1"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "C2K_UIM0_HOT_PLUG_IN"),
+ MTK_FUNCTION(4, "CLKM0"),
+ MTK_FUNCTION(5, "I2S2_MCK"),
+ MTK_FUNCTION(6, "SCL3"),
+ MTK_FUNCTION(7, "URXD0")
+ ),
+ MTK_PIN(
+ 12, "GPIO12",
+ MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(3, "KCOL2"),
+ MTK_FUNCTION(4, "MD_EINT2"),
+ MTK_FUNCTION(5, "IRTX_OUT"),
+ MTK_FUNCTION(6, "SRCLKENAI2"),
+ MTK_FUNCTION(7, "PCM1_DO1")
+ ),
+ MTK_PIN(
+ 13, "GPIO13",
+ MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "WB_CTRL0"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT0"),
+ MTK_FUNCTION(7, "DBG_MON_A0")
+ ),
+ MTK_PIN(
+ 14, "GPIO14",
+ MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "WB_CTRL1"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT1"),
+ MTK_FUNCTION(7, "DBG_MON_A1")
+ ),
+ MTK_PIN(
+ 15, "GPIO15",
+ MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "WB_CTRL2"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT2"),
+ MTK_FUNCTION(7, "DBG_MON_A2")
+ ),
+ MTK_PIN(
+ 16, "GPIO16",
+ MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "WB_CTRL3"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT3"),
+ MTK_FUNCTION(7, "DBG_MON_A3")
+ ),
+ MTK_PIN(
+ 17, "GPIO17",
+ MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "WB_CTRL4"),
+ MTK_FUNCTION(3, "C2K_DM_EINT0"),
+ MTK_FUNCTION(4, "WATCHDOG"),
+ MTK_FUNCTION(7, "DBG_MON_A4")
+ ),
+ MTK_PIN(
+ 18, "GPIO18",
+ MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "WB_CTRL5"),
+ MTK_FUNCTION(3, "C2K_DM_EINT1"),
+ MTK_FUNCTION(7, "DBG_MON_A5")
+ ),
+ MTK_PIN(
+ 19, "GPIO19",
+ MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "ANT_SEL0"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "IRDA_TX"),
+ MTK_FUNCTION(4, "C2K_UART0_TXD"),
+ MTK_FUNCTION(5, "GPS_FRAME_SYNC"),
+ MTK_FUNCTION(6, "LTE_UTXD"),
+ MTK_FUNCTION(7, "DBG_MON_A6")
+ ),
+ MTK_PIN(
+ 20, "GPIO20",
+ MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "ANT_SEL1"),
+ MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(3, "IRDA_RX"),
+ MTK_FUNCTION(4, "C2K_UART0_RXD"),
+ MTK_FUNCTION(5, "MD_EINT2"),
+ MTK_FUNCTION(6, "LTE_URXD"),
+ MTK_FUNCTION(7, "DBG_MON_A7")
+ ),
+ MTK_PIN(
+ 21, "GPIO21",
+ MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "ANT_SEL2"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "IRDA_PDN"),
+ MTK_FUNCTION(4, "CORESONIC_SWCK"),
+ MTK_FUNCTION(5, "MD_EINT1"),
+ MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN"),
+ MTK_FUNCTION(7, "DBG_MON_A8")
+ ),
+ MTK_PIN(
+ 22, "GPIO22",
+ MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "RDN0")
+ ),
+ MTK_PIN(
+ 23, "GPIO23",
+ MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "RDP0")
+ ),
+ MTK_PIN(
+ 24, "GPIO24",
+ MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "RDN1")
+ ),
+ MTK_PIN(
+ 25, "GPIO25",
+ MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "RDP1")
+ ),
+ MTK_PIN(
+ 26, "GPIO26",
+ MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "RCN")
+ ),
+ MTK_PIN(
+ 27, "GPIO27",
+ MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "RCP")
+ ),
+ MTK_PIN(
+ 28, "GPIO28",
+ MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "RDN2")
+ ),
+ MTK_PIN(
+ 29, "GPIO29",
+ MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "RDP2")
+ ),
+ MTK_PIN(
+ 30, "GPIO30",
+ MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "RDN3")
+ ),
+ MTK_PIN(
+ 31, "GPIO31",
+ MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "RDP3")
+ ),
+ MTK_PIN(
+ 32, "GPIO32",
+ MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "RDN0_A"),
+ MTK_FUNCTION(2, "CMHSYNC"),
+ MTK_FUNCTION(3, "CMCSD0")
+ ),
+ MTK_PIN(
+ 33, "GPIO33",
+ MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "RDP0_A"),
+ MTK_FUNCTION(2, "CMVSYNC"),
+ MTK_FUNCTION(3, "CMCSD1")
+ ),
+ MTK_PIN(
+ 34, "GPIO34",
+ MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "RDN1_A"),
+ MTK_FUNCTION(2, "CMDAT9"),
+ MTK_FUNCTION(3, "CMCSD2")
+ ),
+ MTK_PIN(
+ 35, "GPIO35",
+ MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "RDP1_A"),
+ MTK_FUNCTION(2, "CMDAT8"),
+ MTK_FUNCTION(3, "CMCSD3")
+ ),
+ MTK_PIN(
+ 36, "GPIO36",
+ MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "RCN_A"),
+ MTK_FUNCTION(2, "CMDAT7")
+ ),
+ MTK_PIN(
+ 37, "GPIO37",
+ MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "RCP_A"),
+ MTK_FUNCTION(2, "CMDAT6")
+ ),
+ MTK_PIN(
+ 38, "GPIO38",
+ MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "RDN2_A"),
+ MTK_FUNCTION(2, "CMDAT5")
+ ),
+ MTK_PIN(
+ 39, "GPIO39",
+ MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "RDP2_A"),
+ MTK_FUNCTION(2, "CMDAT4")
+ ),
+ MTK_PIN(
+ 40, "GPIO40",
+ MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "RDN3_A"),
+ MTK_FUNCTION(2, "CMDAT3")
+ ),
+ MTK_PIN(
+ 41, "GPIO41",
+ MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "RDP3_A"),
+ MTK_FUNCTION(2, "CMDAT2")
+ ),
+ MTK_PIN(
+ 42, "GPIO42",
+ MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "CMDAT0"),
+ MTK_FUNCTION(2, "CMCSD0"),
+ MTK_FUNCTION(3, "CMMCLK1"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "CLKM5"),
+ MTK_FUNCTION(7, "DBG_MON_A9")
+ ),
+ MTK_PIN(
+ 43, "GPIO43",
+ MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "CMDAT1"),
+ MTK_FUNCTION(2, "CMCSD1"),
+ MTK_FUNCTION(3, "CMFLASH"),
+ MTK_FUNCTION(4, "MD_EINT0"),
+ MTK_FUNCTION(5, "CMMCLK1"),
+ MTK_FUNCTION(6, "CLKM4"),
+ MTK_FUNCTION(7, "DBG_MON_A10")
+ ),
+ MTK_PIN(
+ 44, "GPIO44",
+ MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "CMPCLK"),
+ MTK_FUNCTION(2, "CMCSK"),
+ MTK_FUNCTION(3, "CMCSD2"),
+ MTK_FUNCTION(4, "KCOL3"),
+ MTK_FUNCTION(5, "SRCLKENAI2"),
+ MTK_FUNCTION(6, "PWM0"),
+ MTK_FUNCTION(7, "DBG_MON_A11")
+ ),
+ MTK_PIN(
+ 45, "GPIO45",
+ MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "CMMCLK0"),
+ MTK_FUNCTION(7, "DBG_MON_A12")
+ ),
+ MTK_PIN(
+ 46, "GPIO46",
+ MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "CMMCLK1"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "DM_JTINTP"),
+ MTK_FUNCTION(6, "KCOL6"),
+ MTK_FUNCTION(7, "DBG_MON_A13")
+ ),
+ MTK_PIN(
+ 47, "GPIO47",
+ MTK_EINT_FUNCTION(0, 47),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ 48, "GPIO48",
+ MTK_EINT_FUNCTION(0, 48),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ 49, "GPIO49",
+ MTK_EINT_FUNCTION(0, 49),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(
+ 50, "GPIO50",
+ MTK_EINT_FUNCTION(0, 50),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(
+ 51, "GPIO51",
+ MTK_EINT_FUNCTION(0, 51),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(
+ 52, "GPIO52",
+ MTK_EINT_FUNCTION(0, 52),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(
+ 53, "GPIO53",
+ MTK_EINT_FUNCTION(0, 53),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(5, "MD_EINT2"),
+ MTK_FUNCTION(6, "C2K_UIM1_HOT_PLUG_IN")
+ ),
+ MTK_PIN(
+ 54, "GPIO54",
+ MTK_EINT_FUNCTION(0, 54),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(5, "MD_EINT1"),
+ MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN")
+ ),
+ MTK_PIN(
+ 55, "GPIO55",
+ MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SRCLKENAI0"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "CORESONIC_SWD"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(6, "KROW5"),
+ MTK_FUNCTION(7, "DISP_PWM")
+ ),
+ MTK_PIN(
+ 56, "GPIO56",
+ MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SRCLKENA1")
+ ),
+ MTK_PIN(
+ 57, "GPIO57",
+ MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "DPI_HSYNC0"),
+ MTK_FUNCTION(3, "UTXD2"),
+ MTK_FUNCTION(4, "MD_URXD"),
+ MTK_FUNCTION(5, "SRCLKENAI1"),
+ MTK_FUNCTION(6, "KROW4"),
+ MTK_FUNCTION(7, "DBG_MON_A14")
+ ),
+ MTK_PIN(
+ 58, "GPIO58",
+ MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "DPI_VSYNC0"),
+ MTK_FUNCTION(3, "URXD2"),
+ MTK_FUNCTION(4, "MD_UTXD"),
+ MTK_FUNCTION(5, "TDD_TXD"),
+ MTK_FUNCTION(6, "KROW5"),
+ MTK_FUNCTION(7, "DBG_MON_A15")
+ ),
+ MTK_PIN(
+ 59, "GPIO59",
+ MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION(2, "DPI_CK0"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, "UCTS2"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "KROW6"),
+ MTK_FUNCTION(7, "DBG_MON_A16")
+ ),
+ MTK_PIN(
+ 60, "GPIO60",
+ MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION(2, "DPI_DE0"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, "URTS2"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "KROW7"),
+ MTK_FUNCTION(7, "DBG_MON_A17")
+ ),
+ MTK_PIN(
+ 61, "GPIO61",
+ MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "PCM1_CLK"),
+ MTK_FUNCTION(2, "DPI_D0"),
+ MTK_FUNCTION(3, "I2S0_BCK"),
+ MTK_FUNCTION(4, "KROW4"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "IRTX_OUT"),
+ MTK_FUNCTION(7, "DBG_MON_A18")
+ ),
+ MTK_PIN(
+ 62, "GPIO62",
+ MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "PCM1_SYNC"),
+ MTK_FUNCTION(2, "DPI_D1"),
+ MTK_FUNCTION(3, "I2S0_LRCK"),
+ MTK_FUNCTION(4, "KCOL7"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, "CMFLASH"),
+ MTK_FUNCTION(7, "DBG_MON_A19")
+ ),
+ MTK_PIN(
+ 63, "GPIO63",
+ MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "PCM1_DI"),
+ MTK_FUNCTION(2, "DPI_D2"),
+ MTK_FUNCTION(3, "I2S0_DI"),
+ MTK_FUNCTION(4, "PCM1_DO0"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(6, "KROW3"),
+ MTK_FUNCTION(7, "DBG_MON_A20")
+ ),
+ MTK_PIN(
+ 64, "GPIO64",
+ MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "PCM1_DO0"),
+ MTK_FUNCTION(2, "DPI_D3"),
+ MTK_FUNCTION(3, "I2S0_MCK"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "SRCLKENAI2"),
+ MTK_FUNCTION(6, "KCOL5"),
+ MTK_FUNCTION(7, "DBG_MON_A21")
+ ),
+ MTK_PIN(
+ 65, "GPIO65",
+ MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "SPI_CSA"),
+ MTK_FUNCTION(2, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(3, "I2S3_MCK"),
+ MTK_FUNCTION(4, "KROW2"),
+ MTK_FUNCTION(5, "GPS_FRAME_SYNC"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "DBG_MON_A22")
+ ),
+ MTK_PIN(
+ 66, "GPIO66",
+ MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "SPI_CKA"),
+ MTK_FUNCTION(2, "USB_DRVVBUS"),
+ MTK_FUNCTION(3, "I2S3_BCK"),
+ MTK_FUNCTION(4, "KCOL2"),
+ MTK_FUNCTION(6, "PTA_TXD"),
+ MTK_FUNCTION(7, "DBG_MON_A23")
+ ),
+ MTK_PIN(
+ 67, "GPIO67",
+ MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "SPI_MIA"),
+ MTK_FUNCTION(2, "SPI_MOA"),
+ MTK_FUNCTION(3, "I2S3_DO"),
+ MTK_FUNCTION(4, "PTA_RXD"),
+ MTK_FUNCTION(5, "IDDIG"),
+ MTK_FUNCTION(6, "UCTS1"),
+ MTK_FUNCTION(7, "DBG_MON_A24")
+ ),
+ MTK_PIN(
+ 68, "GPIO68",
+ MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "SPI_MOA"),
+ MTK_FUNCTION(2, "SPI_MIA"),
+ MTK_FUNCTION(3, "I2S3_LRCK"),
+ MTK_FUNCTION(4, "PTA_TXD"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "URTS1"),
+ MTK_FUNCTION(7, "DBG_MON_A25")
+ ),
+ MTK_PIN(
+ 69, "GPIO69",
+ MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "DM_JTINTP")
+ ),
+ MTK_PIN(
+ 70, "GPIO70",
+ MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION(2, "CONN_MCU_TMS"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TMS"),
+ MTK_FUNCTION(4, "TDD_TMS"),
+ MTK_FUNCTION(5, "CORESONIC_SWD"),
+ MTK_FUNCTION(6, "DM_OTMS"),
+ MTK_FUNCTION(7, "DFD_TMS")
+ ),
+ MTK_PIN(
+ 71, "GPIO71",
+ MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION(2, "CONN_MCU_TCK[1]"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TCK"),
+ MTK_FUNCTION(4, "TDD_TCK"),
+ MTK_FUNCTION(5, "CORESONIC_SWCK"),
+ MTK_FUNCTION(6, "DM_OTCK"),
+ MTK_FUNCTION(7, "DFD_TCK_XI")
+ ),
+ MTK_PIN(
+ 72, "GPIO72",
+ MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION(2, "CONN_MCU_TDI"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TDI"),
+ MTK_FUNCTION(4, "TDD_TDI"),
+ MTK_FUNCTION(6, "DM_OTDI"),
+ MTK_FUNCTION(7, "DFD_TDI")
+ ),
+ MTK_PIN(
+ 73, "GPIO73",
+ MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION(2, "CONN_MCU_TDO"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TDO"),
+ MTK_FUNCTION(4, "TDD_TDO"),
+ MTK_FUNCTION(6, "DM_OTDO"),
+ MTK_FUNCTION(7, "DFD_TDO")
+ ),
+ MTK_PIN(
+ 74, "GPIO74",
+ MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(3, "MD_URXD"),
+ MTK_FUNCTION(4, "SDA3"),
+ MTK_FUNCTION(5, "C2K_UART0_RXD"),
+ MTK_FUNCTION(6, "LTE_URXD"),
+ MTK_FUNCTION(7, "AUXIF_ST")
+ ),
+ MTK_PIN(
+ 75, "GPIO75",
+ MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(3, "MD_UTXD"),
+ MTK_FUNCTION(4, "TDD_TXD"),
+ MTK_FUNCTION(5, "C2K_UART0_TXD"),
+ MTK_FUNCTION(6, "LTE_UTXD")
+ ),
+ MTK_PIN(
+ 76, "GPIO76",
+ MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "MD_URXD"),
+ MTK_FUNCTION(4, "SCL3"),
+ MTK_FUNCTION(5, "LTE_URXD"),
+ MTK_FUNCTION(6, "C2K_UART0_RXD"),
+ MTK_FUNCTION(7, "AUXIF_CLK")
+ ),
+ MTK_PIN(
+ 77, "GPIO77",
+ MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "MD_UTXD"),
+ MTK_FUNCTION(4, "TDD_TXD"),
+ MTK_FUNCTION(5, "LTE_UTXD"),
+ MTK_FUNCTION(6, "C2K_UART0_TXD")
+ ),
+ MTK_PIN(
+ 78, "GPIO78",
+ MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "PCM1_DI"),
+ MTK_FUNCTION(3, "I2S3_DO"),
+ MTK_FUNCTION(4, "I2S1_DO"),
+ MTK_FUNCTION(5, "PWM0"),
+ MTK_FUNCTION(6, "I2S2_DI"),
+ MTK_FUNCTION(7, "DBG_MON_A26")
+ ),
+ MTK_PIN(
+ 79, "GPIO79",
+ MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "PCM1_SYNC"),
+ MTK_FUNCTION(3, "I2S3_LRCK"),
+ MTK_FUNCTION(4, "I2S1_LRCK"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "I2S2_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_A27")
+ ),
+ MTK_PIN(
+ 80, "GPIO80",
+ MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "PCM1_CLK[1]"),
+ MTK_FUNCTION(3, "I2S3_BCK"),
+ MTK_FUNCTION(4, "I2S1_BCK"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "I2S2_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A28")
+ ),
+ MTK_PIN(
+ 81, "GPIO81",
+ MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "KROW0"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(4, "CORESONIC_SWCK"),
+ MTK_FUNCTION(5, "C2K_TCK"),
+ MTK_FUNCTION(7, "C2K_DM_EINT1")
+ ),
+ MTK_PIN(
+ 82, "GPIO82",
+ MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "KROW1"),
+ MTK_FUNCTION(3, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(4, "CORESONIC_SWD"),
+ MTK_FUNCTION(5, "C2K_NTRST"),
+ MTK_FUNCTION(6, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "C2K_DM_EINT2")
+ ),
+ MTK_PIN(
+ 83, "GPIO83",
+ MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "KROW2"),
+ MTK_FUNCTION(2, "USB_DRVVBUS"),
+ MTK_FUNCTION(5, "C2K_TDI"),
+ MTK_FUNCTION(7, "C2K_DM_EINT3")
+ ),
+ MTK_PIN(
+ 84, "GPIO84",
+ MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "KCOL0"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "C2K_TDO"),
+ MTK_FUNCTION(6, "AUXIF_CLK")
+ ),
+ MTK_PIN(
+ 85, "GPIO85",
+ MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "KCOL1"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "C2K_TMS"),
+ MTK_FUNCTION(6, "AUXIF_ST"),
+ MTK_FUNCTION(7, "DBG_MON_A31")
+ ),
+ MTK_PIN(
+ 86, "GPIO86",
+ MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "KCOL2"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(5, "C2K_RTCK"),
+ MTK_FUNCTION(7, "DBG_MON_A32")
+ ),
+ MTK_PIN(
+ 87, "GPIO87",
+ MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "BPI_BUS5"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS5"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS5"),
+ MTK_FUNCTION(7, "DBG_MON_B0")
+ ),
+ MTK_PIN(
+ 88, "GPIO88",
+ MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "BPI_BUS6"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS6"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS6"),
+ MTK_FUNCTION(7, "DBG_MON_B1")
+ ),
+ MTK_PIN(
+ 89, "GPIO89",
+ MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "BPI_BUS7"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS7"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS7"),
+ MTK_FUNCTION(7, "DBG_MON_B2")
+ ),
+ MTK_PIN(
+ 90, "GPIO90",
+ MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "BPI_BUS8"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS8"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS8"),
+ MTK_FUNCTION(7, "DBG_MON_B3")
+ ),
+ MTK_PIN(
+ 91, "GPIO91",
+ MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "BPI_BUS9"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS9"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS9"),
+ MTK_FUNCTION(7, "DBG_MON_B4")
+ ),
+ MTK_PIN(
+ 92, "GPIO92",
+ MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "BPI_BUS10"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS10"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS10"),
+ MTK_FUNCTION(7, "DBG_MON_B5")
+ ),
+ MTK_PIN(
+ 93, "GPIO93",
+ MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "BPI_BUS11"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS11"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS11"),
+ MTK_FUNCTION(7, "DBG_MON_B6")
+ ),
+ MTK_PIN(
+ 94, "GPIO94",
+ MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "BPI_BUS12"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS12"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS12"),
+ MTK_FUNCTION(7, "DBG_MON_B7")
+ ),
+ MTK_PIN(
+ 95, "GPIO95",
+ MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "BPI_BUS13"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS13"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS13"),
+ MTK_FUNCTION(7, "DBG_MON_B8")
+ ),
+ MTK_PIN(
+ 96, "GPIO96",
+ MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "BPI_BUS14"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS14"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS14"),
+ MTK_FUNCTION(7, "DBG_MON_B9")
+ ),
+ MTK_PIN(
+ 97, "GPIO97",
+ MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "BPI_BUS15"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS15"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS15"),
+ MTK_FUNCTION(7, "DBG_MON_B10")
+ ),
+ MTK_PIN(
+ 98, "GPIO98",
+ MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "BPI_BUS16"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS16"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS16"),
+ MTK_FUNCTION(7, "DBG_MON_B11")
+ ),
+ MTK_PIN(
+ 99, "GPIO99",
+ MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "BPI_BUS17"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS17"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS17"),
+ MTK_FUNCTION(7, "DBG_MON_B12")
+ ),
+ MTK_PIN(
+ 100, "GPIO100",
+ MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "BPI_BUS18"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS18"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS18"),
+ MTK_FUNCTION(7, "DBG_MON_B13")
+ ),
+ MTK_PIN(
+ 101, "GPIO101",
+ MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "BPI_BUS19"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS19"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS19"),
+ MTK_FUNCTION(7, "DBG_MON_B14")
+ ),
+ MTK_PIN(
+ 102, "GPIO102",
+ MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "BPI_BUS20"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS20"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS20"),
+ MTK_FUNCTION(7, "DBG_MON_B15")
+ ),
+ MTK_PIN(
+ 103, "GPIO103",
+ MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "C2K_TXBPI"),
+ MTK_FUNCTION(7, "DBG_MON_B16")
+ ),
+ MTK_PIN(
+ 104, "GPIO104",
+ MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "RFIC1_BSI_EN"),
+ MTK_FUNCTION(5, "C2K_RX_BSI_EN"),
+ MTK_FUNCTION(7, "DBG_MON_B17")
+ ),
+ MTK_PIN(
+ 105, "GPIO105",
+ MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "RFIC1_BSI_CK"),
+ MTK_FUNCTION(5, "C2K_RX_BSI_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B18")
+ ),
+ MTK_PIN(
+ 106, "GPIO106",
+ MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "RFIC1_BSI_D0"),
+ MTK_FUNCTION(5, "C2K_RX_BSI_DATA"),
+ MTK_FUNCTION(7, "DBG_MON_B19")
+ ),
+ MTK_PIN(
+ 107, "GPIO107",
+ MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "RFIC1_BSI_D1"),
+ MTK_FUNCTION(5, "C2K_TX_BSI_EN"),
+ MTK_FUNCTION(7, "DBG_MON_B20")
+ ),
+ MTK_PIN(
+ 108, "GPIO108",
+ MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "RFIC1_BSI_D2"),
+ MTK_FUNCTION(5, "C2K_TX_BSI_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B21")
+ ),
+ MTK_PIN(
+ 109, "GPIO109",
+ MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(5, "C2K_TX_BSI_DATA"),
+ MTK_FUNCTION(7, "DBG_MON_B22")
+ ),
+ MTK_PIN(
+ 110, "GPIO110",
+ MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "RFIC0_BSI_EN"),
+ MTK_FUNCTION(4, "SPM_BSI_EN"),
+ MTK_FUNCTION(7, "DBG_MON_B23")
+ ),
+ MTK_PIN(
+ 111, "GPIO111",
+ MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "RFIC0_BSI_CK"),
+ MTK_FUNCTION(4, "SPM_BSI_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B24")
+ ),
+ MTK_PIN(
+ 112, "GPIO112",
+ MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D2"),
+ MTK_FUNCTION(4, "SPM_BSI_D2"),
+ MTK_FUNCTION(7, "DBG_MON_B25")
+ ),
+ MTK_PIN(
+ 113, "GPIO113",
+ MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D1"),
+ MTK_FUNCTION(4, "SPM_BSI_D1"),
+ MTK_FUNCTION(7, "DBG_MON_B26")
+ ),
+ MTK_PIN(
+ 114, "GPIO114",
+ MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D0"),
+ MTK_FUNCTION(4, "SPM_BSI_D0"),
+ MTK_FUNCTION(7, "DBG_MON_B27")
+ ),
+ MTK_PIN(
+ 115, "GPIO115",
+ MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "AUXIN0")
+ ),
+ MTK_PIN(
+ 116, "GPIO116",
+ MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "AUXIN1")
+ ),
+ MTK_PIN(
+ 117, "GPIO117",
+ MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "AUXIN2")
+ ),
+ MTK_PIN(
+ 118, "GPIO118",
+ MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "TXBPI")
+ ),
+ MTK_PIN(
+ 119, "GPIO119",
+ MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "BPI_BUS0"),
+ MTK_FUNCTION(7, "DBG_MON_B28")
+ ),
+ MTK_PIN(
+ 120, "GPIO120",
+ MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "BPI_BUS1"),
+ MTK_FUNCTION(7, "DBG_MON_B29")
+ ),
+ MTK_PIN(
+ 121, "GPIO121",
+ MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "BPI_BUS2"),
+ MTK_FUNCTION(7, "DBG_MON_B30")
+ ),
+ MTK_PIN(
+ 122, "GPIO122",
+ MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "BPI_BUS3"),
+ MTK_FUNCTION(7, "DBG_MON_B31")
+ ),
+ MTK_PIN(
+ 123, "GPIO123",
+ MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "BPI_BUS4"),
+ MTK_FUNCTION(7, "DBG_MON_B32")
+ ),
+ MTK_PIN(
+ 124, "GPIO124",
+ MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "BPI_BUS21"),
+ MTK_FUNCTION(5, "DPI_HSYNC1"),
+ MTK_FUNCTION(6, "KCOL2"),
+ MTK_FUNCTION(7, "TDD_TXD")
+ ),
+ MTK_PIN(
+ 125, "GPIO125",
+ MTK_EINT_FUNCTION(0, 125),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "BPI_BUS22"),
+ MTK_FUNCTION(5, "DPI_VSYNC1"),
+ MTK_FUNCTION(6, "KROW2"),
+ MTK_FUNCTION(7, "MD_URXD")
+ ),
+ MTK_PIN(
+ 126, "GPIO126",
+ MTK_EINT_FUNCTION(0, 126),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "BPI_BUS23"),
+ MTK_FUNCTION(5, "DPI_CK1"),
+ MTK_FUNCTION(6, "I2S2_MCK"),
+ MTK_FUNCTION(7, "MD_UTXD")
+ ),
+ MTK_PIN(
+ 127, "GPIO127",
+ MTK_EINT_FUNCTION(0, 127),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "BPI_BUS24"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "DPI_DE1"),
+ MTK_FUNCTION(6, "SRCLKENAI1"),
+ MTK_FUNCTION(7, "URXD0")
+ ),
+ MTK_PIN(
+ 128, "GPIO128",
+ MTK_EINT_FUNCTION(0, 128),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "BPI_BUS25"),
+ MTK_FUNCTION(3, "GPS_FRAME_SYNC"),
+ MTK_FUNCTION(5, "I2S2_DI"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "UTXD0")
+ ),
+ MTK_PIN(
+ 129, "GPIO129",
+ MTK_EINT_FUNCTION(0, 129),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "BPI_BUS26"),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(5, "I2S2_LRCK"),
+ MTK_FUNCTION(6, "PTA_TXD"),
+ MTK_FUNCTION(7, "LTE_URXD")
+ ),
+ MTK_PIN(
+ 130, "GPIO130",
+ MTK_EINT_FUNCTION(0, 130),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "BPI_BUS27"),
+ MTK_FUNCTION(5, "I2S2_BCK"),
+ MTK_FUNCTION(6, "IRTX_OUT"),
+ MTK_FUNCTION(7, "LTE_UTXD")
+ ),
+ MTK_PIN(
+ 131, "GPIO131",
+ MTK_EINT_FUNCTION(0, 131),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "LTE_PAVM0")
+ ),
+ MTK_PIN(
+ 132, "GPIO132",
+ MTK_EINT_FUNCTION(0, 132),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "LTE_PAVM1")
+ ),
+ MTK_PIN(
+ 133, "GPIO133",
+ MTK_EINT_FUNCTION(0, 133),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "MIPI1_SCLK")
+ ),
+ MTK_PIN(
+ 134, "GPIO134",
+ MTK_EINT_FUNCTION(0, 134),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "MIPI1_SDATA")
+ ),
+ MTK_PIN(
+ 135, "GPIO135",
+ MTK_EINT_FUNCTION(0, 135),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "MIPI0_SCLK")
+ ),
+ MTK_PIN(
+ 136, "GPIO136",
+ MTK_EINT_FUNCTION(0, 136),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "MIPI0_SDATA")
+ ),
+ MTK_PIN(
+ 137, "GPIO137",
+ MTK_EINT_FUNCTION(0, 137),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ 138, "GPIO138",
+ MTK_EINT_FUNCTION(0, 138),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION(2, "PWRAP_SPIDI")
+ ),
+ MTK_PIN(
+ 139, "GPIO139",
+ MTK_EINT_FUNCTION(0, 139),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION(2, "PWRAP_SPIDO")
+ ),
+ MTK_PIN(
+ 140, "GPIO140",
+ MTK_EINT_FUNCTION(0, 140),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "DM_JTINTP")
+ ),
+ MTK_PIN(
+ 141, "GPIO141",
+ MTK_EINT_FUNCTION(0, 141),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I")
+ ),
+ MTK_PIN(
+ 142, "GPIO142",
+ MTK_EINT_FUNCTION(0, 142),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+ ),
+ MTK_PIN(
+ 143, "GPIO143",
+ MTK_EINT_FUNCTION(0, 143),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI")
+ ),
+ MTK_PIN(
+ 144, "GPIO144",
+ MTK_EINT_FUNCTION(0, 144),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO"),
+ MTK_FUNCTION(3, "AUD_DAT_MOSI")
+ ),
+ MTK_PIN(
+ 145, "GPIO145",
+ MTK_EINT_FUNCTION(0, 145),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(3, "AUD_DAT_MISO")
+ ),
+ MTK_PIN(
+ 146, "GPIO146",
+ MTK_EINT_FUNCTION(0, 146),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+ MTK_PIN(
+ 147, "GPIO147",
+ MTK_EINT_FUNCTION(0, 147),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "DSI_TE")
+ ),
+ MTK_PIN(
+ 148, "GPIO148",
+ MTK_EINT_FUNCTION(0, 148),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "SRCLKENA")
+ ),
+ MTK_PIN(
+ 149, "GPIO149",
+ MTK_EINT_FUNCTION(0, 149),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ 150, "GPIO150",
+ MTK_EINT_FUNCTION(0, 150),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "TDP0")
+ ),
+ MTK_PIN(
+ 151, "GPIO151",
+ MTK_EINT_FUNCTION(0, 151),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "TDN0")
+ ),
+ MTK_PIN(
+ 152, "GPIO152",
+ MTK_EINT_FUNCTION(0, 152),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "TDP1")
+ ),
+ MTK_PIN(
+ 153, "GPIO153",
+ MTK_EINT_FUNCTION(0, 153),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "TDN1")
+ ),
+ MTK_PIN(
+ 154, "GPIO154",
+ MTK_EINT_FUNCTION(0, 154),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "TCP")
+ ),
+ MTK_PIN(
+ 155, "GPIO155",
+ MTK_EINT_FUNCTION(0, 155),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "TCN")
+ ),
+ MTK_PIN(
+ 156, "GPIO156",
+ MTK_EINT_FUNCTION(0, 156),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "TDP2")
+ ),
+ MTK_PIN(
+ 157, "GPIO157",
+ MTK_EINT_FUNCTION(0, 157),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "TDN2")
+ ),
+ MTK_PIN(
+ 158, "GPIO158",
+ MTK_EINT_FUNCTION(0, 158),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "TDP3")
+ ),
+ MTK_PIN(
+ 159, "GPIO159",
+ MTK_EINT_FUNCTION(0, 159),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "TDN3")
+ ),
+ MTK_PIN(
+ 160, "GPIO160",
+ MTK_EINT_FUNCTION(0, 160),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "MD_SIM2_SCLK"),
+ MTK_FUNCTION(2, "MD_SIM1_SCLK"),
+ MTK_FUNCTION(3, "UIM0_CLK"),
+ MTK_FUNCTION(4, "UIM1_CLK")
+ ),
+ MTK_PIN(
+ 161, "GPIO161",
+ MTK_EINT_FUNCTION(0, 161),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "MD_SIM2_SRST"),
+ MTK_FUNCTION(2, "MD_SIM1_SRST"),
+ MTK_FUNCTION(3, "UIM0_RST"),
+ MTK_FUNCTION(4, "UIM1_RST")
+ ),
+ MTK_PIN(
+ 162, "GPIO162",
+ MTK_EINT_FUNCTION(0, 162),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "MD_SIM2_SDAT"),
+ MTK_FUNCTION(2, "MD_SIM1_SDAT"),
+ MTK_FUNCTION(3, "UIM0_IO"),
+ MTK_FUNCTION(4, "UIM1_IO")
+ ),
+ MTK_PIN(
+ 163, "GPIO163",
+ MTK_EINT_FUNCTION(0, 163),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "MD_SIM1_SCLK"),
+ MTK_FUNCTION(2, "MD_SIM2_SCLK"),
+ MTK_FUNCTION(3, "UIM1_CLK"),
+ MTK_FUNCTION(4, "UIM0_CLK")
+ ),
+ MTK_PIN(
+ 164, "GPIO164",
+ MTK_EINT_FUNCTION(0, 164),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "MD_SIM1_SRST"),
+ MTK_FUNCTION(2, "MD_SIM2_SRST"),
+ MTK_FUNCTION(3, "UIM1_RST"),
+ MTK_FUNCTION(4, "UIM0_RST")
+ ),
+ MTK_PIN(
+ 165, "GPIO165",
+ MTK_EINT_FUNCTION(0, 165),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "MD_SIM1_SDAT"),
+ MTK_FUNCTION(2, "MD_SIM2_SDAT"),
+ MTK_FUNCTION(3, "UIM1_IO"),
+ MTK_FUNCTION(4, "UIM0_IO")
+ ),
+ MTK_PIN(
+ 166, "GPIO166",
+ MTK_EINT_FUNCTION(0, 166),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TMS"),
+ MTK_FUNCTION(3, "C2K_TMS"),
+ MTK_FUNCTION(4, "TDD_TMS"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "JTMS"),
+ MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC")
+ ),
+ MTK_PIN(
+ 167, "GPIO167",
+ MTK_EINT_FUNCTION(0, 167),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TCK"),
+ MTK_FUNCTION(3, "C2K_TCK"),
+ MTK_FUNCTION(4, "TDD_TCK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "JTCK"),
+ MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC")
+ ),
+ MTK_PIN(
+ 168, "GPIO168",
+ MTK_EINT_FUNCTION(0, 168),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TDI"),
+ MTK_FUNCTION(3, "C2K_TDI"),
+ MTK_FUNCTION(4, "TDD_TDI"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "JTDI")
+ ),
+ MTK_PIN(
+ 169, "GPIO169",
+ MTK_EINT_FUNCTION(0, 169),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TDO"),
+ MTK_FUNCTION(3, "C2K_TDO"),
+ MTK_FUNCTION(4, "TDD_TDO"),
+ MTK_FUNCTION(5, "CONN_DSP_JDO"),
+ MTK_FUNCTION(6, "JTDO")
+ ),
+ MTK_PIN(
+ 170, "GPIO170",
+ MTK_EINT_FUNCTION(0, 170),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(3, "C2K_NTRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(6, "DM_JTINTP")
+ ),
+ MTK_PIN(
+ 171, "GPIO171",
+ MTK_EINT_FUNCTION(0, 171),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(3, "C2K_RTCK")
+ ),
+ MTK_PIN(
+ 172, "GPIO172",
+ MTK_EINT_FUNCTION(0, 172),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "MSDC0_CMD")
+ ),
+ MTK_PIN(
+ 173, "GPIO173",
+ MTK_EINT_FUNCTION(0, 173),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "MSDC0_DSL")
+ ),
+ MTK_PIN(
+ 174, "GPIO174",
+ MTK_EINT_FUNCTION(0, 174),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "MSDC0_CLK")
+ ),
+ MTK_PIN(
+ 175, "GPIO175",
+ MTK_EINT_FUNCTION(0, 175),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "MSDC0_DAT0")
+ ),
+ MTK_PIN(
+ 176, "GPIO176",
+ MTK_EINT_FUNCTION(0, 176),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "MSDC0_DAT1")
+ ),
+ MTK_PIN(
+ 177, "GPIO177",
+ MTK_EINT_FUNCTION(0, 177),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "MSDC0_DAT2")
+ ),
+ MTK_PIN(
+ 178, "GPIO178",
+ MTK_EINT_FUNCTION(0, 178),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "MSDC0_DAT3")
+ ),
+ MTK_PIN(
+ 179, "GPIO179",
+ MTK_EINT_FUNCTION(0, 179),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "MSDC0_DAT4")
+ ),
+ MTK_PIN(
+ 180, "GPIO180",
+ MTK_EINT_FUNCTION(0, 180),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "MSDC0_DAT5")
+ ),
+ MTK_PIN(
+ 181, "GPIO181",
+ MTK_EINT_FUNCTION(0, 181),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "MSDC0_DAT6")
+ ),
+ MTK_PIN(
+ 182, "GPIO182",
+ MTK_EINT_FUNCTION(0, 182),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "MSDC0_DAT7")
+ ),
+ MTK_PIN(
+ 183, "GPIO183",
+ MTK_EINT_FUNCTION(0, 183),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "MSDC0_RSTB")
+ ),
+ MTK_PIN(
+ 184, "GPIO184",
+ MTK_EINT_FUNCTION(0, 184),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "F2W_DATA"),
+ MTK_FUNCTION(2, "MRG_CLK"),
+ MTK_FUNCTION(3, "C2K_DM_EINT2"),
+ MTK_FUNCTION(4, "PCM0_CLK")
+ ),
+ MTK_PIN(
+ 185, "GPIO185",
+ MTK_EINT_FUNCTION(0, 185),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "F2W_CK"),
+ MTK_FUNCTION(2, "MRG_DI"),
+ MTK_FUNCTION(3, "C2K_DM_EINT3"),
+ MTK_FUNCTION(4, "PCM0_DI")
+ ),
+ MTK_PIN(
+ 186, "GPIO186",
+ MTK_EINT_FUNCTION(0, 186),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "WB_RSTB"),
+ MTK_FUNCTION(4, "URXD3"),
+ MTK_FUNCTION(5, "UTXD3")
+ ),
+ MTK_PIN(
+ 187, "GPIO187",
+ MTK_EINT_FUNCTION(0, 187),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "WB_SCLK"),
+ MTK_FUNCTION(2, "MRG_DO"),
+ MTK_FUNCTION(4, "PCM0_DO")
+ ),
+ MTK_PIN(
+ 188, "GPIO188",
+ MTK_EINT_FUNCTION(0, 188),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "WB_SDATA"),
+ MTK_FUNCTION(2, "MRG_SYNC"),
+ MTK_FUNCTION(4, "PCM0_SYNC")
+ ),
+ MTK_PIN(
+ 189, "GPIO189",
+ MTK_EINT_FUNCTION(0, 189),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "WB_SEN"),
+ MTK_FUNCTION(4, "UTXD3"),
+ MTK_FUNCTION(5, "URXD3")
+ ),
+ MTK_PIN(
+ 190, "GPIO190",
+ MTK_EINT_FUNCTION(0, 190),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "GPS_RXQN")
+ ),
+ MTK_PIN(
+ 191, "GPIO191",
+ MTK_EINT_FUNCTION(0, 191),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "GPS_RXQP")
+ ),
+ MTK_PIN(
+ 192, "GPIO192",
+ MTK_EINT_FUNCTION(0, 192),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "GPS_RXIN")
+ ),
+ MTK_PIN(
+ 193, "GPIO193",
+ MTK_EINT_FUNCTION(0, 193),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "GPS_RXIP")
+ ),
+ MTK_PIN(
+ 194, "GPIO194",
+ MTK_EINT_FUNCTION(0, 194),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "WB_RXQN")
+ ),
+ MTK_PIN(
+ 195, "GPIO195",
+ MTK_EINT_FUNCTION(0, 195),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "WB_RXQP")
+ ),
+ MTK_PIN(
+ 196, "GPIO196",
+ MTK_EINT_FUNCTION(0, 196),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "WB_RXIN")
+ ),
+ MTK_PIN(
+ 197, "GPIO197",
+ MTK_EINT_FUNCTION(0, 197),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "WB_RXIP")
+ ),
+ MTK_PIN(
+ 198, "GPIO198",
+ MTK_EINT_FUNCTION(0, 198),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION(2, "SDA1"),
+ MTK_FUNCTION(3, "C2K_UART0_RXD"),
+ MTK_FUNCTION(4, "C2K_TMS"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(7, "DM_OTMS")
+ ),
+ MTK_PIN(
+ 199, "GPIO199",
+ MTK_EINT_FUNCTION(0, 199),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION(2, "SCL1"),
+ MTK_FUNCTION(3, "C2K_UART0_TXD"),
+ MTK_FUNCTION(4, "C2K_TCK"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "TDD_TXD"),
+ MTK_FUNCTION(7, "DM_OTCK")
+ ),
+ MTK_PIN(
+ 200, "GPIO200",
+ MTK_EINT_FUNCTION(0, 200),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION(2, "ANT_SEL6"),
+ MTK_FUNCTION(3, "GPS_FRAME_SYNC"),
+ MTK_FUNCTION(4, "C2K_TDI"),
+ MTK_FUNCTION(5, "UTXD0"),
+ MTK_FUNCTION(7, "DM_OTDI")
+ ),
+ MTK_PIN(
+ 201, "GPIO201",
+ MTK_EINT_FUNCTION(0, 201),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "C2K_TDO"),
+ MTK_FUNCTION(5, "URXD0"),
+ MTK_FUNCTION(7, "DM_OTDO")
+ ),
+ MTK_PIN(
+ 202, "GPIO202",
+ MTK_EINT_FUNCTION(0, 202),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(4, "C2K_NTRST"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "KCOL3"),
+ MTK_FUNCTION(7, "DM_JTINTP")
+ ),
+ MTK_PIN(
+ 203, "GPIO203",
+ MTK_EINT_FUNCTION(0, 203),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO203"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "C2K_RTCK"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "KCOL6")
+ ),
+ MTK_PIN(
+ 204, "GPIO204",
+ MTK_EINT_FUNCTION(0, 204),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 205, "GPIO205",
+ MTK_EINT_FUNCTION(0, 205),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 206, "GPIO206",
+ MTK_EINT_FUNCTION(0, 206),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 207, "GPIO207",
+ MTK_EINT_FUNCTION(0, 207),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 208, "GPIO208",
+ MTK_EINT_FUNCTION(0, 208),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 209, "GPIO209",
+ MTK_EINT_FUNCTION(0, 209),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 210, "GPIO210",
+ MTK_EINT_FUNCTION(0, 210),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 211, "GPIO211",
+ MTK_EINT_FUNCTION(0, 211),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 212, "GPIO212",
+ MTK_EINT_FUNCTION(0, 212),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+};
+
+static const struct mtk_pin_desc mtk_pins_mt6735m[] = {
+ MTK_PIN(
+ 0, "GPIO0",
+ MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "DPI_D4"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "KCOL2"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT0")
+ ),
+ MTK_PIN(
+ 1, "GPIO1",
+ MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "DPI_D5"),
+ MTK_FUNCTION(3, "MD_EINT0"),
+ MTK_FUNCTION(4, "TDD_TDO"),
+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT1")
+ ),
+ MTK_PIN(
+ 2, "GPIO2",
+ MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "CLKM0"),
+ MTK_FUNCTION(2, "DPI_D6"),
+ MTK_FUNCTION(3, "MD_EINT0"),
+ MTK_FUNCTION(4, "USB_DRVVBUS"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(6, "PTA_TXD"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT2")
+ ),
+ MTK_PIN(
+ 3, "GPIO3",
+ MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "CLKM1"),
+ MTK_FUNCTION(2, "DPI_D7"),
+ MTK_FUNCTION(3, "SPI_MIB"),
+ MTK_FUNCTION(4, "MD_EINT0"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(7, "C2K_ARM_EINT3")
+ ),
+ MTK_PIN(
+ 4, "GPIO4",
+ MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "CLKM2"),
+ MTK_FUNCTION(2, "DPI_D8"),
+ MTK_FUNCTION(3, "SPI_MOB"),
+ MTK_FUNCTION(4, "TDD_TCK"),
+ MTK_FUNCTION(5, "CONN_MCU_TCK_0"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(7, "C2K_DM_EINT0")
+ ),
+ MTK_PIN(
+ 5, "GPIO5",
+ MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION(2, "DPI_D9"),
+ MTK_FUNCTION(3, "SPI_CSB"),
+ MTK_FUNCTION(4, "TDD_TDI"),
+ MTK_FUNCTION(5, "CONN_MCU_TDI"),
+ MTK_FUNCTION(6, "I2S1_DO"),
+ MTK_FUNCTION(7, "MD_URXD")
+ ),
+ MTK_PIN(
+ 6, "GPIO6",
+ MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION(2, "DPI_D10"),
+ MTK_FUNCTION(3, "SPI_CKB"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "I2S1_LRCK"),
+ MTK_FUNCTION(7, "MD_UTXD")
+ ),
+ MTK_PIN(
+ 7, "GPIO7",
+ MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "UCTS3"),
+ MTK_FUNCTION(2, "DPI_D11"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "TDD_TMS"),
+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
+ MTK_FUNCTION(6, "I2S1_BCK"),
+ MTK_FUNCTION(7, "TDD_TXD")
+ ),
+ MTK_PIN(
+ 8, "GPIO8",
+ MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "URTS3"),
+ MTK_FUNCTION(2, "C2K_UIM0_HOT_PLUG_IN"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "PCM1_DO1"),
+ MTK_FUNCTION(5, "MD_EINT1"),
+ MTK_FUNCTION(6, "KCOL4"),
+ MTK_FUNCTION(7, "UTXD0")
+ ),
+ MTK_PIN(
+ 9, "GPIO9",
+ MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(2, "PCM1_DO0"),
+ MTK_FUNCTION(3, "I2S3_MCK"),
+ MTK_FUNCTION(4, "MD_EINT2"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, "I2S1_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_A29")
+ ),
+ MTK_PIN(
+ 10, "GPIO10",
+ MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "KROW2"),
+ MTK_FUNCTION(4, "MD_EINT0"),
+ MTK_FUNCTION(5, "I2S1_MCK"),
+ MTK_FUNCTION(6, "SDA3"),
+ MTK_FUNCTION(7, "DBG_MON_A30")
+ ),
+ MTK_PIN(
+ 11, "GPIO11",
+ MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "MD_EINT1"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "C2K_UIM0_HOT_PLUG_IN"),
+ MTK_FUNCTION(4, "CLKM0"),
+ MTK_FUNCTION(5, "I2S2_MCK"),
+ MTK_FUNCTION(6, "SCL3"),
+ MTK_FUNCTION(7, "URXD0")
+ ),
+ MTK_PIN(
+ 12, "GPIO12",
+ MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(3, "KCOL2"),
+ MTK_FUNCTION(4, "MD_EINT2"),
+ MTK_FUNCTION(5, "IRTX_OUT"),
+ MTK_FUNCTION(6, "SRCLKENAI2"),
+ MTK_FUNCTION(7, "PCM1_DO1")
+ ),
+ MTK_PIN(
+ 13, "GPIO13",
+ MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "WB_CTRL0"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT0"),
+ MTK_FUNCTION(7, "DBG_MON_A0")
+ ),
+ MTK_PIN(
+ 14, "GPIO14",
+ MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "WB_CTRL1"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT1"),
+ MTK_FUNCTION(7, "DBG_MON_A1")
+ ),
+ MTK_PIN(
+ 15, "GPIO15",
+ MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "WB_CTRL2"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT2"),
+ MTK_FUNCTION(7, "DBG_MON_A2")
+ ),
+ MTK_PIN(
+ 16, "GPIO16",
+ MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "WB_CTRL3"),
+ MTK_FUNCTION(3, "C2K_ARM_EINT3"),
+ MTK_FUNCTION(7, "DBG_MON_A3")
+ ),
+ MTK_PIN(
+ 17, "GPIO17",
+ MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "WB_CTRL4"),
+ MTK_FUNCTION(3, "C2K_DM_EINT0"),
+ MTK_FUNCTION(4, "WATCHDOG"),
+ MTK_FUNCTION(7, "DBG_MON_A4")
+ ),
+ MTK_PIN(
+ 18, "GPIO18",
+ MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "WB_CTRL5"),
+ MTK_FUNCTION(3, "C2K_DM_EINT1"),
+ MTK_FUNCTION(7, "DBG_MON_A5")
+ ),
+ MTK_PIN(
+ 19, "GPIO19",
+ MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "ANT_SEL0"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "IRDA_TX"),
+ MTK_FUNCTION(4, "C2K_UART0_TXD"),
+ MTK_FUNCTION(5, "GPS_FRAME_SYNC"),
+ MTK_FUNCTION(6, "LTE_UTXD"),
+ MTK_FUNCTION(7, "DBG_MON_A6")
+ ),
+ MTK_PIN(
+ 20, "GPIO20",
+ MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "ANT_SEL1"),
+ MTK_FUNCTION(2, "C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(3, "IRDA_RX"),
+ MTK_FUNCTION(4, "C2K_UART0_RXD"),
+ MTK_FUNCTION(5, "MD_EINT2"),
+ MTK_FUNCTION(6, "LTE_URXD"),
+ MTK_FUNCTION(7, "DBG_MON_A7")
+ ),
+ MTK_PIN(
+ 21, "GPIO21",
+ MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "ANT_SEL2"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "IRDA_PDN"),
+ MTK_FUNCTION(4, "CORESONIC_SWCK"),
+ MTK_FUNCTION(5, "MD_EINT1"),
+ MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN"),
+ MTK_FUNCTION(7, "DBG_MON_A8")
+ ),
+ MTK_PIN(
+ 22, "GPIO22",
+ MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "RDN0")
+ ),
+ MTK_PIN(
+ 23, "GPIO23",
+ MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "RDP0")
+ ),
+ MTK_PIN(
+ 24, "GPIO24",
+ MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "RDN1")
+ ),
+ MTK_PIN(
+ 25, "GPIO25",
+ MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "RDP1")
+ ),
+ MTK_PIN(
+ 26, "GPIO26",
+ MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "RCN")
+ ),
+ MTK_PIN(
+ 27, "GPIO27",
+ MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "RCP")
+ ),
+ MTK_PIN(
+ 28, "GPIO28",
+ MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "RDN2")
+ ),
+ MTK_PIN(
+ 29, "GPIO29",
+ MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "RDP2")
+ ),
+ MTK_PIN(
+ 30, "GPIO30",
+ MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "RDN3")
+ ),
+ MTK_PIN(
+ 31, "GPIO31",
+ MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "RDP3")
+ ),
+ MTK_PIN(
+ 32, "GPIO32",
+ MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "RDN0_A"),
+ MTK_FUNCTION(2, "CMHSYNC"),
+ MTK_FUNCTION(3, "CMCSD0")
+ ),
+ MTK_PIN(
+ 33, "GPIO33",
+ MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "RDP0_A"),
+ MTK_FUNCTION(2, "CMVSYNC"),
+ MTK_FUNCTION(3, "CMCSD1")
+ ),
+ MTK_PIN(
+ 34, "GPIO34",
+ MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "RDN1_A"),
+ MTK_FUNCTION(2, "CMDAT9"),
+ MTK_FUNCTION(3, "CMCSD2")
+ ),
+ MTK_PIN(
+ 35, "GPIO35",
+ MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "RDP1_A"),
+ MTK_FUNCTION(2, "CMDAT8"),
+ MTK_FUNCTION(3, "CMCSD3")
+ ),
+ MTK_PIN(
+ 36, "GPIO36",
+ MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "RCN_A"),
+ MTK_FUNCTION(2, "CMDAT7")
+ ),
+ MTK_PIN(
+ 37, "GPIO37",
+ MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "RCP_A"),
+ MTK_FUNCTION(2, "CMDAT6")
+ ),
+ MTK_PIN(
+ 38, "GPIO38",
+ MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "RDN2_A"),
+ MTK_FUNCTION(2, "CMDAT5")
+ ),
+ MTK_PIN(
+ 39, "GPIO39",
+ MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "RDP2_A"),
+ MTK_FUNCTION(2, "CMDAT4")
+ ),
+ MTK_PIN(
+ 40, "GPIO40",
+ MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "RDN3_A"),
+ MTK_FUNCTION(2, "CMDAT3")
+ ),
+ MTK_PIN(
+ 41, "GPIO41",
+ MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "RDP3_A"),
+ MTK_FUNCTION(2, "CMDAT2")
+ ),
+ MTK_PIN(
+ 42, "GPIO42",
+ MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "CMDAT0"),
+ MTK_FUNCTION(2, "CMCSD0"),
+ MTK_FUNCTION(3, "CMMCLK1"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "CLKM5"),
+ MTK_FUNCTION(7, "DBG_MON_A9")
+ ),
+ MTK_PIN(
+ 43, "GPIO43",
+ MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "CMDAT1"),
+ MTK_FUNCTION(2, "CMCSD1"),
+ MTK_FUNCTION(3, "CMFLASH"),
+ MTK_FUNCTION(4, "MD_EINT0"),
+ MTK_FUNCTION(5, "CMMCLK1"),
+ MTK_FUNCTION(6, "CLKM4"),
+ MTK_FUNCTION(7, "DBG_MON_A10")
+ ),
+ MTK_PIN(
+ 44, "GPIO44",
+ MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "CMPCLK"),
+ MTK_FUNCTION(2, "CMCSK"),
+ MTK_FUNCTION(3, "CMCSD2"),
+ MTK_FUNCTION(4, "KCOL3"),
+ MTK_FUNCTION(5, "SRCLKENAI2"),
+ MTK_FUNCTION(6, "PWM0"),
+ MTK_FUNCTION(7, "DBG_MON_A11")
+ ),
+ MTK_PIN(
+ 45, "GPIO45",
+ MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "CMMCLK0"),
+ MTK_FUNCTION(7, "DBG_MON_A12")
+ ),
+ MTK_PIN(
+ 46, "GPIO46",
+ MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "CMMCLK1"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "DM_JTINTP"),
+ MTK_FUNCTION(6, "KCOL6"),
+ MTK_FUNCTION(7, "DBG_MON_A13")
+ ),
+ MTK_PIN(
+ 47, "GPIO47",
+ MTK_EINT_FUNCTION(0, 47),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ 48, "GPIO48",
+ MTK_EINT_FUNCTION(0, 48),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ 49, "GPIO49",
+ MTK_EINT_FUNCTION(0, 49),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(
+ 50, "GPIO50",
+ MTK_EINT_FUNCTION(0, 50),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(
+ 51, "GPIO51",
+ MTK_EINT_FUNCTION(0, 51),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(
+ 52, "GPIO52",
+ MTK_EINT_FUNCTION(0, 52),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(
+ 53, "GPIO53",
+ MTK_EINT_FUNCTION(0, 53),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(5, "MD_EINT2"),
+ MTK_FUNCTION(6, "C2K_UIM1_HOT_PLUG_IN")
+ ),
+ MTK_PIN(
+ 54, "GPIO54",
+ MTK_EINT_FUNCTION(0, 54),
+ DRV_FIXED,
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(5, "MD_EINT1"),
+ MTK_FUNCTION(6, "C2K_UIM0_HOT_PLUG_IN")
+ ),
+ MTK_PIN(
+ 55, "GPIO55",
+ MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SRCLKENAI0"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "CORESONIC_SWD"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(6, "KROW5"),
+ MTK_FUNCTION(7, "DISP_PWM")
+ ),
+ MTK_PIN(
+ 56, "GPIO56",
+ MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SRCLKENA1")
+ ),
+ MTK_PIN(
+ 57, "GPIO57",
+ MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "DPI_HSYNC0"),
+ MTK_FUNCTION(3, "UTXD2"),
+ MTK_FUNCTION(4, "MD_URXD"),
+ MTK_FUNCTION(5, "SRCLKENAI1"),
+ MTK_FUNCTION(6, "KROW4"),
+ MTK_FUNCTION(7, "DBG_MON_A14")
+ ),
+ MTK_PIN(
+ 58, "GPIO58",
+ MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "DPI_VSYNC0"),
+ MTK_FUNCTION(3, "URXD2"),
+ MTK_FUNCTION(4, "MD_UTXD"),
+ MTK_FUNCTION(5, "TDD_TXD"),
+ MTK_FUNCTION(6, "KROW5"),
+ MTK_FUNCTION(7, "DBG_MON_A15")
+ ),
+ MTK_PIN(
+ 59, "GPIO59",
+ MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION(2, "DPI_CK0"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, "UCTS2"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "KROW6"),
+ MTK_FUNCTION(7, "DBG_MON_A16")
+ ),
+ MTK_PIN(
+ 60, "GPIO60",
+ MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION(2, "DPI_DE0"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, "URTS2"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "KROW7"),
+ MTK_FUNCTION(7, "DBG_MON_A17")
+ ),
+ MTK_PIN(
+ 61, "GPIO61",
+ MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "PCM1_CLK"),
+ MTK_FUNCTION(2, "DPI_D0"),
+ MTK_FUNCTION(3, "I2S0_BCK"),
+ MTK_FUNCTION(4, "KROW4"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "IRTX_OUT"),
+ MTK_FUNCTION(7, "DBG_MON_A18")
+ ),
+ MTK_PIN(
+ 62, "GPIO62",
+ MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "PCM1_SYNC"),
+ MTK_FUNCTION(2, "DPI_D1"),
+ MTK_FUNCTION(3, "I2S0_LRCK"),
+ MTK_FUNCTION(4, "KCOL7"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, "CMFLASH"),
+ MTK_FUNCTION(7, "DBG_MON_A19")
+ ),
+ MTK_PIN(
+ 63, "GPIO63",
+ MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "PCM1_DI"),
+ MTK_FUNCTION(2, "DPI_D2"),
+ MTK_FUNCTION(3, "I2S0_DI"),
+ MTK_FUNCTION(4, "PCM1_DO0"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(6, "KROW3"),
+ MTK_FUNCTION(7, "DBG_MON_A20")
+ ),
+ MTK_PIN(
+ 64, "GPIO64",
+ MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "PCM1_DO0"),
+ MTK_FUNCTION(2, "DPI_D3"),
+ MTK_FUNCTION(3, "I2S0_MCK"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "SRCLKENAI2"),
+ MTK_FUNCTION(6, "KCOL5"),
+ MTK_FUNCTION(7, "DBG_MON_A21")
+ ),
+ MTK_PIN(
+ 65, "GPIO65",
+ MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "SPI_CSA"),
+ MTK_FUNCTION(2, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(3, "I2S3_MCK"),
+ MTK_FUNCTION(4, "KROW2"),
+ MTK_FUNCTION(5, "GPS_FRAME_SYNC"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "DBG_MON_A22")
+ ),
+ MTK_PIN(
+ 66, "GPIO66",
+ MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "SPI_CKA"),
+ MTK_FUNCTION(2, "USB_DRVVBUS"),
+ MTK_FUNCTION(3, "I2S3_BCK"),
+ MTK_FUNCTION(4, "KCOL2"),
+ MTK_FUNCTION(6, "PTA_TXD"),
+ MTK_FUNCTION(7, "DBG_MON_A23")
+ ),
+ MTK_PIN(
+ 67, "GPIO67",
+ MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "SPI_MIA"),
+ MTK_FUNCTION(2, "SPI_MOA"),
+ MTK_FUNCTION(3, "I2S3_DO"),
+ MTK_FUNCTION(4, "PTA_RXD"),
+ MTK_FUNCTION(5, "IDDIG"),
+ MTK_FUNCTION(6, "UCTS1"),
+ MTK_FUNCTION(7, "DBG_MON_A24")
+ ),
+ MTK_PIN(
+ 68, "GPIO68",
+ MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "SPI_MOA"),
+ MTK_FUNCTION(2, "SPI_MIA"),
+ MTK_FUNCTION(3, "I2S3_LRCK"),
+ MTK_FUNCTION(4, "PTA_TXD"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "URTS1"),
+ MTK_FUNCTION(7, "DBG_MON_A25")
+ ),
+ MTK_PIN(
+ 69, "GPIO69",
+ MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "DM_JTINTP")
+ ),
+ MTK_PIN(
+ 70, "GPIO70",
+ MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION(2, "CONN_MCU_TMS"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TMS"),
+ MTK_FUNCTION(4, "TDD_TMS"),
+ MTK_FUNCTION(5, "CORESONIC_SWD"),
+ MTK_FUNCTION(6, "DM_OTMS"),
+ MTK_FUNCTION(7, "DFD_TMS")
+ ),
+ MTK_PIN(
+ 71, "GPIO71",
+ MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION(2, "CONN_MCU_TCK_1"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TCK"),
+ MTK_FUNCTION(4, "TDD_TCK"),
+ MTK_FUNCTION(5, "CORESONIC_SWCK"),
+ MTK_FUNCTION(6, "DM_OTCK"),
+ MTK_FUNCTION(7, "DFD_TCK_XI")
+ ),
+ MTK_PIN(
+ 72, "GPIO72",
+ MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION(2, "CONN_MCU_TDI"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TDI"),
+ MTK_FUNCTION(4, "TDD_TDI"),
+ MTK_FUNCTION(6, "DM_OTDI"),
+ MTK_FUNCTION(7, "DFD_TDI")
+ ),
+ MTK_PIN(
+ 73, "GPIO73",
+ MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION(2, "CONN_MCU_TDO"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TDO"),
+ MTK_FUNCTION(4, "TDD_TDO"),
+ MTK_FUNCTION(6, "DM_OTDO"),
+ MTK_FUNCTION(7, "DFD_TDO")
+ ),
+ MTK_PIN(
+ 74, "GPIO74",
+ MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(3, "MD_URXD"),
+ MTK_FUNCTION(4, "SDA3"),
+ MTK_FUNCTION(5, "C2K_UART0_RXD"),
+ MTK_FUNCTION(6, "LTE_URXD"),
+ MTK_FUNCTION(7, "AUXIF_ST")
+ ),
+ MTK_PIN(
+ 75, "GPIO75",
+ MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(3, "MD_UTXD"),
+ MTK_FUNCTION(4, "TDD_TXD"),
+ MTK_FUNCTION(5, "C2K_UART0_TXD"),
+ MTK_FUNCTION(6, "LTE_UTXD")
+ ),
+ MTK_PIN(
+ 76, "GPIO76",
+ MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "MD_URXD"),
+ MTK_FUNCTION(4, "SCL3"),
+ MTK_FUNCTION(5, "LTE_URXD"),
+ MTK_FUNCTION(6, "C2K_UART0_RXD"),
+ MTK_FUNCTION(7, "AUXIF_CLK")
+ ),
+ MTK_PIN(
+ 77, "GPIO77",
+ MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "MD_UTXD"),
+ MTK_FUNCTION(4, "TDD_TXD"),
+ MTK_FUNCTION(5, "LTE_UTXD"),
+ MTK_FUNCTION(6, "C2K_UART0_TXD")
+ ),
+ MTK_PIN(
+ 78, "GPIO78",
+ MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "PCM1_DI"),
+ MTK_FUNCTION(3, "I2S3_DO"),
+ MTK_FUNCTION(4, "I2S1_DO"),
+ MTK_FUNCTION(5, "PWM0"),
+ MTK_FUNCTION(6, "I2S2_DI"),
+ MTK_FUNCTION(7, "DBG_MON_A26")
+ ),
+ MTK_PIN(
+ 79, "GPIO79",
+ MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "PCM1_SYNC"),
+ MTK_FUNCTION(3, "I2S3_LRCK"),
+ MTK_FUNCTION(4, "I2S1_LRCK"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, "I2S2_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_A27")
+ ),
+ MTK_PIN(
+ 80, "GPIO80",
+ MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "PCM1_CLK[1]"),
+ MTK_FUNCTION(3, "I2S3_BCK"),
+ MTK_FUNCTION(4, "I2S1_BCK"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "I2S2_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A28")
+ ),
+ MTK_PIN(
+ 81, "GPIO81",
+ MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "KROW0"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(4, "CORESONIC_SWCK"),
+ MTK_FUNCTION(5, "C2K_TCK"),
+ MTK_FUNCTION(7, "C2K_DM_EINT1")
+ ),
+ MTK_PIN(
+ 82, "GPIO82",
+ MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "KROW1"),
+ MTK_FUNCTION(3, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(4, "CORESONIC_SWD"),
+ MTK_FUNCTION(5, "C2K_NTRST"),
+ MTK_FUNCTION(6, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "C2K_DM_EINT2")
+ ),
+ MTK_PIN(
+ 83, "GPIO83",
+ MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "KROW2"),
+ MTK_FUNCTION(2, "USB_DRVVBUS"),
+ MTK_FUNCTION(5, "C2K_TDI"),
+ MTK_FUNCTION(7, "C2K_DM_EINT3")
+ ),
+ MTK_PIN(
+ 84, "GPIO84",
+ MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "KCOL0"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "C2K_TDO"),
+ MTK_FUNCTION(6, "AUXIF_CLK")
+ ),
+ MTK_PIN(
+ 85, "GPIO85",
+ MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "KCOL1"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "C2K_TMS"),
+ MTK_FUNCTION(6, "AUXIF_ST"),
+ MTK_FUNCTION(7, "DBG_MON_A31")
+ ),
+ MTK_PIN(
+ 86, "GPIO86",
+ MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "KCOL2"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(5, "C2K_RTCK"),
+ MTK_FUNCTION(7, "DBG_MON_A32")
+ ),
+ MTK_PIN(
+ 87, "GPIO87",
+ MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "BPI_BUS5"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS5"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS5"),
+ MTK_FUNCTION(7, "DBG_MON_B0")
+ ),
+ MTK_PIN(
+ 88, "GPIO88",
+ MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "BPI_BUS6"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS6"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS6"),
+ MTK_FUNCTION(7, "DBG_MON_B1")
+ ),
+ MTK_PIN(
+ 89, "GPIO89",
+ MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "BPI_BUS7"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS7"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS7"),
+ MTK_FUNCTION(7, "DBG_MON_B2")
+ ),
+ MTK_PIN(
+ 90, "GPIO90",
+ MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "BPI_BUS8"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS8"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS8"),
+ MTK_FUNCTION(7, "DBG_MON_B3")
+ ),
+ MTK_PIN(
+ 91, "GPIO91",
+ MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "BPI_BUS9"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS9"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS9"),
+ MTK_FUNCTION(7, "DBG_MON_B4")
+ ),
+ MTK_PIN(
+ 92, "GPIO92",
+ MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "BPI_BUS10"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS10"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS10"),
+ MTK_FUNCTION(7, "DBG_MON_B5")
+ ),
+ MTK_PIN(
+ 93, "GPIO93",
+ MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "BPI_BUS11"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS11"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS11"),
+ MTK_FUNCTION(7, "DBG_MON_B6")
+ ),
+ MTK_PIN(
+ 94, "GPIO94",
+ MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "BPI_BUS12"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS12"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS12"),
+ MTK_FUNCTION(7, "DBG_MON_B7")
+ ),
+ MTK_PIN(
+ 95, "GPIO95",
+ MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "BPI_BUS13"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS13"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS13"),
+ MTK_FUNCTION(7, "DBG_MON_B8")
+ ),
+ MTK_PIN(
+ 96, "GPIO96",
+ MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "BPI_BUS14"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS14"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS14"),
+ MTK_FUNCTION(7, "DBG_MON_B9")
+ ),
+ MTK_PIN(
+ 97, "GPIO97",
+ MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "BPI_BUS15"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS15"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS15"),
+ MTK_FUNCTION(7, "DBG_MON_B10")
+ ),
+ MTK_PIN(
+ 98, "GPIO98",
+ MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "BPI_BUS16"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS16"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS16"),
+ MTK_FUNCTION(7, "DBG_MON_B11")
+ ),
+ MTK_PIN(
+ 99, "GPIO99",
+ MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "BPI_BUS17"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS17"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS17"),
+ MTK_FUNCTION(7, "DBG_MON_B12")
+ ),
+ MTK_PIN(
+ 100, "GPIO100",
+ MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "BPI_BUS18"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS18"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS18"),
+ MTK_FUNCTION(7, "DBG_MON_B13")
+ ),
+ MTK_PIN(
+ 101, "GPIO101",
+ MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "BPI_BUS19"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS19"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS19"),
+ MTK_FUNCTION(7, "DBG_MON_B14")
+ ),
+ MTK_PIN(
+ 102, "GPIO102",
+ MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "BPI_BUS20"),
+ MTK_FUNCTION(2, "LTE_C2K_BPI_BUS20"),
+ MTK_FUNCTION(5, "C2K_BPI_BUS20"),
+ MTK_FUNCTION(7, "DBG_MON_B15")
+ ),
+ MTK_PIN(
+ 103, "GPIO103",
+ MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "C2K_TXBPI"),
+ MTK_FUNCTION(7, "DBG_MON_B16")
+ ),
+ MTK_PIN(
+ 104, "GPIO104",
+ MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "RFIC1_BSI_EN"),
+ MTK_FUNCTION(5, "C2K_RX_BSI_EN"),
+ MTK_FUNCTION(7, "DBG_MON_B17")
+ ),
+ MTK_PIN(
+ 105, "GPIO105",
+ MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "RFIC1_BSI_CK"),
+ MTK_FUNCTION(5, "C2K_RX_BSI_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B18")
+ ),
+ MTK_PIN(
+ 106, "GPIO106",
+ MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "RFIC1_BSI_D0"),
+ MTK_FUNCTION(5, "C2K_RX_BSI_DATA"),
+ MTK_FUNCTION(7, "DBG_MON_B19")
+ ),
+ MTK_PIN(
+ 107, "GPIO107",
+ MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "RFIC1_BSI_D1"),
+ MTK_FUNCTION(5, "C2K_TX_BSI_EN"),
+ MTK_FUNCTION(7, "DBG_MON_B20")
+ ),
+ MTK_PIN(
+ 108, "GPIO108",
+ MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "RFIC1_BSI_D2"),
+ MTK_FUNCTION(5, "C2K_TX_BSI_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B21")
+ ),
+ MTK_PIN(
+ 109, "GPIO109",
+ MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(5, "C2K_TX_BSI_DATA"),
+ MTK_FUNCTION(7, "DBG_MON_B22")
+ ),
+ MTK_PIN(
+ 110, "GPIO110",
+ MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "RFIC0_BSI_EN"),
+ MTK_FUNCTION(4, "SPM_BSI_EN"),
+ MTK_FUNCTION(7, "DBG_MON_B23")
+ ),
+ MTK_PIN(
+ 111, "GPIO111",
+ MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "RFIC0_BSI_CK"),
+ MTK_FUNCTION(4, "SPM_BSI_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B24")
+ ),
+ MTK_PIN(
+ 112, "GPIO112",
+ MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D2"),
+ MTK_FUNCTION(4, "SPM_BSI_D2"),
+ MTK_FUNCTION(7, "DBG_MON_B25")
+ ),
+ MTK_PIN(
+ 113, "GPIO113",
+ MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D1"),
+ MTK_FUNCTION(4, "SPM_BSI_D1"),
+ MTK_FUNCTION(7, "DBG_MON_B26")
+ ),
+ MTK_PIN(
+ 114, "GPIO114",
+ MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D0"),
+ MTK_FUNCTION(4, "SPM_BSI_D0"),
+ MTK_FUNCTION(7, "DBG_MON_B27")
+ ),
+ MTK_PIN(
+ 115, "GPIO115",
+ MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "AUXIN0")
+ ),
+ MTK_PIN(
+ 116, "GPIO116",
+ MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "AUXIN1")
+ ),
+ MTK_PIN(
+ 117, "GPIO117",
+ MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "AUXIN2")
+ ),
+ MTK_PIN(
+ 118, "GPIO118",
+ MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "TXBPI")
+ ),
+ MTK_PIN(
+ 119, "GPIO119",
+ MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "BPI_BUS0"),
+ MTK_FUNCTION(7, "DBG_MON_B28")
+ ),
+ MTK_PIN(
+ 120, "GPIO120",
+ MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "BPI_BUS1"),
+ MTK_FUNCTION(7, "DBG_MON_B29")
+ ),
+ MTK_PIN(
+ 121, "GPIO121",
+ MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "BPI_BUS2"),
+ MTK_FUNCTION(7, "DBG_MON_B30")
+ ),
+ MTK_PIN(
+ 122, "GPIO122",
+ MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "BPI_BUS3"),
+ MTK_FUNCTION(7, "DBG_MON_B31")
+ ),
+ MTK_PIN(
+ 123, "GPIO123",
+ MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "BPI_BUS4"),
+ MTK_FUNCTION(7, "DBG_MON_B32")
+ ),
+ MTK_PIN(
+ 124, "GPIO124",
+ MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "BPI_BUS21"),
+ MTK_FUNCTION(5, "DPI_HSYNC1"),
+ MTK_FUNCTION(6, "KCOL2"),
+ MTK_FUNCTION(7, "TDD_TXD")
+ ),
+ MTK_PIN(
+ 125, "GPIO125",
+ MTK_EINT_FUNCTION(0, 125),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "BPI_BUS22"),
+ MTK_FUNCTION(5, "DPI_VSYNC1"),
+ MTK_FUNCTION(6, "KROW2"),
+ MTK_FUNCTION(7, "MD_URXD")
+ ),
+ MTK_PIN(
+ 126, "GPIO126",
+ MTK_EINT_FUNCTION(0, 126),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "BPI_BUS23"),
+ MTK_FUNCTION(5, "DPI_CK1"),
+ MTK_FUNCTION(6, "I2S2_MCK"),
+ MTK_FUNCTION(7, "MD_UTXD")
+ ),
+ MTK_PIN(
+ 127, "GPIO127",
+ MTK_EINT_FUNCTION(0, 127),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "BPI_BUS24"),
+ MTK_FUNCTION(3, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "DPI_DE1"),
+ MTK_FUNCTION(6, "SRCLKENAI1"),
+ MTK_FUNCTION(7, "URXD0")
+ ),
+ MTK_PIN(
+ 128, "GPIO128",
+ MTK_EINT_FUNCTION(0, 128),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "BPI_BUS25"),
+ MTK_FUNCTION(3, "GPS_FRAME_SYNC"),
+ MTK_FUNCTION(5, "I2S2_DI"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "UTXD0")
+ ),
+ MTK_PIN(
+ 129, "GPIO129",
+ MTK_EINT_FUNCTION(0, 129),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "BPI_BUS26"),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(5, "I2S2_LRCK"),
+ MTK_FUNCTION(6, "PTA_TXD"),
+ MTK_FUNCTION(7, "LTE_URXD")
+ ),
+ MTK_PIN(
+ 130, "GPIO130",
+ MTK_EINT_FUNCTION(0, 130),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "BPI_BUS27"),
+ MTK_FUNCTION(5, "I2S2_BCK"),
+ MTK_FUNCTION(6, "IRTX_OUT"),
+ MTK_FUNCTION(7, "LTE_UTXD")
+ ),
+ MTK_PIN(
+ 131, "GPIO131",
+ MTK_EINT_FUNCTION(0, 131),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "LTE_PAVM0")
+ ),
+ MTK_PIN(
+ 132, "GPIO132",
+ MTK_EINT_FUNCTION(0, 132),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "LTE_PAVM1")
+ ),
+ MTK_PIN(
+ 133, "GPIO133",
+ MTK_EINT_FUNCTION(0, 133),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "MIPI1_SCLK")
+ ),
+ MTK_PIN(
+ 134, "GPIO134",
+ MTK_EINT_FUNCTION(0, 134),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "MIPI1_SDATA")
+ ),
+ MTK_PIN(
+ 135, "GPIO135",
+ MTK_EINT_FUNCTION(0, 135),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "MIPI0_SCLK")
+ ),
+ MTK_PIN(
+ 136, "GPIO136",
+ MTK_EINT_FUNCTION(0, 136),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "MIPI0_SDATA")
+ ),
+ MTK_PIN(
+ 137, "GPIO137",
+ MTK_EINT_FUNCTION(0, 137),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ 138, "GPIO138",
+ MTK_EINT_FUNCTION(0, 138),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION(2, "PWRAP_SPIDI")
+ ),
+ MTK_PIN(
+ 139, "GPIO139",
+ MTK_EINT_FUNCTION(0, 139),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION(2, "PWRAP_SPIDO")
+ ),
+ MTK_PIN(
+ 140, "GPIO140",
+ MTK_EINT_FUNCTION(0, 140),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(3, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "DM_JTINTP")
+ ),
+ MTK_PIN(
+ 141, "GPIO141",
+ MTK_EINT_FUNCTION(0, 141),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I")
+ ),
+ MTK_PIN(
+ 142, "GPIO142",
+ MTK_EINT_FUNCTION(0, 142),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+ ),
+ MTK_PIN(
+ 143, "GPIO143",
+ MTK_EINT_FUNCTION(0, 143),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI")
+ ),
+ MTK_PIN(
+ 144, "GPIO144",
+ MTK_EINT_FUNCTION(0, 144),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO"),
+ MTK_FUNCTION(3, "AUD_DAT_MOSI")
+ ),
+ MTK_PIN(
+ 145, "GPIO145",
+ MTK_EINT_FUNCTION(0, 145),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(3, "AUD_DAT_MISO")
+ ),
+ MTK_PIN(
+ 146, "GPIO146",
+ MTK_EINT_FUNCTION(0, 146),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+ MTK_PIN(
+ 147, "GPIO147",
+ MTK_EINT_FUNCTION(0, 147),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "DSI_TE")
+ ),
+ MTK_PIN(
+ 148, "GPIO148",
+ MTK_EINT_FUNCTION(0, 148),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "SRCLKENA")
+ ),
+ MTK_PIN(
+ 149, "GPIO149",
+ MTK_EINT_FUNCTION(0, 149),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ 150, "GPIO150",
+ MTK_EINT_FUNCTION(0, 150),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "TDP0")
+ ),
+ MTK_PIN(
+ 151, "GPIO151",
+ MTK_EINT_FUNCTION(0, 151),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "TDN0")
+ ),
+ MTK_PIN(
+ 152, "GPIO152",
+ MTK_EINT_FUNCTION(0, 152),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "TDP1")
+ ),
+ MTK_PIN(
+ 153, "GPIO153",
+ MTK_EINT_FUNCTION(0, 153),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "TDN1")
+ ),
+ MTK_PIN(
+ 154, "GPIO154",
+ MTK_EINT_FUNCTION(0, 154),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "TCP")
+ ),
+ MTK_PIN(
+ 155, "GPIO155",
+ MTK_EINT_FUNCTION(0, 155),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "TCN")
+ ),
+ MTK_PIN(
+ 156, "GPIO156",
+ MTK_EINT_FUNCTION(0, 156),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "TDP2")
+ ),
+ MTK_PIN(
+ 157, "GPIO157",
+ MTK_EINT_FUNCTION(0, 157),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "TDN2")
+ ),
+ MTK_PIN(
+ 158, "GPIO158",
+ MTK_EINT_FUNCTION(0, 158),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "TDP3")
+ ),
+ MTK_PIN(
+ 159, "GPIO159",
+ MTK_EINT_FUNCTION(0, 159),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "TDN3")
+ ),
+ MTK_PIN(
+ 160, "GPIO160",
+ MTK_EINT_FUNCTION(0, 160),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "MD_SIM2_SCLK"),
+ MTK_FUNCTION(2, "MD_SIM1_SCLK"),
+ MTK_FUNCTION(3, "UIM0_CLK"),
+ MTK_FUNCTION(4, "UIM1_CLK")
+ ),
+ MTK_PIN(
+ 161, "GPIO161",
+ MTK_EINT_FUNCTION(0, 161),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "MD_SIM2_SRST"),
+ MTK_FUNCTION(2, "MD_SIM1_SRST"),
+ MTK_FUNCTION(3, "UIM0_RST"),
+ MTK_FUNCTION(4, "UIM1_RST")
+ ),
+ MTK_PIN(
+ 162, "GPIO162",
+ MTK_EINT_FUNCTION(0, 162),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "MD_SIM2_SDAT"),
+ MTK_FUNCTION(2, "MD_SIM1_SDAT"),
+ MTK_FUNCTION(3, "UIM0_IO"),
+ MTK_FUNCTION(4, "UIM1_IO")
+ ),
+ MTK_PIN(
+ 163, "GPIO163",
+ MTK_EINT_FUNCTION(0, 163),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "MD_SIM1_SCLK"),
+ MTK_FUNCTION(2, "MD_SIM2_SCLK"),
+ MTK_FUNCTION(3, "UIM1_CLK"),
+ MTK_FUNCTION(4, "UIM0_CLK")
+ ),
+ MTK_PIN(
+ 164, "GPIO164",
+ MTK_EINT_FUNCTION(0, 164),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "MD_SIM1_SRST"),
+ MTK_FUNCTION(2, "MD_SIM2_SRST"),
+ MTK_FUNCTION(3, "UIM1_RST"),
+ MTK_FUNCTION(4, "UIM0_RST")
+ ),
+ MTK_PIN(
+ 165, "GPIO165",
+ MTK_EINT_FUNCTION(0, 165),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "MD_SIM1_SDAT"),
+ MTK_FUNCTION(2, "MD_SIM2_SDAT"),
+ MTK_FUNCTION(3, "UIM1_IO"),
+ MTK_FUNCTION(4, "UIM0_IO")
+ ),
+ MTK_PIN(
+ 166, "GPIO166",
+ MTK_EINT_FUNCTION(0, 166),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TMS"),
+ MTK_FUNCTION(3, "C2K_TMS"),
+ MTK_FUNCTION(4, "TDD_TMS"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "JTMS"),
+ MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC")
+ ),
+ MTK_PIN(
+ 167, "GPIO167",
+ MTK_EINT_FUNCTION(0, 167),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TCK"),
+ MTK_FUNCTION(3, "C2K_TCK"),
+ MTK_FUNCTION(4, "TDD_TCK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "JTCK"),
+ MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC")
+ ),
+ MTK_PIN(
+ 168, "GPIO168",
+ MTK_EINT_FUNCTION(0, 168),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TDI"),
+ MTK_FUNCTION(3, "C2K_TDI"),
+ MTK_FUNCTION(4, "TDD_TDI"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "JTDI")
+ ),
+ MTK_PIN(
+ 169, "GPIO169",
+ MTK_EINT_FUNCTION(0, 169),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TDO"),
+ MTK_FUNCTION(3, "C2K_TDO"),
+ MTK_FUNCTION(4, "TDD_TDO"),
+ MTK_FUNCTION(5, "CONN_DSP_JDO"),
+ MTK_FUNCTION(6, "JTDO")
+ ),
+ MTK_PIN(
+ 170, "GPIO170",
+ MTK_EINT_FUNCTION(0, 170),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "LTE_MD32_JTAG_TRST"),
+ MTK_FUNCTION(3, "C2K_NTRST"),
+ MTK_FUNCTION(4, "TDD_TRSTN"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(6, "DM_JTINTP")
+ ),
+ MTK_PIN(
+ 171, "GPIO171",
+ MTK_EINT_FUNCTION(0, 171),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(3, "C2K_RTCK")
+ ),
+ MTK_PIN(
+ 172, "GPIO172",
+ MTK_EINT_FUNCTION(0, 172),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "MSDC0_CMD")
+ ),
+ MTK_PIN(
+ 173, "GPIO173",
+ MTK_EINT_FUNCTION(0, 173),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "MSDC0_DSL")
+ ),
+ MTK_PIN(
+ 174, "GPIO174",
+ MTK_EINT_FUNCTION(0, 174),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "MSDC0_CLK")
+ ),
+ MTK_PIN(
+ 175, "GPIO175",
+ MTK_EINT_FUNCTION(0, 175),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "MSDC0_DAT0")
+ ),
+ MTK_PIN(
+ 176, "GPIO176",
+ MTK_EINT_FUNCTION(0, 176),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "MSDC0_DAT1")
+ ),
+ MTK_PIN(
+ 177, "GPIO177",
+ MTK_EINT_FUNCTION(0, 177),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "MSDC0_DAT2")
+ ),
+ MTK_PIN(
+ 178, "GPIO178",
+ MTK_EINT_FUNCTION(0, 178),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "MSDC0_DAT3")
+ ),
+ MTK_PIN(
+ 179, "GPIO179",
+ MTK_EINT_FUNCTION(0, 179),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "MSDC0_DAT4")
+ ),
+ MTK_PIN(
+ 180, "GPIO180",
+ MTK_EINT_FUNCTION(0, 180),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "MSDC0_DAT5")
+ ),
+ MTK_PIN(
+ 181, "GPIO181",
+ MTK_EINT_FUNCTION(0, 181),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "MSDC0_DAT6")
+ ),
+ MTK_PIN(
+ 182, "GPIO182",
+ MTK_EINT_FUNCTION(0, 182),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "MSDC0_DAT7")
+ ),
+ MTK_PIN(
+ 183, "GPIO183",
+ MTK_EINT_FUNCTION(0, 183),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "MSDC0_RSTB")
+ ),
+ MTK_PIN(
+ 184, "GPIO184",
+ MTK_EINT_FUNCTION(0, 184),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "F2W_DATA"),
+ MTK_FUNCTION(2, "MRG_CLK"),
+ MTK_FUNCTION(3, "C2K_DM_EINT2"),
+ MTK_FUNCTION(4, "PCM0_CLK")
+ ),
+ MTK_PIN(
+ 185, "GPIO185",
+ MTK_EINT_FUNCTION(0, 185),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "F2W_CK"),
+ MTK_FUNCTION(2, "MRG_DI"),
+ MTK_FUNCTION(3, "C2K_DM_EINT3"),
+ MTK_FUNCTION(4, "PCM0_DI")
+ ),
+ MTK_PIN(
+ 186, "GPIO186",
+ MTK_EINT_FUNCTION(0, 186),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "WB_RSTB"),
+ MTK_FUNCTION(4, "URXD3"),
+ MTK_FUNCTION(5, "UTXD3")
+ ),
+ MTK_PIN(
+ 187, "GPIO187",
+ MTK_EINT_FUNCTION(0, 187),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "WB_SCLK"),
+ MTK_FUNCTION(2, "MRG_DO"),
+ MTK_FUNCTION(4, "PCM0_DO")
+ ),
+ MTK_PIN(
+ 188, "GPIO188",
+ MTK_EINT_FUNCTION(0, 188),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "WB_SDATA"),
+ MTK_FUNCTION(2, "MRG_SYNC"),
+ MTK_FUNCTION(4, "PCM0_SYNC")
+ ),
+ MTK_PIN(
+ 189, "GPIO189",
+ MTK_EINT_FUNCTION(0, 189),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "WB_SEN"),
+ MTK_FUNCTION(4, "UTXD3"),
+ MTK_FUNCTION(5, "URXD3")
+ ),
+ MTK_PIN(
+ 190, "GPIO190",
+ MTK_EINT_FUNCTION(0, 190),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "GPS_RXQN")
+ ),
+ MTK_PIN(
+ 191, "GPIO191",
+ MTK_EINT_FUNCTION(0, 191),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "GPS_RXQP")
+ ),
+ MTK_PIN(
+ 192, "GPIO192",
+ MTK_EINT_FUNCTION(0, 192),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "GPS_RXIN")
+ ),
+ MTK_PIN(
+ 193, "GPIO193",
+ MTK_EINT_FUNCTION(0, 193),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "GPS_RXIP")
+ ),
+ MTK_PIN(
+ 194, "GPIO194",
+ MTK_EINT_FUNCTION(0, 194),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "WB_RXQN")
+ ),
+ MTK_PIN(
+ 195, "GPIO195",
+ MTK_EINT_FUNCTION(0, 195),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "WB_RXQP")
+ ),
+ MTK_PIN(
+ 196, "GPIO196",
+ MTK_EINT_FUNCTION(0, 196),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "WB_RXIN")
+ ),
+ MTK_PIN(
+ 197, "GPIO197",
+ MTK_EINT_FUNCTION(0, 197),
+ DRV_GRP2,
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "WB_RXIP")
+ ),
+ MTK_PIN(
+ 198, "GPIO198",
+ MTK_EINT_FUNCTION(0, 198),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 199, "GPIO199",
+ MTK_EINT_FUNCTION(0, 199),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 200, "GPIO200",
+ MTK_EINT_FUNCTION(0, 200),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 201, "GPIO201",
+ MTK_EINT_FUNCTION(0, 201),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 202, "GPIO202",
+ MTK_EINT_FUNCTION(0, 202),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 203, "GPIO203",
+ MTK_EINT_FUNCTION(0, 203),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 204, "GPIO204",
+ MTK_EINT_FUNCTION(0, 204),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 205, "GPIO205",
+ MTK_EINT_FUNCTION(0, 205),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 206, "GPIO206",
+ MTK_EINT_FUNCTION(0, 206),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 207, "GPIO207",
+ MTK_EINT_FUNCTION(0, 207),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 208, "GPIO208",
+ MTK_EINT_FUNCTION(0, 208),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 209, "GPIO209",
+ MTK_EINT_FUNCTION(0, 209),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 210, "GPIO210",
+ MTK_EINT_FUNCTION(0, 210),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 211, "GPIO211",
+ MTK_EINT_FUNCTION(0, 211),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 212, "GPIO212",
+ MTK_EINT_FUNCTION(0, 212),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+};
+
+#endif
--
2.54.0
^ permalink raw reply related
* [PATCH v8 5/6] dt-bindings: pinctrl: mediatek: Add bindings for MT6735 pin controller
From: Yassine Oudjana @ 2026-05-30 14:57 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng
Cc: Yassine Oudjana, linux-mediatek, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260530145800.1029920-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Add DT bindings for the MT6735 pin controller, which consist of macros
to be used as values for the pinmux property. Each macro corresponds
to a unique possible pin-function combination.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
MAINTAINERS | 6 +
.../pinctrl/mediatek,mt6735-pinctrl.h | 1148 +++++++++++++++++
2 files changed, 1154 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/mediatek,mt6735-pinctrl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d56bc9434896..315feb314732 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21283,6 +21283,12 @@ F: drivers/pinctrl/mediatek/pinctrl-rt2880.c
F: drivers/pinctrl/mediatek/pinctrl-rt305x.c
F: drivers/pinctrl/mediatek/pinctrl-rt3883.c
+PIN CONTROLLER - MEDIATEK MT6735
+M: Yassine Oudjana <y.oudjana@protonmail.com>
+L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: include/dt-bindings/pinctrl/mediatek,mt6735-pinctrl.h
+
PIN CONTROLLER - MICROCHIP AT91
M: Ludovic Desroches <ludovic.desroches@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/include/dt-bindings/pinctrl/mediatek,mt6735-pinctrl.h b/include/dt-bindings/pinctrl/mediatek,mt6735-pinctrl.h
new file mode 100644
index 000000000000..1134caf9022c
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mediatek,mt6735-pinctrl.h
@@ -0,0 +1,1148 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_MEDIATEK_MT6735_PINFUNC_H__
+#define __DT_BINDINGS_PINCTRL_MEDIATEK_MT6735_PINFUNC_H__
+
+#include "mt65xx.h"
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_IDDIG (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_DPI_D4 (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_CLKM4 (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(0) | 4)
+#define PINMUX_GPIO0__FUNC_PWM3 (MTK_PIN_NO(0) | 5)
+#define PINMUX_GPIO0__FUNC_KCOL2 (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_C2K_ARM_EINT0 (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_PWM2 (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_DPI_D5 (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_MD_EINT0 (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_TDD_TDO (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5)
+#define PINMUX_GPIO1__FUNC_PTA_RXD (MTK_PIN_NO(1) | 6)
+#define PINMUX_GPIO1__FUNC_C2K_ARM_EINT1 (MTK_PIN_NO(1) | 7)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_DPI_D6 (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_MD_EINT0 (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_USB_DRVVBUS (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5)
+#define PINMUX_GPIO2__FUNC_PTA_TXD (MTK_PIN_NO(2) | 6)
+#define PINMUX_GPIO2__FUNC_C2K_ARM_EINT2 (MTK_PIN_NO(2) | 7)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_DPI_D7 (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_SPI_MIB (MTK_PIN_NO(3) | 3)
+#define PINMUX_GPIO3__FUNC_MD_EINT0 (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5)
+#define PINMUX_GPIO3__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(3) | 6)
+#define PINMUX_GPIO3__FUNC_C2K_ARM_EINT3 (MTK_PIN_NO(3) | 7)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_DPI_D8 (MTK_PIN_NO(4) | 2)
+#define PINMUX_GPIO4__FUNC_SPI_MOB (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_TDD_TCK (MTK_PIN_NO(4) | 4)
+#define PINMUX_GPIO4__FUNC_CONN_MCU_TCK_0 (MTK_PIN_NO(4) | 5)
+#define PINMUX_GPIO4__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(4) | 6)
+#define PINMUX_GPIO4__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(4) | 7)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_DPI_D9 (MTK_PIN_NO(5) | 2)
+#define PINMUX_GPIO5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3)
+#define PINMUX_GPIO5__FUNC_TDD_TDI (MTK_PIN_NO(5) | 4)
+#define PINMUX_GPIO5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5)
+#define PINMUX_GPIO5__FUNC_I2S1_DO (MTK_PIN_NO(5) | 6)
+#define PINMUX_GPIO5__FUNC_MD_URXD (MTK_PIN_NO(5) | 7)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_URTS2 (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_DPI_D10 (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_SPI_CKB (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_TDD_TRSTN (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5)
+#define PINMUX_GPIO6__FUNC_I2S1_LRCK (MTK_PIN_NO(6) | 6)
+#define PINMUX_GPIO6__FUNC_MD_UTXD (MTK_PIN_NO(6) | 7)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_UCTS3 (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_DPI_D11 (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_SDA1 (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_TDD_TMS (MTK_PIN_NO(7) | 4)
+#define PINMUX_GPIO7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5)
+#define PINMUX_GPIO7__FUNC_I2S1_BCK (MTK_PIN_NO(7) | 6)
+#define PINMUX_GPIO7__FUNC_TDD_TXD (MTK_PIN_NO(7) | 7)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_URTS3 (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_SCL1 (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_PCM1_DO1 (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_MD_EINT1 (MTK_PIN_NO(8) | 5)
+#define PINMUX_GPIO8__FUNC_KCOL4 (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_UTXD0 (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_PCM1_DO0 (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_I2S3_MCK (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_MD_EINT2 (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_CLKM2 (MTK_PIN_NO(9) | 5)
+#define PINMUX_GPIO9__FUNC_I2S1_MCK (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_DBG_MON_A29 (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_PWM1 (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_CLKM1 (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_KROW2 (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_MD_EINT0 (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_I2S1_MCK (MTK_PIN_NO(10) | 5)
+#define PINMUX_GPIO10__FUNC_SDA3 (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_DBG_MON_A30 (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_MD_EINT1 (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_IRTX_OUT (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_CLKM0 (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_I2S2_MCK (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_SCL3 (MTK_PIN_NO(11) | 6)
+#define PINMUX_GPIO11__FUNC_URXD0 (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_I2S0_MCK (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_KCOL2 (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_MD_EINT2 (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_IRTX_OUT (MTK_PIN_NO(12) | 5)
+#define PINMUX_GPIO12__FUNC_SRCLKENAI2 (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_PCM1_DO1 (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_WB_CTRL0 (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_C2K_ARM_EINT0 (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_DBG_MON_A0 (MTK_PIN_NO(13) | 7)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_WB_CTRL1 (MTK_PIN_NO(14) | 1)
+#define PINMUX_GPIO14__FUNC_C2K_ARM_EINT1 (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_DBG_MON_A1 (MTK_PIN_NO(14) | 7)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_WB_CTRL2 (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_C2K_ARM_EINT2 (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_DBG_MON_A2 (MTK_PIN_NO(15) | 7)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_WB_CTRL3 (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_C2K_ARM_EINT3 (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_DBG_MON_A3 (MTK_PIN_NO(16) | 7)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_WB_CTRL4 (MTK_PIN_NO(17) | 1)
+#define PINMUX_GPIO17__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_WATCHDOG (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_DBG_MON_A4 (MTK_PIN_NO(17) | 7)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_WB_CTRL5 (MTK_PIN_NO(18) | 1)
+#define PINMUX_GPIO18__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(18) | 3)
+#define PINMUX_GPIO18__FUNC_DBG_MON_A5 (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_ANT_SEL0 (MTK_PIN_NO(19) | 1)
+#define PINMUX_GPIO19__FUNC_IRTX_OUT (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_IRDA_TX (MTK_PIN_NO(19) | 3)
+#define PINMUX_GPIO19__FUNC_C2K_UART0_TXD (MTK_PIN_NO(19) | 4)
+#define PINMUX_GPIO19__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_LTE_UTXD (MTK_PIN_NO(19) | 6)
+#define PINMUX_GPIO19__FUNC_DBG_MON_A6 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_ANT_SEL1 (MTK_PIN_NO(20) | 1)
+#define PINMUX_GPIO20__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_IRDA_RX (MTK_PIN_NO(20) | 3)
+#define PINMUX_GPIO20__FUNC_C2K_UART0_RXD (MTK_PIN_NO(20) | 4)
+#define PINMUX_GPIO20__FUNC_MD_EINT2 (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_LTE_URXD (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_DBG_MON_A7 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_ANT_SEL2 (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_PWM2 (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_IRDA_PDN (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_CORESONIC_SWCK (MTK_PIN_NO(21) | 4)
+#define PINMUX_GPIO21__FUNC_MD_EINT1 (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_A8 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_RDN0 (MTK_PIN_NO(22) | 1)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_RDP0 (MTK_PIN_NO(23) | 1)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_RDN1 (MTK_PIN_NO(24) | 1)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_RDP1 (MTK_PIN_NO(25) | 1)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_RCN (MTK_PIN_NO(26) | 1)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_RCP (MTK_PIN_NO(27) | 1)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_RDN2 (MTK_PIN_NO(28) | 1)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_RDP2 (MTK_PIN_NO(29) | 1)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_RDN3 (MTK_PIN_NO(30) | 1)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_RDP3 (MTK_PIN_NO(31) | 1)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_RDN0_A (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_CMHSYNC (MTK_PIN_NO(32) | 2)
+#define PINMUX_GPIO32__FUNC_CMCSD0 (MTK_PIN_NO(32) | 3)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_RDP0_A (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_CMVSYNC (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_CMCSD1 (MTK_PIN_NO(33) | 3)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_RDN1_A (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_CMDAT9 (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_CMCSD2 (MTK_PIN_NO(34) | 3)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_RDP1_A (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_CMDAT8 (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_CMCSD3 (MTK_PIN_NO(35) | 3)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_RCN_A (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_CMDAT7 (MTK_PIN_NO(36) | 2)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_RCP_A (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_CMDAT6 (MTK_PIN_NO(37) | 2)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_RDN2_A (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_CMDAT5 (MTK_PIN_NO(38) | 2)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_RDP2_A (MTK_PIN_NO(39) | 1)
+#define PINMUX_GPIO39__FUNC_CMDAT4 (MTK_PIN_NO(39) | 2)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_RDN3_A (MTK_PIN_NO(40) | 1)
+#define PINMUX_GPIO40__FUNC_CMDAT3 (MTK_PIN_NO(40) | 2)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_RDP3_A (MTK_PIN_NO(41) | 1)
+#define PINMUX_GPIO41__FUNC_CMDAT2 (MTK_PIN_NO(41) | 2)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_CMDAT0 (MTK_PIN_NO(42) | 1)
+#define PINMUX_GPIO42__FUNC_CMCSD0 (MTK_PIN_NO(42) | 2)
+#define PINMUX_GPIO42__FUNC_CMMCLK1 (MTK_PIN_NO(42) | 3)
+#define PINMUX_GPIO42__FUNC_ANT_SEL5 (MTK_PIN_NO(42) | 5)
+#define PINMUX_GPIO42__FUNC_CLKM5 (MTK_PIN_NO(42) | 6)
+#define PINMUX_GPIO42__FUNC_DBG_MON_A9 (MTK_PIN_NO(42) | 7)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_CMDAT1 (MTK_PIN_NO(43) | 1)
+#define PINMUX_GPIO43__FUNC_CMCSD1 (MTK_PIN_NO(43) | 2)
+#define PINMUX_GPIO43__FUNC_CMFLASH (MTK_PIN_NO(43) | 3)
+#define PINMUX_GPIO43__FUNC_MD_EINT0 (MTK_PIN_NO(43) | 4)
+#define PINMUX_GPIO43__FUNC_CMMCLK1 (MTK_PIN_NO(43) | 5)
+#define PINMUX_GPIO43__FUNC_CLKM4 (MTK_PIN_NO(43) | 6)
+#define PINMUX_GPIO43__FUNC_DBG_MON_A10 (MTK_PIN_NO(43) | 7)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_CMPCLK (MTK_PIN_NO(44) | 1)
+#define PINMUX_GPIO44__FUNC_CMCSK (MTK_PIN_NO(44) | 2)
+#define PINMUX_GPIO44__FUNC_CMCSD2 (MTK_PIN_NO(44) | 3)
+#define PINMUX_GPIO44__FUNC_KCOL3 (MTK_PIN_NO(44) | 4)
+#define PINMUX_GPIO44__FUNC_SRCLKENAI2 (MTK_PIN_NO(44) | 5)
+#define PINMUX_GPIO44__FUNC_PWM0 (MTK_PIN_NO(44) | 6)
+#define PINMUX_GPIO44__FUNC_DBG_MON_A11 (MTK_PIN_NO(44) | 7)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_CMMCLK0 (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_DBG_MON_A12 (MTK_PIN_NO(45) | 7)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_CMMCLK1 (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 2)
+#define PINMUX_GPIO46__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(46) | 3)
+#define PINMUX_GPIO46__FUNC_TDD_TRSTN (MTK_PIN_NO(46) | 4)
+#define PINMUX_GPIO46__FUNC_DM_JTINTP (MTK_PIN_NO(46) | 5)
+#define PINMUX_GPIO46__FUNC_KCOL6 (MTK_PIN_NO(46) | 6)
+#define PINMUX_GPIO46__FUNC_DBG_MON_A13 (MTK_PIN_NO(46) | 7)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_SDA0 (MTK_PIN_NO(47) | 1)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_SCL0 (MTK_PIN_NO(48) | 1)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_SDA1 (MTK_PIN_NO(49) | 1)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_SCL1 (MTK_PIN_NO(50) | 1)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_SDA2 (MTK_PIN_NO(51) | 1)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_SCL2 (MTK_PIN_NO(52) | 1)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_SDA3 (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_IDDIG (MTK_PIN_NO(53) | 3)
+#define PINMUX_GPIO53__FUNC_MD_EINT2 (MTK_PIN_NO(53) | 5)
+#define PINMUX_GPIO53__FUNC_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(53) | 6)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_SCL3 (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_IDDIG (MTK_PIN_NO(54) | 3)
+#define PINMUX_GPIO54__FUNC_MD_EINT1 (MTK_PIN_NO(54) | 5)
+#define PINMUX_GPIO54__FUNC_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(54) | 6)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_SRCLKENAI0 (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_PWM2 (MTK_PIN_NO(55) | 2)
+#define PINMUX_GPIO55__FUNC_CLKM5 (MTK_PIN_NO(55) | 3)
+#define PINMUX_GPIO55__FUNC_CORESONIC_SWD (MTK_PIN_NO(55) | 4)
+#define PINMUX_GPIO55__FUNC_ANT_SEL6 (MTK_PIN_NO(55) | 5)
+#define PINMUX_GPIO55__FUNC_KROW5 (MTK_PIN_NO(55) | 6)
+#define PINMUX_GPIO55__FUNC_DISP_PWM (MTK_PIN_NO(55) | 7)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_SRCLKENA1 (MTK_PIN_NO(56) | 1)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_URXD2 (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_DPI_HSYNC0 (MTK_PIN_NO(57) | 2)
+#define PINMUX_GPIO57__FUNC_UTXD2 (MTK_PIN_NO(57) | 3)
+#define PINMUX_GPIO57__FUNC_MD_URXD (MTK_PIN_NO(57) | 4)
+#define PINMUX_GPIO57__FUNC_SRCLKENAI1 (MTK_PIN_NO(57) | 5)
+#define PINMUX_GPIO57__FUNC_KROW4 (MTK_PIN_NO(57) | 6)
+#define PINMUX_GPIO57__FUNC_DBG_MON_A14 (MTK_PIN_NO(57) | 7)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_UTXD2 (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_DPI_VSYNC0 (MTK_PIN_NO(58) | 2)
+#define PINMUX_GPIO58__FUNC_URXD2 (MTK_PIN_NO(58) | 3)
+#define PINMUX_GPIO58__FUNC_MD_UTXD (MTK_PIN_NO(58) | 4)
+#define PINMUX_GPIO58__FUNC_TDD_TXD (MTK_PIN_NO(58) | 5)
+#define PINMUX_GPIO58__FUNC_KROW5 (MTK_PIN_NO(58) | 6)
+#define PINMUX_GPIO58__FUNC_DBG_MON_A15 (MTK_PIN_NO(58) | 7)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_URXD3 (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_DPI_CK0 (MTK_PIN_NO(59) | 2)
+#define PINMUX_GPIO59__FUNC_UTXD3 (MTK_PIN_NO(59) | 3)
+#define PINMUX_GPIO59__FUNC_UCTS2 (MTK_PIN_NO(59) | 4)
+#define PINMUX_GPIO59__FUNC_PWM3 (MTK_PIN_NO(59) | 5)
+#define PINMUX_GPIO59__FUNC_KROW6 (MTK_PIN_NO(59) | 6)
+#define PINMUX_GPIO59__FUNC_DBG_MON_A16 (MTK_PIN_NO(59) | 7)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_UTXD3 (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_DPI_DE0 (MTK_PIN_NO(60) | 2)
+#define PINMUX_GPIO60__FUNC_URXD3 (MTK_PIN_NO(60) | 3)
+#define PINMUX_GPIO60__FUNC_URTS2 (MTK_PIN_NO(60) | 4)
+#define PINMUX_GPIO60__FUNC_PWM4 (MTK_PIN_NO(60) | 5)
+#define PINMUX_GPIO60__FUNC_KROW7 (MTK_PIN_NO(60) | 6)
+#define PINMUX_GPIO60__FUNC_DBG_MON_A17 (MTK_PIN_NO(60) | 7)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_PCM1_CLK (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_DPI_D0 (MTK_PIN_NO(61) | 2)
+#define PINMUX_GPIO61__FUNC_I2S0_BCK (MTK_PIN_NO(61) | 3)
+#define PINMUX_GPIO61__FUNC_KROW4 (MTK_PIN_NO(61) | 4)
+#define PINMUX_GPIO61__FUNC_ANT_SEL3 (MTK_PIN_NO(61) | 5)
+#define PINMUX_GPIO61__FUNC_IRTX_OUT (MTK_PIN_NO(61) | 6)
+#define PINMUX_GPIO61__FUNC_DBG_MON_A18 (MTK_PIN_NO(61) | 7)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_PCM1_SYNC (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_DPI_D1 (MTK_PIN_NO(62) | 2)
+#define PINMUX_GPIO62__FUNC_I2S0_LRCK (MTK_PIN_NO(62) | 3)
+#define PINMUX_GPIO62__FUNC_KCOL7 (MTK_PIN_NO(62) | 4)
+#define PINMUX_GPIO62__FUNC_CLKM3 (MTK_PIN_NO(62) | 5)
+#define PINMUX_GPIO62__FUNC_CMFLASH (MTK_PIN_NO(62) | 6)
+#define PINMUX_GPIO62__FUNC_DBG_MON_A19 (MTK_PIN_NO(62) | 7)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_PCM1_DI (MTK_PIN_NO(63) | 1)
+#define PINMUX_GPIO63__FUNC_DPI_D2 (MTK_PIN_NO(63) | 2)
+#define PINMUX_GPIO63__FUNC_I2S0_DI (MTK_PIN_NO(63) | 3)
+#define PINMUX_GPIO63__FUNC_PCM1_DO0 (MTK_PIN_NO(63) | 4)
+#define PINMUX_GPIO63__FUNC_CLKM5 (MTK_PIN_NO(63) | 5)
+#define PINMUX_GPIO63__FUNC_KROW3 (MTK_PIN_NO(63) | 6)
+#define PINMUX_GPIO63__FUNC_DBG_MON_A20 (MTK_PIN_NO(63) | 7)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_PCM1_DO0 (MTK_PIN_NO(64) | 1)
+#define PINMUX_GPIO64__FUNC_DPI_D3 (MTK_PIN_NO(64) | 2)
+#define PINMUX_GPIO64__FUNC_I2S0_MCK (MTK_PIN_NO(64) | 3)
+#define PINMUX_GPIO64__FUNC_PCM1_DI (MTK_PIN_NO(64) | 4)
+#define PINMUX_GPIO64__FUNC_SRCLKENAI2 (MTK_PIN_NO(64) | 5)
+#define PINMUX_GPIO64__FUNC_KCOL5 (MTK_PIN_NO(64) | 6)
+#define PINMUX_GPIO64__FUNC_DBG_MON_A21 (MTK_PIN_NO(64) | 7)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_SPI_CSA (MTK_PIN_NO(65) | 1)
+#define PINMUX_GPIO65__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(65) | 2)
+#define PINMUX_GPIO65__FUNC_I2S3_MCK (MTK_PIN_NO(65) | 3)
+#define PINMUX_GPIO65__FUNC_KROW2 (MTK_PIN_NO(65) | 4)
+#define PINMUX_GPIO65__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(65) | 5)
+#define PINMUX_GPIO65__FUNC_PTA_RXD (MTK_PIN_NO(65) | 6)
+#define PINMUX_GPIO65__FUNC_DBG_MON_A22 (MTK_PIN_NO(65) | 7)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_SPI_CKA (MTK_PIN_NO(66) | 1)
+#define PINMUX_GPIO66__FUNC_USB_DRVVBUS (MTK_PIN_NO(66) | 2)
+#define PINMUX_GPIO66__FUNC_I2S3_BCK (MTK_PIN_NO(66) | 3)
+#define PINMUX_GPIO66__FUNC_KCOL2 (MTK_PIN_NO(66) | 4)
+#define PINMUX_GPIO66__FUNC_PTA_TXD (MTK_PIN_NO(66) | 6)
+#define PINMUX_GPIO66__FUNC_DBG_MON_A23 (MTK_PIN_NO(66) | 7)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_SPI_MIA (MTK_PIN_NO(67) | 1)
+#define PINMUX_GPIO67__FUNC_SPI_MOA (MTK_PIN_NO(67) | 2)
+#define PINMUX_GPIO67__FUNC_I2S3_DO (MTK_PIN_NO(67) | 3)
+#define PINMUX_GPIO67__FUNC_PTA_RXD (MTK_PIN_NO(67) | 4)
+#define PINMUX_GPIO67__FUNC_IDDIG (MTK_PIN_NO(67) | 5)
+#define PINMUX_GPIO67__FUNC_UCTS1 (MTK_PIN_NO(67) | 6)
+#define PINMUX_GPIO67__FUNC_DBG_MON_A24 (MTK_PIN_NO(67) | 7)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_SPI_MOA (MTK_PIN_NO(68) | 1)
+#define PINMUX_GPIO68__FUNC_SPI_MIA (MTK_PIN_NO(68) | 2)
+#define PINMUX_GPIO68__FUNC_I2S3_LRCK (MTK_PIN_NO(68) | 3)
+#define PINMUX_GPIO68__FUNC_PTA_TXD (MTK_PIN_NO(68) | 4)
+#define PINMUX_GPIO68__FUNC_ANT_SEL4 (MTK_PIN_NO(68) | 5)
+#define PINMUX_GPIO68__FUNC_URTS1 (MTK_PIN_NO(68) | 6)
+#define PINMUX_GPIO68__FUNC_DBG_MON_A25 (MTK_PIN_NO(68) | 7)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_DISP_PWM (MTK_PIN_NO(69) | 1)
+#define PINMUX_GPIO69__FUNC_PWM1 (MTK_PIN_NO(69) | 2)
+#define PINMUX_GPIO69__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(69) | 3)
+#define PINMUX_GPIO69__FUNC_TDD_TRSTN (MTK_PIN_NO(69) | 4)
+#define PINMUX_GPIO69__FUNC_ANT_SEL7 (MTK_PIN_NO(69) | 5)
+#define PINMUX_GPIO69__FUNC_DM_JTINTP (MTK_PIN_NO(69) | 6)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_JTMS (MTK_PIN_NO(70) | 1)
+#define PINMUX_GPIO70__FUNC_CONN_MCU_TMS (MTK_PIN_NO(70) | 2)
+#define PINMUX_GPIO70__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(70) | 3)
+#define PINMUX_GPIO70__FUNC_TDD_TMS (MTK_PIN_NO(70) | 4)
+#define PINMUX_GPIO70__FUNC_CORESONIC_SWD (MTK_PIN_NO(70) | 5)
+#define PINMUX_GPIO70__FUNC_DM_OTMS (MTK_PIN_NO(70) | 6)
+#define PINMUX_GPIO70__FUNC_DFD_TMS (MTK_PIN_NO(70) | 7)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_JTCK (MTK_PIN_NO(71) | 1)
+#define PINMUX_GPIO71__FUNC_CONN_MCU_TCK_1 (MTK_PIN_NO(71) | 2)
+#define PINMUX_GPIO71__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(71) | 3)
+#define PINMUX_GPIO71__FUNC_TDD_TCK (MTK_PIN_NO(71) | 4)
+#define PINMUX_GPIO71__FUNC_CORESONIC_SWCK (MTK_PIN_NO(71) | 5)
+#define PINMUX_GPIO71__FUNC_DM_OTCK (MTK_PIN_NO(71) | 6)
+#define PINMUX_GPIO71__FUNC_DFD_TCK_XI (MTK_PIN_NO(71) | 7)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_JTDI (MTK_PIN_NO(72) | 1)
+#define PINMUX_GPIO72__FUNC_CONN_MCU_TDI (MTK_PIN_NO(72) | 2)
+#define PINMUX_GPIO72__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(72) | 3)
+#define PINMUX_GPIO72__FUNC_TDD_TDI (MTK_PIN_NO(72) | 4)
+#define PINMUX_GPIO72__FUNC_DM_OTDI (MTK_PIN_NO(72) | 6)
+#define PINMUX_GPIO72__FUNC_DFD_TDI (MTK_PIN_NO(72) | 7)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_JTDO (MTK_PIN_NO(73) | 1)
+#define PINMUX_GPIO73__FUNC_CONN_MCU_TDO (MTK_PIN_NO(73) | 2)
+#define PINMUX_GPIO73__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(73) | 3)
+#define PINMUX_GPIO73__FUNC_TDD_TDO (MTK_PIN_NO(73) | 4)
+#define PINMUX_GPIO73__FUNC_DM_OTDO (MTK_PIN_NO(73) | 6)
+#define PINMUX_GPIO73__FUNC_DFD_TDO (MTK_PIN_NO(73) | 7)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_URXD0 (MTK_PIN_NO(74) | 1)
+#define PINMUX_GPIO74__FUNC_UTXD0 (MTK_PIN_NO(74) | 2)
+#define PINMUX_GPIO74__FUNC_MD_URXD (MTK_PIN_NO(74) | 3)
+#define PINMUX_GPIO74__FUNC_SDA3 (MTK_PIN_NO(74) | 4)
+#define PINMUX_GPIO74__FUNC_C2K_UART0_RXD (MTK_PIN_NO(74) | 5)
+#define PINMUX_GPIO74__FUNC_LTE_URXD (MTK_PIN_NO(74) | 6)
+#define PINMUX_GPIO74__FUNC_AUXIF_ST (MTK_PIN_NO(74) | 7)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_UTXD0 (MTK_PIN_NO(75) | 1)
+#define PINMUX_GPIO75__FUNC_URXD0 (MTK_PIN_NO(75) | 2)
+#define PINMUX_GPIO75__FUNC_MD_UTXD (MTK_PIN_NO(75) | 3)
+#define PINMUX_GPIO75__FUNC_TDD_TXD (MTK_PIN_NO(75) | 4)
+#define PINMUX_GPIO75__FUNC_C2K_UART0_TXD (MTK_PIN_NO(75) | 5)
+#define PINMUX_GPIO75__FUNC_LTE_UTXD (MTK_PIN_NO(75) | 6)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_URXD1 (MTK_PIN_NO(76) | 1)
+#define PINMUX_GPIO76__FUNC_UTXD1 (MTK_PIN_NO(76) | 2)
+#define PINMUX_GPIO76__FUNC_MD_URXD (MTK_PIN_NO(76) | 3)
+#define PINMUX_GPIO76__FUNC_SCL3 (MTK_PIN_NO(76) | 4)
+#define PINMUX_GPIO76__FUNC_LTE_URXD (MTK_PIN_NO(76) | 5)
+#define PINMUX_GPIO76__FUNC_C2K_UART0_RXD (MTK_PIN_NO(76) | 6)
+#define PINMUX_GPIO76__FUNC_AUXIF_CLK (MTK_PIN_NO(76) | 7)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_UTXD1 (MTK_PIN_NO(77) | 1)
+#define PINMUX_GPIO77__FUNC_URXD1 (MTK_PIN_NO(77) | 2)
+#define PINMUX_GPIO77__FUNC_MD_UTXD (MTK_PIN_NO(77) | 3)
+#define PINMUX_GPIO77__FUNC_TDD_TXD (MTK_PIN_NO(77) | 4)
+#define PINMUX_GPIO77__FUNC_LTE_UTXD (MTK_PIN_NO(77) | 5)
+#define PINMUX_GPIO77__FUNC_C2K_UART0_TXD (MTK_PIN_NO(77) | 6)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_I2S0_DI (MTK_PIN_NO(78) | 1)
+#define PINMUX_GPIO78__FUNC_PCM1_DI (MTK_PIN_NO(78) | 2)
+#define PINMUX_GPIO78__FUNC_I2S3_DO (MTK_PIN_NO(78) | 3)
+#define PINMUX_GPIO78__FUNC_I2S1_DO (MTK_PIN_NO(78) | 4)
+#define PINMUX_GPIO78__FUNC_PWM0 (MTK_PIN_NO(78) | 5)
+#define PINMUX_GPIO78__FUNC_I2S2_DI (MTK_PIN_NO(78) | 6)
+#define PINMUX_GPIO78__FUNC_DBG_MON_A26 (MTK_PIN_NO(78) | 7)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_I2S0_LRCK (MTK_PIN_NO(79) | 1)
+#define PINMUX_GPIO79__FUNC_PCM1_SYNC (MTK_PIN_NO(79) | 2)
+#define PINMUX_GPIO79__FUNC_I2S3_LRCK (MTK_PIN_NO(79) | 3)
+#define PINMUX_GPIO79__FUNC_I2S1_LRCK (MTK_PIN_NO(79) | 4)
+#define PINMUX_GPIO79__FUNC_PWM3 (MTK_PIN_NO(79) | 5)
+#define PINMUX_GPIO79__FUNC_I2S2_LRCK (MTK_PIN_NO(79) | 6)
+#define PINMUX_GPIO79__FUNC_DBG_MON_A27 (MTK_PIN_NO(79) | 7)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_I2S0_BCK (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_PCM1_CLK (MTK_PIN_NO(80) | 2)
+#define PINMUX_GPIO80__FUNC_I2S3_BCK (MTK_PIN_NO(80) | 3)
+#define PINMUX_GPIO80__FUNC_I2S1_BCK (MTK_PIN_NO(80) | 4)
+#define PINMUX_GPIO80__FUNC_PWM4 (MTK_PIN_NO(80) | 5)
+#define PINMUX_GPIO80__FUNC_I2S2_BCK (MTK_PIN_NO(80) | 6)
+#define PINMUX_GPIO80__FUNC_DBG_MON_A28 (MTK_PIN_NO(80) | 7)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_KROW0 (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(81) | 3)
+#define PINMUX_GPIO81__FUNC_CORESONIC_SWCK (MTK_PIN_NO(81) | 4)
+#define PINMUX_GPIO81__FUNC_C2K_TCK (MTK_PIN_NO(81) | 5)
+#define PINMUX_GPIO81__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(81) | 7)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_KROW1 (MTK_PIN_NO(82) | 1)
+#define PINMUX_GPIO82__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(82) | 3)
+#define PINMUX_GPIO82__FUNC_CORESONIC_SWD (MTK_PIN_NO(82) | 4)
+#define PINMUX_GPIO82__FUNC_C2K_NTRST (MTK_PIN_NO(82) | 5)
+#define PINMUX_GPIO82__FUNC_USB_DRVVBUS (MTK_PIN_NO(82) | 6)
+#define PINMUX_GPIO82__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(82) | 7)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_KROW2 (MTK_PIN_NO(83) | 1)
+#define PINMUX_GPIO83__FUNC_USB_DRVVBUS (MTK_PIN_NO(83) | 2)
+#define PINMUX_GPIO83__FUNC_C2K_TDI (MTK_PIN_NO(83) | 5)
+#define PINMUX_GPIO83__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(83) | 7)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_KCOL0 (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_URTS0 (MTK_PIN_NO(84) | 2)
+#define PINMUX_GPIO84__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(84) | 3)
+#define PINMUX_GPIO84__FUNC_SCL2 (MTK_PIN_NO(84) | 4)
+#define PINMUX_GPIO84__FUNC_C2K_TDO (MTK_PIN_NO(84) | 5)
+#define PINMUX_GPIO84__FUNC_AUXIF_CLK (MTK_PIN_NO(84) | 6)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_KCOL1 (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_UCTS0 (MTK_PIN_NO(85) | 2)
+#define PINMUX_GPIO85__FUNC_UCTS1 (MTK_PIN_NO(85) | 3)
+#define PINMUX_GPIO85__FUNC_SDA2 (MTK_PIN_NO(85) | 4)
+#define PINMUX_GPIO85__FUNC_C2K_TMS (MTK_PIN_NO(85) | 5)
+#define PINMUX_GPIO85__FUNC_AUXIF_ST (MTK_PIN_NO(85) | 6)
+#define PINMUX_GPIO85__FUNC_DBG_MON_A31 (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_KCOL2 (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_URTS1 (MTK_PIN_NO(86) | 3)
+#define PINMUX_GPIO86__FUNC_C2K_RTCK (MTK_PIN_NO(86) | 5)
+#define PINMUX_GPIO86__FUNC_DBG_MON_A32 (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_BPI_BUS5 (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_LTE_C2K_BPI_BUS5 (MTK_PIN_NO(87) | 2)
+#define PINMUX_GPIO87__FUNC_C2K_BPI_BUS5 (MTK_PIN_NO(87) | 5)
+#define PINMUX_GPIO87__FUNC_DBG_MON_B0 (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_BPI_BUS6 (MTK_PIN_NO(88) | 1)
+#define PINMUX_GPIO88__FUNC_LTE_C2K_BPI_BUS6 (MTK_PIN_NO(88) | 2)
+#define PINMUX_GPIO88__FUNC_C2K_BPI_BUS6 (MTK_PIN_NO(88) | 5)
+#define PINMUX_GPIO88__FUNC_DBG_MON_B1 (MTK_PIN_NO(88) | 7)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_BPI_BUS7 (MTK_PIN_NO(89) | 1)
+#define PINMUX_GPIO89__FUNC_LTE_C2K_BPI_BUS7 (MTK_PIN_NO(89) | 2)
+#define PINMUX_GPIO89__FUNC_CLKM0 (MTK_PIN_NO(89) | 3)
+#define PINMUX_GPIO89__FUNC_C2K_BPI_BUS7 (MTK_PIN_NO(89) | 5)
+#define PINMUX_GPIO89__FUNC_DBG_MON_B2 (MTK_PIN_NO(89) | 7)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_BPI_BUS8 (MTK_PIN_NO(90) | 1)
+#define PINMUX_GPIO90__FUNC_LTE_C2K_BPI_BUS8 (MTK_PIN_NO(90) | 2)
+#define PINMUX_GPIO90__FUNC_CLKM1 (MTK_PIN_NO(90) | 3)
+#define PINMUX_GPIO90__FUNC_C2K_BPI_BUS8 (MTK_PIN_NO(90) | 5)
+#define PINMUX_GPIO90__FUNC_DBG_MON_B3 (MTK_PIN_NO(90) | 7)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_BPI_BUS9 (MTK_PIN_NO(91) | 1)
+#define PINMUX_GPIO91__FUNC_LTE_C2K_BPI_BUS9 (MTK_PIN_NO(91) | 2)
+#define PINMUX_GPIO91__FUNC_CLKM2 (MTK_PIN_NO(91) | 3)
+#define PINMUX_GPIO91__FUNC_C2K_BPI_BUS9 (MTK_PIN_NO(91) | 5)
+#define PINMUX_GPIO91__FUNC_DBG_MON_B4 (MTK_PIN_NO(91) | 7)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_BPI_BUS10 (MTK_PIN_NO(92) | 1)
+#define PINMUX_GPIO92__FUNC_LTE_C2K_BPI_BUS10 (MTK_PIN_NO(92) | 2)
+#define PINMUX_GPIO92__FUNC_CLKM3 (MTK_PIN_NO(92) | 3)
+#define PINMUX_GPIO92__FUNC_C2K_BPI_BUS10 (MTK_PIN_NO(92) | 5)
+#define PINMUX_GPIO92__FUNC_DBG_MON_B5 (MTK_PIN_NO(92) | 7)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_BPI_BUS11 (MTK_PIN_NO(93) | 1)
+#define PINMUX_GPIO93__FUNC_LTE_C2K_BPI_BUS11 (MTK_PIN_NO(93) | 2)
+#define PINMUX_GPIO93__FUNC_C2K_BPI_BUS11 (MTK_PIN_NO(93) | 5)
+#define PINMUX_GPIO93__FUNC_DBG_MON_B6 (MTK_PIN_NO(93) | 7)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_BPI_BUS12 (MTK_PIN_NO(94) | 1)
+#define PINMUX_GPIO94__FUNC_LTE_C2K_BPI_BUS12 (MTK_PIN_NO(94) | 2)
+#define PINMUX_GPIO94__FUNC_C2K_BPI_BUS12 (MTK_PIN_NO(94) | 5)
+#define PINMUX_GPIO94__FUNC_DBG_MON_B7 (MTK_PIN_NO(94) | 7)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_BPI_BUS13 (MTK_PIN_NO(95) | 1)
+#define PINMUX_GPIO95__FUNC_LTE_C2K_BPI_BUS13 (MTK_PIN_NO(95) | 2)
+#define PINMUX_GPIO95__FUNC_C2K_BPI_BUS13 (MTK_PIN_NO(95) | 5)
+#define PINMUX_GPIO95__FUNC_DBG_MON_B8 (MTK_PIN_NO(95) | 7)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_BPI_BUS14 (MTK_PIN_NO(96) | 1)
+#define PINMUX_GPIO96__FUNC_LTE_C2K_BPI_BUS14 (MTK_PIN_NO(96) | 2)
+#define PINMUX_GPIO96__FUNC_C2K_BPI_BUS14 (MTK_PIN_NO(96) | 5)
+#define PINMUX_GPIO96__FUNC_DBG_MON_B9 (MTK_PIN_NO(96) | 7)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_BPI_BUS15 (MTK_PIN_NO(97) | 1)
+#define PINMUX_GPIO97__FUNC_LTE_C2K_BPI_BUS15 (MTK_PIN_NO(97) | 2)
+#define PINMUX_GPIO97__FUNC_C2K_BPI_BUS15 (MTK_PIN_NO(97) | 5)
+#define PINMUX_GPIO97__FUNC_DBG_MON_B10 (MTK_PIN_NO(97) | 7)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_BPI_BUS16 (MTK_PIN_NO(98) | 1)
+#define PINMUX_GPIO98__FUNC_LTE_C2K_BPI_BUS16 (MTK_PIN_NO(98) | 2)
+#define PINMUX_GPIO98__FUNC_C2K_BPI_BUS16 (MTK_PIN_NO(98) | 5)
+#define PINMUX_GPIO98__FUNC_DBG_MON_B11 (MTK_PIN_NO(98) | 7)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_BPI_BUS17 (MTK_PIN_NO(99) | 1)
+#define PINMUX_GPIO99__FUNC_LTE_C2K_BPI_BUS17 (MTK_PIN_NO(99) | 2)
+#define PINMUX_GPIO99__FUNC_C2K_BPI_BUS17 (MTK_PIN_NO(99) | 5)
+#define PINMUX_GPIO99__FUNC_DBG_MON_B12 (MTK_PIN_NO(99) | 7)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_BPI_BUS18 (MTK_PIN_NO(100) | 1)
+#define PINMUX_GPIO100__FUNC_LTE_C2K_BPI_BUS18 (MTK_PIN_NO(100) | 2)
+#define PINMUX_GPIO100__FUNC_C2K_BPI_BUS18 (MTK_PIN_NO(100) | 5)
+#define PINMUX_GPIO100__FUNC_DBG_MON_B13 (MTK_PIN_NO(100) | 7)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_BPI_BUS19 (MTK_PIN_NO(101) | 1)
+#define PINMUX_GPIO101__FUNC_LTE_C2K_BPI_BUS19 (MTK_PIN_NO(101) | 2)
+#define PINMUX_GPIO101__FUNC_C2K_BPI_BUS19 (MTK_PIN_NO(101) | 5)
+#define PINMUX_GPIO101__FUNC_DBG_MON_B14 (MTK_PIN_NO(101) | 7)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_BPI_BUS20 (MTK_PIN_NO(102) | 1)
+#define PINMUX_GPIO102__FUNC_LTE_C2K_BPI_BUS20 (MTK_PIN_NO(102) | 2)
+#define PINMUX_GPIO102__FUNC_C2K_BPI_BUS20 (MTK_PIN_NO(102) | 5)
+#define PINMUX_GPIO102__FUNC_DBG_MON_B15 (MTK_PIN_NO(102) | 7)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_C2K_TXBPI (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_DBG_MON_B16 (MTK_PIN_NO(103) | 7)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_RFIC1_BSI_EN (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_C2K_RX_BSI_EN (MTK_PIN_NO(104) | 5)
+#define PINMUX_GPIO104__FUNC_DBG_MON_B17 (MTK_PIN_NO(104) | 7)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_RFIC1_BSI_CK (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_C2K_RX_BSI_CLK (MTK_PIN_NO(105) | 5)
+#define PINMUX_GPIO105__FUNC_DBG_MON_B18 (MTK_PIN_NO(105) | 7)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_RFIC1_BSI_D0 (MTK_PIN_NO(106) | 1)
+#define PINMUX_GPIO106__FUNC_C2K_RX_BSI_DATA (MTK_PIN_NO(106) | 5)
+#define PINMUX_GPIO106__FUNC_DBG_MON_B19 (MTK_PIN_NO(106) | 7)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_RFIC1_BSI_D1 (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_C2K_TX_BSI_EN (MTK_PIN_NO(107) | 5)
+#define PINMUX_GPIO107__FUNC_DBG_MON_B20 (MTK_PIN_NO(107) | 7)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_RFIC1_BSI_D2 (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_C2K_TX_BSI_CLK (MTK_PIN_NO(108) | 5)
+#define PINMUX_GPIO108__FUNC_DBG_MON_B21 (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_C2K_TX_BSI_DATA (MTK_PIN_NO(109) | 5)
+#define PINMUX_GPIO109__FUNC_DBG_MON_B22 (MTK_PIN_NO(109) | 7)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_SPM_BSI_EN (MTK_PIN_NO(110) | 4)
+#define PINMUX_GPIO110__FUNC_DBG_MON_B23 (MTK_PIN_NO(110) | 7)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_SPM_BSI_CLK (MTK_PIN_NO(111) | 4)
+#define PINMUX_GPIO111__FUNC_DBG_MON_B24 (MTK_PIN_NO(111) | 7)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_SPM_BSI_D2 (MTK_PIN_NO(112) | 4)
+#define PINMUX_GPIO112__FUNC_DBG_MON_B25 (MTK_PIN_NO(112) | 7)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_SPM_BSI_D1 (MTK_PIN_NO(113) | 4)
+#define PINMUX_GPIO113__FUNC_DBG_MON_B26 (MTK_PIN_NO(113) | 7)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_SPM_BSI_D0 (MTK_PIN_NO(114) | 4)
+#define PINMUX_GPIO114__FUNC_DBG_MON_B27 (MTK_PIN_NO(114) | 7)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_AUXIN0 (MTK_PIN_NO(115) | 1)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_AUXIN1 (MTK_PIN_NO(116) | 1)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_AUXIN2 (MTK_PIN_NO(117) | 1)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_TXBPI (MTK_PIN_NO(118) | 1)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_BPI_BUS0 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_DBG_MON_B28 (MTK_PIN_NO(119) | 7)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_BPI_BUS1 (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_DBG_MON_B29 (MTK_PIN_NO(120) | 7)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_BPI_BUS2 (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_DBG_MON_B30 (MTK_PIN_NO(121) | 7)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_BPI_BUS3 (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_DBG_MON_B31 (MTK_PIN_NO(122) | 7)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_BPI_BUS4 (MTK_PIN_NO(123) | 1)
+#define PINMUX_GPIO123__FUNC_DBG_MON_B32 (MTK_PIN_NO(123) | 7)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_BPI_BUS21 (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_DPI_HSYNC1 (MTK_PIN_NO(124) | 5)
+#define PINMUX_GPIO124__FUNC_KCOL2 (MTK_PIN_NO(124) | 6)
+#define PINMUX_GPIO124__FUNC_TDD_TXD (MTK_PIN_NO(124) | 7)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_BPI_BUS22 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_DPI_VSYNC1 (MTK_PIN_NO(125) | 5)
+#define PINMUX_GPIO125__FUNC_KROW2 (MTK_PIN_NO(125) | 6)
+#define PINMUX_GPIO125__FUNC_MD_URXD (MTK_PIN_NO(125) | 7)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_BPI_BUS23 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_DPI_CK1 (MTK_PIN_NO(126) | 5)
+#define PINMUX_GPIO126__FUNC_I2S2_MCK (MTK_PIN_NO(126) | 6)
+#define PINMUX_GPIO126__FUNC_MD_UTXD (MTK_PIN_NO(126) | 7)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_BPI_BUS24 (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(127) | 3)
+#define PINMUX_GPIO127__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(127) | 4)
+#define PINMUX_GPIO127__FUNC_DPI_DE1 (MTK_PIN_NO(127) | 5)
+#define PINMUX_GPIO127__FUNC_SRCLKENAI1 (MTK_PIN_NO(127) | 6)
+#define PINMUX_GPIO127__FUNC_URXD0 (MTK_PIN_NO(127) | 7)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_BPI_BUS25 (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(128) | 3)
+#define PINMUX_GPIO128__FUNC_I2S2_DI (MTK_PIN_NO(128) | 5)
+#define PINMUX_GPIO128__FUNC_PTA_RXD (MTK_PIN_NO(128) | 6)
+#define PINMUX_GPIO128__FUNC_UTXD0 (MTK_PIN_NO(128) | 7)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_BPI_BUS26 (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_DISP_PWM (MTK_PIN_NO(129) | 2)
+#define PINMUX_GPIO129__FUNC_I2S2_LRCK (MTK_PIN_NO(129) | 5)
+#define PINMUX_GPIO129__FUNC_PTA_TXD (MTK_PIN_NO(129) | 6)
+#define PINMUX_GPIO129__FUNC_LTE_URXD (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_BPI_BUS27 (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_I2S2_BCK (MTK_PIN_NO(130) | 5)
+#define PINMUX_GPIO130__FUNC_IRTX_OUT (MTK_PIN_NO(130) | 6)
+#define PINMUX_GPIO130__FUNC_LTE_UTXD (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_LTE_PAVM0 (MTK_PIN_NO(131) | 1)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_LTE_PAVM1 (MTK_PIN_NO(132) | 1)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_MIPI1_SCLK (MTK_PIN_NO(133) | 1)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_MIPI1_SDATA (MTK_PIN_NO(134) | 1)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_MIPI0_SCLK (MTK_PIN_NO(135) | 1)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_MIPI0_SDATA (MTK_PIN_NO(136) | 1)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_RTC32K_CK (MTK_PIN_NO(137) | 1)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_PWRAP_SPIDO (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_PWRAP_SPIDI (MTK_PIN_NO(138) | 2)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_PWRAP_SPIDI (MTK_PIN_NO(139) | 1)
+#define PINMUX_GPIO139__FUNC_PWRAP_SPIDO (MTK_PIN_NO(139) | 2)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(140) | 3)
+#define PINMUX_GPIO140__FUNC_TDD_TRSTN (MTK_PIN_NO(140) | 4)
+#define PINMUX_GPIO140__FUNC_DM_JTINTP (MTK_PIN_NO(140) | 5)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(141) | 1)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(142) | 1)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(143) | 1)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_AUD_DAT_MISO (MTK_PIN_NO(144) | 1)
+#define PINMUX_GPIO144__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(144) | 3)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(145) | 1)
+#define PINMUX_GPIO145__FUNC_AUD_DAT_MISO (MTK_PIN_NO(145) | 3)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_LCM_RST (MTK_PIN_NO(146) | 1)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_DSI_TE (MTK_PIN_NO(147) | 1)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_SRCLKENA (MTK_PIN_NO(148) | 1)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_WATCHDOG (MTK_PIN_NO(149) | 1)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_TDP0 (MTK_PIN_NO(150) | 1)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_TDN0 (MTK_PIN_NO(151) | 1)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_TDP1 (MTK_PIN_NO(152) | 1)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_TDN1 (MTK_PIN_NO(153) | 1)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_TCP (MTK_PIN_NO(154) | 1)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_TCN (MTK_PIN_NO(155) | 1)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_TDP2 (MTK_PIN_NO(156) | 1)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_TDN2 (MTK_PIN_NO(157) | 1)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_TDP3 (MTK_PIN_NO(158) | 1)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_TDN3 (MTK_PIN_NO(159) | 1)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_MD_SIM2_SCLK (MTK_PIN_NO(160) | 1)
+#define PINMUX_GPIO160__FUNC_MD_SIM1_SCLK (MTK_PIN_NO(160) | 2)
+#define PINMUX_GPIO160__FUNC_UIM0_CLK (MTK_PIN_NO(160) | 3)
+#define PINMUX_GPIO160__FUNC_UIM1_CLK (MTK_PIN_NO(160) | 4)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_MD_SIM2_SRST (MTK_PIN_NO(161) | 1)
+#define PINMUX_GPIO161__FUNC_MD_SIM1_SRST (MTK_PIN_NO(161) | 2)
+#define PINMUX_GPIO161__FUNC_UIM0_RST (MTK_PIN_NO(161) | 3)
+#define PINMUX_GPIO161__FUNC_UIM1_RST (MTK_PIN_NO(161) | 4)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_MD_SIM2_SDAT (MTK_PIN_NO(162) | 1)
+#define PINMUX_GPIO162__FUNC_MD_SIM1_SDAT (MTK_PIN_NO(162) | 2)
+#define PINMUX_GPIO162__FUNC_UIM0_IO (MTK_PIN_NO(162) | 3)
+#define PINMUX_GPIO162__FUNC_UIM1_IO (MTK_PIN_NO(162) | 4)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_MD_SIM1_SCLK (MTK_PIN_NO(163) | 1)
+#define PINMUX_GPIO163__FUNC_MD_SIM2_SCLK (MTK_PIN_NO(163) | 2)
+#define PINMUX_GPIO163__FUNC_UIM1_CLK (MTK_PIN_NO(163) | 3)
+#define PINMUX_GPIO163__FUNC_UIM0_CLK (MTK_PIN_NO(163) | 4)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_MD_SIM1_SRST (MTK_PIN_NO(164) | 1)
+#define PINMUX_GPIO164__FUNC_MD_SIM2_SRST (MTK_PIN_NO(164) | 2)
+#define PINMUX_GPIO164__FUNC_UIM1_RST (MTK_PIN_NO(164) | 3)
+#define PINMUX_GPIO164__FUNC_UIM0_RST (MTK_PIN_NO(164) | 4)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_MD_SIM1_SDAT (MTK_PIN_NO(165) | 1)
+#define PINMUX_GPIO165__FUNC_MD_SIM2_SDAT (MTK_PIN_NO(165) | 2)
+#define PINMUX_GPIO165__FUNC_UIM1_IO (MTK_PIN_NO(165) | 3)
+#define PINMUX_GPIO165__FUNC_UIM0_IO (MTK_PIN_NO(165) | 4)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_MSDC1_CMD (MTK_PIN_NO(166) | 1)
+#define PINMUX_GPIO166__FUNC_LTE_MD32_JTAG_TMS (MTK_PIN_NO(166) | 2)
+#define PINMUX_GPIO166__FUNC_C2K_TMS (MTK_PIN_NO(166) | 3)
+#define PINMUX_GPIO166__FUNC_TDD_TMS (MTK_PIN_NO(166) | 4)
+#define PINMUX_GPIO166__FUNC_CONN_DSP_JMS (MTK_PIN_NO(166) | 5)
+#define PINMUX_GPIO166__FUNC_JTMS (MTK_PIN_NO(166) | 6)
+#define PINMUX_GPIO166__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(166) | 7)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_MSDC1_CLK (MTK_PIN_NO(167) | 1)
+#define PINMUX_GPIO167__FUNC_LTE_MD32_JTAG_TCK (MTK_PIN_NO(167) | 2)
+#define PINMUX_GPIO167__FUNC_C2K_TCK (MTK_PIN_NO(167) | 3)
+#define PINMUX_GPIO167__FUNC_TDD_TCK (MTK_PIN_NO(167) | 4)
+#define PINMUX_GPIO167__FUNC_CONN_DSP_JCK (MTK_PIN_NO(167) | 5)
+#define PINMUX_GPIO167__FUNC_JTCK (MTK_PIN_NO(167) | 6)
+#define PINMUX_GPIO167__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(167) | 7)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_MSDC1_DAT0 (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_LTE_MD32_JTAG_TDI (MTK_PIN_NO(168) | 2)
+#define PINMUX_GPIO168__FUNC_C2K_TDI (MTK_PIN_NO(168) | 3)
+#define PINMUX_GPIO168__FUNC_TDD_TDI (MTK_PIN_NO(168) | 4)
+#define PINMUX_GPIO168__FUNC_CONN_DSP_JDI (MTK_PIN_NO(168) | 5)
+#define PINMUX_GPIO168__FUNC_JTDI (MTK_PIN_NO(168) | 6)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_MSDC1_DAT1 (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_LTE_MD32_JTAG_TDO (MTK_PIN_NO(169) | 2)
+#define PINMUX_GPIO169__FUNC_C2K_TDO (MTK_PIN_NO(169) | 3)
+#define PINMUX_GPIO169__FUNC_TDD_TDO (MTK_PIN_NO(169) | 4)
+#define PINMUX_GPIO169__FUNC_CONN_DSP_JDO (MTK_PIN_NO(169) | 5)
+#define PINMUX_GPIO169__FUNC_JTDO (MTK_PIN_NO(169) | 6)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_MSDC1_DAT2 (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_LTE_MD32_JTAG_TRST (MTK_PIN_NO(170) | 2)
+#define PINMUX_GPIO170__FUNC_C2K_NTRST (MTK_PIN_NO(170) | 3)
+#define PINMUX_GPIO170__FUNC_TDD_TRSTN (MTK_PIN_NO(170) | 4)
+#define PINMUX_GPIO170__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(170) | 5)
+#define PINMUX_GPIO170__FUNC_DM_JTINTP (MTK_PIN_NO(170) | 6)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_MSDC1_DAT3 (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_C2K_RTCK (MTK_PIN_NO(171) | 3)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_MSDC0_CMD (MTK_PIN_NO(172) | 1)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_MSDC0_DSL (MTK_PIN_NO(173) | 1)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_MSDC0_CLK (MTK_PIN_NO(174) | 1)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_MSDC0_DAT0 (MTK_PIN_NO(175) | 1)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_MSDC0_DAT1 (MTK_PIN_NO(176) | 1)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_MSDC0_DAT2 (MTK_PIN_NO(177) | 1)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_MSDC0_DAT3 (MTK_PIN_NO(178) | 1)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_MSDC0_DAT4 (MTK_PIN_NO(179) | 1)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_MSDC0_DAT5 (MTK_PIN_NO(180) | 1)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_MSDC0_DAT6 (MTK_PIN_NO(181) | 1)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_MSDC0_DAT7 (MTK_PIN_NO(182) | 1)
+
+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define PINMUX_GPIO183__FUNC_MSDC0_RSTB (MTK_PIN_NO(183) | 1)
+
+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define PINMUX_GPIO184__FUNC_F2W_DATA (MTK_PIN_NO(184) | 1)
+#define PINMUX_GPIO184__FUNC_MRG_CLK (MTK_PIN_NO(184) | 2)
+#define PINMUX_GPIO184__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(184) | 3)
+#define PINMUX_GPIO184__FUNC_PCM0_CLK (MTK_PIN_NO(184) | 4)
+
+#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define PINMUX_GPIO185__FUNC_F2W_CK (MTK_PIN_NO(185) | 1)
+#define PINMUX_GPIO185__FUNC_MRG_DI (MTK_PIN_NO(185) | 2)
+#define PINMUX_GPIO185__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(185) | 3)
+#define PINMUX_GPIO185__FUNC_PCM0_DI (MTK_PIN_NO(185) | 4)
+
+#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define PINMUX_GPIO186__FUNC_WB_RSTB (MTK_PIN_NO(186) | 1)
+#define PINMUX_GPIO186__FUNC_URXD3 (MTK_PIN_NO(186) | 4)
+#define PINMUX_GPIO186__FUNC_UTXD3 (MTK_PIN_NO(186) | 5)
+
+#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define PINMUX_GPIO187__FUNC_WB_SCLK (MTK_PIN_NO(187) | 1)
+#define PINMUX_GPIO187__FUNC_MRG_DO (MTK_PIN_NO(187) | 2)
+#define PINMUX_GPIO187__FUNC_PCM0_DO (MTK_PIN_NO(187) | 4)
+
+#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define PINMUX_GPIO188__FUNC_WB_SDATA (MTK_PIN_NO(188) | 1)
+#define PINMUX_GPIO188__FUNC_MRG_SYNC (MTK_PIN_NO(188) | 2)
+#define PINMUX_GPIO188__FUNC_PCM0_SYNC (MTK_PIN_NO(188) | 4)
+
+#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define PINMUX_GPIO189__FUNC_WB_SEN (MTK_PIN_NO(189) | 1)
+#define PINMUX_GPIO189__FUNC_UTXD3 (MTK_PIN_NO(189) | 4)
+#define PINMUX_GPIO189__FUNC_URXD3 (MTK_PIN_NO(189) | 5)
+
+#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define PINMUX_GPIO190__FUNC_GPS_RXQN (MTK_PIN_NO(190) | 1)
+
+#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define PINMUX_GPIO191__FUNC_GPS_RXQP (MTK_PIN_NO(191) | 1)
+
+#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define PINMUX_GPIO192__FUNC_GPS_RXIN (MTK_PIN_NO(192) | 1)
+
+#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define PINMUX_GPIO193__FUNC_GPS_RXIP (MTK_PIN_NO(193) | 1)
+
+#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define PINMUX_GPIO194__FUNC_WB_RXQN (MTK_PIN_NO(194) | 1)
+
+#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define PINMUX_GPIO195__FUNC_WB_RXQP (MTK_PIN_NO(195) | 1)
+
+#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
+#define PINMUX_GPIO196__FUNC_WB_RXIN (MTK_PIN_NO(196) | 1)
+
+#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)
+#define PINMUX_GPIO197__FUNC_WB_RXIP (MTK_PIN_NO(197) | 1)
+
+#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)
+#define PINMUX_GPIO198__FUNC_MSDC2_CMD (MTK_PIN_NO(198) | 1)
+#define PINMUX_GPIO198__FUNC_SDA1 (MTK_PIN_NO(198) | 2)
+#define PINMUX_GPIO198__FUNC_C2K_UART0_RXD (MTK_PIN_NO(198) | 3)
+#define PINMUX_GPIO198__FUNC_C2K_TMS (MTK_PIN_NO(198) | 4)
+#define PINMUX_GPIO198__FUNC_ANT_SEL6 (MTK_PIN_NO(198) | 5)
+#define PINMUX_GPIO198__FUNC_DM_OTMS (MTK_PIN_NO(198) | 7)
+
+#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define PINMUX_GPIO199__FUNC_MSDC2_CLK (MTK_PIN_NO(199) | 1)
+#define PINMUX_GPIO199__FUNC_SCL1 (MTK_PIN_NO(199) | 2)
+#define PINMUX_GPIO199__FUNC_C2K_UART0_TXD (MTK_PIN_NO(199) | 3)
+#define PINMUX_GPIO199__FUNC_C2K_TCK (MTK_PIN_NO(199) | 4)
+#define PINMUX_GPIO199__FUNC_ANT_SEL7 (MTK_PIN_NO(199) | 5)
+#define PINMUX_GPIO199__FUNC_TDD_TXD (MTK_PIN_NO(199) | 6)
+#define PINMUX_GPIO199__FUNC_DM_OTCK (MTK_PIN_NO(199) | 7)
+
+#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define PINMUX_GPIO200__FUNC_MSDC2_DAT0 (MTK_PIN_NO(200) | 1)
+#define PINMUX_GPIO200__FUNC_ANT_SEL6 (MTK_PIN_NO(200) | 2)
+#define PINMUX_GPIO200__FUNC_GPS_FRAME_SYNC (MTK_PIN_NO(200) | 3)
+#define PINMUX_GPIO200__FUNC_C2K_TDI (MTK_PIN_NO(200) | 4)
+#define PINMUX_GPIO200__FUNC_UTXD0 (MTK_PIN_NO(200) | 5)
+#define PINMUX_GPIO200__FUNC_DM_OTDI (MTK_PIN_NO(200) | 7)
+
+#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define PINMUX_GPIO201__FUNC_MSDC2_DAT1 (MTK_PIN_NO(201) | 1)
+#define PINMUX_GPIO201__FUNC_ANT_SEL3 (MTK_PIN_NO(201) | 2)
+#define PINMUX_GPIO201__FUNC_PWM0 (MTK_PIN_NO(201) | 3)
+#define PINMUX_GPIO201__FUNC_C2K_TDO (MTK_PIN_NO(201) | 4)
+#define PINMUX_GPIO201__FUNC_URXD0 (MTK_PIN_NO(201) | 5)
+#define PINMUX_GPIO201__FUNC_DM_OTDO (MTK_PIN_NO(201) | 7)
+
+#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define PINMUX_GPIO202__FUNC_MSDC2_DAT2 (MTK_PIN_NO(202) | 1)
+#define PINMUX_GPIO202__FUNC_ANT_SEL4 (MTK_PIN_NO(202) | 2)
+#define PINMUX_GPIO202__FUNC_SDA2 (MTK_PIN_NO(202) | 3)
+#define PINMUX_GPIO202__FUNC_C2K_NTRST (MTK_PIN_NO(202) | 4)
+#define PINMUX_GPIO202__FUNC_UTXD1 (MTK_PIN_NO(202) | 5)
+#define PINMUX_GPIO202__FUNC_KCOL3 (MTK_PIN_NO(202) | 6)
+#define PINMUX_GPIO202__FUNC_DM_JTINTP (MTK_PIN_NO(202) | 7)
+
+#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define PINMUX_GPIO203__FUNC_MSDC2_DAT3 (MTK_PIN_NO(203) | 1)
+#define PINMUX_GPIO203__FUNC_ANT_SEL5 (MTK_PIN_NO(203) | 2)
+#define PINMUX_GPIO203__FUNC_SCL2 (MTK_PIN_NO(203) | 3)
+#define PINMUX_GPIO203__FUNC_C2K_RTCK (MTK_PIN_NO(203) | 4)
+#define PINMUX_GPIO203__FUNC_URXD1 (MTK_PIN_NO(203) | 5)
+#define PINMUX_GPIO203__FUNC_KCOL6 (MTK_PIN_NO(203) | 6)
+
+#endif /* __DT_BINDINGS_PINCTRL_MEDIATEK_MT6735_PINFUNC_H__ */
--
2.54.0
^ permalink raw reply related
* [PATCH v8 4/6] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Document MT6765 pin controller
From: Yassine Oudjana @ 2026-05-30 14:57 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng
Cc: Yassine Oudjana, linux-mediatek, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260530145800.1029920-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
The MT6765 pin controller has had a driver for a while, but DT
bindings were never documented for it.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../pinctrl/mediatek,mt6779-pinctrl.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
index 2124804c8863..1f65f0fd41bd 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -18,6 +18,7 @@ description:
properties:
compatible:
enum:
+ - mediatek,mt6765-pinctrl
- mediatek,mt6779-pinctrl
- mediatek,mt6795-pinctrl
- mediatek,mt6797-pinctrl
@@ -61,6 +62,41 @@ required:
allOf:
- $ref: pinctrl.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt6765-pinctrl
+ then:
+ properties:
+ reg:
+ minItems: 9
+ maxItems: 9
+
+ reg-names:
+ items:
+ - const: iocfg0
+ - const: iocfg1
+ - const: iocfg2
+ - const: iocfg3
+ - const: iocfg4
+ - const: iocfg5
+ - const: iocfg6
+ - const: iocfg7
+ - const: eint
+
+ interrupts:
+ items:
+ - description: EINT interrupt
+
+ patternProperties:
+ '-pins$':
+ patternProperties:
+ '^pins':
+ properties:
+ drive-strength:
+ enum: [1, 2, 4, 16]
+
- if:
properties:
compatible:
--
2.54.0
^ permalink raw reply related
* [PATCH v8 3/6] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6795
From: Yassine Oudjana @ 2026-05-30 14:57 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng
Cc: Yassine Oudjana, linux-mediatek, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260530145800.1029920-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Combine MT6795 pin controller document into MT6779 one. In the
process, amend the example with comments and additional pinctrl
nodes from the MT6795 example, replace the current interrupts
property description with the one from the MT6795 document since
it makes more sense and define its items using conditionals
as they now vary between variants. Also use conditionals to define
valid values for the drive-strength property as well as items of
the interrupts property for each variant since they are different
on MT6795.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../pinctrl/mediatek,mt6779-pinctrl.yaml | 67 ++++-
.../pinctrl/mediatek,mt6795-pinctrl.yaml | 228 ------------------
2 files changed, 65 insertions(+), 230 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
index 4dc9504e24ad..2124804c8863 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -8,6 +8,7 @@ title: MediaTek MT6779 Pin Controller
maintainers:
- Andy Teng <andy.teng@mediatek.com>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Sean Wang <sean.wang@kernel.org>
description:
@@ -18,6 +19,7 @@ properties:
compatible:
enum:
- mediatek,mt6779-pinctrl
+ - mediatek,mt6795-pinctrl
- mediatek,mt6797-pinctrl
reg:
@@ -81,6 +83,45 @@ allOf:
- const: iocfg_lt
- const: iocfg_tl
- const: eint
+
+ patternProperties:
+ '-pins$':
+ patternProperties:
+ '^pins':
+ properties:
+ drive-strength:
+ enum: [2, 4, 8, 12, 16]
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt6795-pinctrl
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: base
+ - const: eint
+
+ interrupts:
+ minItems: 1
+ items:
+ - description: EINT interrupt
+ - description: EINT event_b interrupt
+
+ patternProperties:
+ '-pins$':
+ patternProperties:
+ '^pins':
+ properties:
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
- if:
properties:
compatible:
@@ -99,6 +140,15 @@ allOf:
- const: iocfgb
- const: iocfgr
- const: iocfgt
+
+ patternProperties:
+ '-pins$':
+ patternProperties:
+ '^pins':
+ properties:
+ drive-strength:
+ enum: [2, 4, 8, 12, 16]
+
- if:
properties:
reg-names:
@@ -170,8 +220,7 @@ patternProperties:
input-schmitt-disable: true
- drive-strength:
- enum: [2, 4, 8, 12, 16]
+ drive-strength: true
slew-rate:
enum: [0, 1]
@@ -263,5 +312,19 @@ examples:
mediatek,pull-up-adv = <0>;
};
};
+
+ /* GPIO0 set as multifunction GPIO0 */
+ gpio-pins {
+ pins {
+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
+ };
+ };
+
+ /* GPIO52 set as multifunction SDA0 */
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO52__FUNC_SDA0>;
+ };
+ };
};
};
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
deleted file mode 100644
index 68e91c05f122..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
+++ /dev/null
@@ -1,228 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek MT6795 Pin Controller
-
-maintainers:
- - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- - Sean Wang <sean.wang@kernel.org>
-
-description:
- The MediaTek's MT6795 Pin controller is used to control SoC pins.
-
-properties:
- compatible:
- const: mediatek,mt6795-pinctrl
-
- gpio-controller: true
-
- '#gpio-cells':
- description:
- Number of cells in GPIO specifier. Since the generic GPIO binding is used,
- the amount of cells must be specified as 2. See the below mentioned gpio
- binding representation for description of particular cells.
- const: 2
-
- gpio-ranges:
- description: GPIO valid number range.
- maxItems: 1
-
- reg:
- description:
- Physical address base for GPIO base and eint registers.
- minItems: 2
-
- reg-names:
- items:
- - const: base
- - const: eint
-
- interrupt-controller: true
-
- '#interrupt-cells':
- const: 2
-
- interrupts:
- description: Interrupt outputs to the system interrupt controller (sysirq).
- minItems: 1
- items:
- - description: EINT interrupt
- - description: EINT event_b interrupt
-
-# PIN CONFIGURATION NODES
-patternProperties:
- '-pins$':
- type: object
- additionalProperties: false
- patternProperties:
- '^pins':
- type: object
- additionalProperties: false
- description: |
- A pinctrl node should contain at least one subnodes representing the
- pinctrl groups available on the machine. Each subnode will list the
- pins it needs, and how they should be configured, with regard to muxer
- configuration, pullups, drive strength, input enable/disable and input
- schmitt.
- An example of using macro:
- pincontroller {
- /* GPIO0 set as multifunction GPIO0 */
- gpio-pins {
- pins {
- pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
- }
- };
- /* GPIO45 set as multifunction SDA0 */
- i2c0-pins {
- pins {
- pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
- }
- };
- };
- $ref: pinmux-node.yaml
-
- properties:
- pinmux:
- description:
- Integer array, represents gpio pin number and mux setting.
- Supported pin number and mux varies for different SoCs, and are
- defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
-
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
-
- bias-pull-down:
- oneOf:
- - type: boolean
- - enum: [100, 101, 102, 103]
- description: mt6795 pull down PUPD/R0/R1 type define value.
- description:
- For normal pull down type, it is not necessary to specify R1R0
- values; When pull down type is PUPD/R0/R1, adding R1R0 defines
- will set different resistance values.
-
- bias-pull-up:
- oneOf:
- - type: boolean
- - enum: [100, 101, 102, 103]
- description: mt6795 pull up PUPD/R0/R1 type define value.
- description:
- For normal pull up type, it is not necessary to specify R1R0
- values; When pull up type is PUPD/R0/R1, adding R1R0 defines will
- set different resistance values.
-
- bias-disable: true
-
- output-high: true
-
- output-low: true
-
- input-enable: true
-
- input-disable: true
-
- input-schmitt-enable: true
-
- input-schmitt-disable: true
-
- mediatek,pull-up-adv:
- description: |
- Pull up settings for 2 pull resistors, R0 and R1. User can
- configure those special pins. Valid arguments are described as
- below:
- 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
- 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
- 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
- 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 3]
-
- mediatek,pull-down-adv:
- description: |
- Pull down settings for 2 pull resistors, R0 and R1. User can
- configure those special pins. Valid arguments are described as
- below:
- 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
- 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
- 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
- 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 3]
-
- required:
- - pinmux
-
-allOf:
- - $ref: pinctrl.yaml#
-
-required:
- - compatible
- - reg
- - reg-names
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
-
- pio: pinctrl@10005000 {
- compatible = "mediatek,mt6795-pinctrl";
- reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
- reg-names = "base", "eint";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pio 0 0 196>;
- interrupt-controller;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
-
- i2c0-pins {
- pins-sda-scl {
- pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
- <PINMUX_GPIO46__FUNC_SCL0>;
- };
- };
-
- mmc0-pins {
- pins-cmd-dat {
- pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
- <PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
- <PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
- <PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
- <PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
- <PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
- <PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
- <PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
- <PINMUX_GPIO162__FUNC_MSDC0_CMD>;
- input-enable;
- bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
- };
-
- pins-clk {
- pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
- bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
- };
-
- pins-rst {
- pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
- bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
- };
- };
- };
- };
--
2.54.0
^ permalink raw reply related
* [PATCH v8 2/6] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Improve pinctrl subnode and property descriptions
From: Yassine Oudjana @ 2026-05-30 14:57 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng
Cc: Yassine Oudjana, linux-mediatek, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260530145800.1029920-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
Change "subnodes" to "subnode" in subnode description for better
grammatical accuracy, capitalize pinmux description, wrap all descriptions
at 80 characters, and remove literal style indicators from descriptions
that don't need their new lines preserved.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
index 0dcbca5ca8f9..4dc9504e24ad 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -119,11 +119,11 @@ patternProperties:
'^pins':
type: object
description:
- A pinctrl node should contain at least one subnodes representing the
+ A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
- pins it needs, and how they should be configured, with regard to muxer
- configuration, pullups, drive strength, input enable/disable and input
- schmitt.
+ pins it needs, and how they should be configured, with regard to
+ muxer configuration, pullups, drive strength, input enable/disable
+ and input schmitt.
allOf:
- $ref: pinmux-node.yaml
- $ref: pincfg-node.yaml
@@ -133,7 +133,8 @@ patternProperties:
description:
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
- defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
+ defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
+ directly.
bias-disable: true
@@ -142,7 +143,7 @@ patternProperties:
- type: boolean
- enum: [100, 101, 102, 103]
description: Pull up PUPD/R0/R1 type define value.
- description: |
+ description:
For normal pull up type, it is not necessary to specify R1R0
values; When pull up type is PUPD/R0/R1, adding R1R0 defines
will set different resistance values.
@@ -152,7 +153,7 @@ patternProperties:
- type: boolean
- enum: [100, 101, 102, 103]
description: Pull down PUPD/R0/R1 type define value.
- description: |
+ description:
For normal pull down type, it is not necessary to specify R1R0
values; When pull down type is PUPD/R0/R1, adding R1R0 defines
will set different resistance values.
--
2.54.0
^ permalink raw reply related
* [PATCH v8 1/6] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Pull pinctrl node changes from MT6795 document
From: Yassine Oudjana @ 2026-05-30 14:57 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng
Cc: Yassine Oudjana, linux-mediatek, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260530145800.1029920-1-y.oudjana@protonmail.com>
From: Yassine Oudjana <y.oudjana@protonmail.com>
mediatek,pinctrl-mt6795.yaml has different node name patterns which match
bindings of other MediaTek pin controllers, ref for pinmux-node.yaml which
has a description of the pinmux property, as well as some additional
descriptions for some pin configuration properties. Pull those changes
into mediatek,mt6779-pinctrl.yaml and adjust the example DTS to match in
preparation to combine the MT6795 document into it.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../pinctrl/mediatek,mt6779-pinctrl.yaml | 38 ++++++++++++++-----
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
index f4bab7a132d3..0dcbca5ca8f9 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -111,12 +111,12 @@ allOf:
- "#interrupt-cells"
patternProperties:
- '-[0-9]*$':
+ '-pins$':
type: object
additionalProperties: false
patternProperties:
- '-pins*$':
+ '^pins':
type: object
description:
A pinctrl node should contain at least one subnodes representing the
@@ -124,7 +124,9 @@ patternProperties:
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ allOf:
+ - $ref: pinmux-node.yaml
+ - $ref: pincfg-node.yaml
properties:
pinmux:
@@ -135,9 +137,25 @@ patternProperties:
bias-disable: true
- bias-pull-up: true
-
- bias-pull-down: true
+ bias-pull-up:
+ oneOf:
+ - type: boolean
+ - enum: [100, 101, 102, 103]
+ description: Pull up PUPD/R0/R1 type define value.
+ description: |
+ For normal pull up type, it is not necessary to specify R1R0
+ values; When pull up type is PUPD/R0/R1, adding R1R0 defines
+ will set different resistance values.
+
+ bias-pull-down:
+ oneOf:
+ - type: boolean
+ - enum: [100, 101, 102, 103]
+ description: Pull down PUPD/R0/R1 type define value.
+ description: |
+ For normal pull down type, it is not necessary to specify R1R0
+ values; When pull down type is PUPD/R0/R1, adding R1R0 defines
+ will set different resistance values.
input-enable: true
@@ -221,8 +239,8 @@ examples:
#interrupt-cells = <2>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
- mmc0_pins_default: mmc0-0 {
- cmd-dat-pins {
+ mmc0_pins_default: mmc0-pins {
+ pins-cmd-dat {
pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
@@ -235,11 +253,11 @@ examples:
input-enable;
mediatek,pull-up-adv = <1>;
};
- clk-pins {
+ pins-clk {
pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
mediatek,pull-down-adv = <2>;
};
- rst-pins {
+ pins-rst {
pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
mediatek,pull-up-adv = <0>;
};
--
2.54.0
^ permalink raw reply related
* [PATCH v8 0/6] MediaTek pinctrl DT binding cleanup and MT6735 pinctrl support
From: Yassine Oudjana @ 2026-05-30 14:57 UTC (permalink / raw)
To: Sean Wang, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng
Cc: Yassine Oudjana, linux-mediatek, linux-gpio, devicetree,
linux-kernel, linux-arm-kernel
From: Yassine Oudjana <y.oudjana@protonmail.com>
These patches are part of a larger effort to support the MT6735 SoC family in
mainline Linux. More patches (unsent or sent and pending review or revision) can
be found here[1].
This series adds a driver for the pin controller found on the MediaTek MT6735
and MT6735M SoCs. The two differ in the last 6 physical pins, which are used
for MSDC2 on MT6735 but don't exist on MT6735M (since MSDC2 doesn't exist on it
to begin with). In preparation to document DT bindings for this pin controller,
the existing documents for MT67xx SoCs are combined into one in order to
eliminate duplicate property definitions and standardize pin configuration node
names. Necessary cleanup is done along the way.
[1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging
Changes since v7:
- Wrap &mtk_paris_pinctrl_pm_ops with pm_sleep_ptr to fix build error reported
by kernel test robot.
Changes since v6:
- Mention changing MT6797 DT in 1st patch commit message.
- Squash MT6735 DT binding patches.
- Add debounce time to eint_hw struct. MT6735 supports the same debounce
times as MT6765 so reuse debounce_time_mt6765.
Changes since v5:
- Revise and fix all register bits for all group register types (IES, SMT,
RDSEL, TDSEL, PUPD_R0_R1, PULLEN and PULLSEL).
- Add pull_type array.
- Use proper getters/setters for bias and drive.
- Add minItems for MT6795 interrupts.
Changes since v4:
- Remove patches that were applied previously.
- Define interrupts items for each variant (bringing back maxItems: 1 to the top
level definition then adding maxItems: 2 under the MT6795 condition causes a
dt_binding_check error for some reason)
- Move example changes to the patch they belong to
- Don't unnecessarily move the allOf block.
Changes since v3:
- Improve interrupts description to make clear what sysirq means.
- Set drive-strength constraints per variant.
- Set maxItems for reg in MT6795.
- Add blank lines between conditionals.
- Add ref for both pinmux-node.yaml and pincfg-node.yaml.
- Make pinctrl subnode-related changes in separate patch.
- Fix up some pinctrl subnode property descriptions.
- Add interrupts items descriptions to MT6765 and MT6735.Changes since v3:
- Improve interrupts description to make clear what sysirq means.
- Set drive-strength constraints per variant.
- Set maxItems for reg in MT6795.
- Add blank lines between conditionals.
- Add ref for both pinmux-node.yaml and pincfg-node.yaml.
- Make pinctrl subnode-related changes in separate patch.
- Fix up some pinctrl subnode property descriptions.
- Add interrupts items descriptions to MT6765 and MT6735.
Changes since v2:
- Add interrupt descriptions.
- Change interrupts property item limits.
- Move pinmux examples from node description to example dts.
- Properly add myself as maintainer for MT6735 pinctrl driver and DT bindings
document.
- Remove tabs from a few defines in pinctrl-mt6735.c.
Changes since v1:
- Combine other documents into existing mediatek,mt6779-pinctrl.yaml
instead of creating a new document with wild card in its name.
- Split first patch into smaller patches focused on specific changes.
- Remove syscon compatible from MT6779 DT to avoid a check error.
- Fix interrupt count for MT6795.
Yassine Oudjana (6):
dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Pull pinctrl node
changes from MT6795 document
dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Improve pinctrl subnode
and property descriptions
dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6795
dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Document MT6765 pin
controller
dt-bindings: pinctrl: mediatek: Add bindings for MT6735 pin controller
pinctrl: mediatek: Add MT6735 pinctrl driver
.../pinctrl/mediatek,mt6779-pinctrl.yaml | 152 +-
.../pinctrl/mediatek,mt6795-pinctrl.yaml | 228 -
MAINTAINERS | 9 +
drivers/pinctrl/mediatek/Kconfig | 6 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt6735.c | 880 ++++
drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h | 3993 +++++++++++++++++
.../pinctrl/mediatek,mt6735-pinctrl.h | 1148 +++++
8 files changed, 6172 insertions(+), 245 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6735.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6735.h
create mode 100644 include/dt-bindings/pinctrl/mediatek,mt6735-pinctrl.h
--
2.54.0
^ permalink raw reply
* [PATCH 51/76] drm/mediatek: hdmi_v2: Switch to atomic_create_state
From: Maxime Ripard @ 2026-05-30 13:59 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Maarten Lankhorst,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: Dmitry Baryshkov, dri-devel, Maxime Ripard, Chun-Kuang Hu,
Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno,
linux-mediatek, linux-kernel, linux-arm-kernel
In-Reply-To: <20260530-drm-no-more-bridge-reset-v1-0-875d828d31bc@kernel.org>
The drm_bridge_funcs.atomic_reset callback and its
drm_atomic_helper_bridge_reset() helper are deprecated.
Switch to the atomic_create_state callback and its
drm_atomic_helper_bridge_create_state() counterpart.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
---
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
index 7bbf463056c9..d9316d30fd5f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
@@ -1324,11 +1324,11 @@ static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
.atomic_enable = mtk_hdmi_v2_bridge_enable,
.atomic_disable = mtk_hdmi_v2_bridge_disable,
.atomic_post_disable = mtk_hdmi_v2_bridge_post_disable,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
- .atomic_reset = drm_atomic_helper_bridge_reset,
+ .atomic_create_state = drm_atomic_helper_bridge_create_state,
.detect = mtk_hdmi_v2_bridge_detect,
.edid_read = mtk_hdmi_v2_bridge_edid_read,
.hpd_enable = mtk_hdmi_v2_hpd_enable,
.hpd_disable = mtk_hdmi_v2_hpd_disable,
.hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid,
--
2.54.0
^ permalink raw reply related
* [PATCH 49/76] drm/mediatek: dsi: Switch to atomic_create_state
From: Maxime Ripard @ 2026-05-30 13:59 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Maarten Lankhorst,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: Dmitry Baryshkov, dri-devel, Maxime Ripard, Chun-Kuang Hu,
Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno,
linux-mediatek, linux-kernel, linux-arm-kernel
In-Reply-To: <20260530-drm-no-more-bridge-reset-v1-0-875d828d31bc@kernel.org>
The drm_bridge_funcs.atomic_reset callback and its
drm_atomic_helper_bridge_reset() helper are deprecated.
Switch to the atomic_create_state callback and its
drm_atomic_helper_bridge_create_state() counterpart.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
---
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index eb325e68aa59..3f3f56eed3f9 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -892,11 +892,11 @@ static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
.atomic_disable = mtk_dsi_bridge_atomic_disable,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_enable = mtk_dsi_bridge_atomic_enable,
.atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
.atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
- .atomic_reset = drm_atomic_helper_bridge_reset,
+ .atomic_create_state = drm_atomic_helper_bridge_create_state,
.mode_valid = mtk_dsi_bridge_mode_valid,
.mode_set = mtk_dsi_bridge_mode_set,
};
void mtk_dsi_ddp_start(struct device *dev)
--
2.54.0
^ permalink raw reply related
* [PATCH 50/76] drm/mediatek: hdmi: Switch to atomic_create_state
From: Maxime Ripard @ 2026-05-30 13:59 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Maarten Lankhorst,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: Dmitry Baryshkov, dri-devel, Maxime Ripard, Chun-Kuang Hu,
Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno,
linux-mediatek, linux-kernel, linux-arm-kernel
In-Reply-To: <20260530-drm-no-more-bridge-reset-v1-0-875d828d31bc@kernel.org>
The drm_bridge_funcs.atomic_reset callback and its
drm_atomic_helper_bridge_reset() helper are deprecated.
Switch to the atomic_create_state callback and its
drm_atomic_helper_bridge_create_state() counterpart.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
---
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 38a7c7953874..738090a47176 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1070,11 +1070,11 @@ static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
.mode_valid = mtk_hdmi_bridge_mode_valid,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
- .atomic_reset = drm_atomic_helper_bridge_reset,
+ .atomic_create_state = drm_atomic_helper_bridge_create_state,
.attach = mtk_hdmi_bridge_attach,
.mode_fixup = mtk_hdmi_bridge_mode_fixup,
.atomic_disable = mtk_hdmi_bridge_atomic_disable,
.atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
.mode_set = mtk_hdmi_bridge_mode_set,
--
2.54.0
^ permalink raw reply related
* [PATCH 48/76] drm/mediatek: dpi: Switch to atomic_create_state
From: Maxime Ripard @ 2026-05-30 13:59 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Maarten Lankhorst,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: Dmitry Baryshkov, dri-devel, Maxime Ripard, Chun-Kuang Hu,
Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno,
linux-mediatek, linux-kernel, linux-arm-kernel
In-Reply-To: <20260530-drm-no-more-bridge-reset-v1-0-875d828d31bc@kernel.org>
The drm_bridge_funcs.atomic_reset callback and its
drm_atomic_helper_bridge_reset() helper are deprecated.
Switch to the atomic_create_state callback and its
drm_atomic_helper_bridge_create_state() counterpart.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
---
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index bb4b7e6f1e29..959c994eef24 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -987,11 +987,11 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.atomic_check = mtk_dpi_bridge_atomic_check,
.atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
.atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
- .atomic_reset = drm_atomic_helper_bridge_reset,
+ .atomic_create_state = drm_atomic_helper_bridge_create_state,
.debugfs_init = mtk_dpi_debugfs_init,
};
static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = {
.destroy = drm_encoder_cleanup,
--
2.54.0
^ permalink raw reply related
* [PATCH 47/76] drm/mediatek: dp: Switch to atomic_create_state
From: Maxime Ripard @ 2026-05-30 13:59 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Maarten Lankhorst,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: Dmitry Baryshkov, dri-devel, Maxime Ripard, Chun-Kuang Hu,
Philipp Zabel, Matthias Brugger, AngeloGioacchino Del Regno,
linux-mediatek, linux-kernel, linux-arm-kernel
In-Reply-To: <20260530-drm-no-more-bridge-reset-v1-0-875d828d31bc@kernel.org>
The drm_bridge_funcs.atomic_reset callback and its
drm_atomic_helper_bridge_reset() helper are deprecated.
Switch to the atomic_create_state callback and its
drm_atomic_helper_bridge_create_state() counterpart.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
---
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Matthias Brugger <matthias.bgg@gmail.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/gpu/drm/mediatek/mtk_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index eefbc7e0f9c8..f656b85b8421 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -2576,11 +2576,11 @@ static const struct drm_bridge_funcs mtk_dp_bridge_funcs = {
.atomic_check = mtk_dp_bridge_atomic_check,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
.atomic_get_output_bus_fmts = mtk_dp_bridge_atomic_get_output_bus_fmts,
.atomic_get_input_bus_fmts = mtk_dp_bridge_atomic_get_input_bus_fmts,
- .atomic_reset = drm_atomic_helper_bridge_reset,
+ .atomic_create_state = drm_atomic_helper_bridge_create_state,
.attach = mtk_dp_bridge_attach,
.detach = mtk_dp_bridge_detach,
.atomic_enable = mtk_dp_bridge_atomic_enable,
.atomic_disable = mtk_dp_bridge_atomic_disable,
.mode_valid = mtk_dp_bridge_mode_valid,
--
2.54.0
^ permalink raw reply related
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