* [PATCH v2] [net] net: airoha: fix foe_check_time allocation size
From: Wayen Yan @ 2026-06-16 11:52 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
foe_check_time is declared as u16 pointer but was allocated with
only ppe_num_entries bytes instead of ppe_num_entries * sizeof(u16).
When airoha_ppe_foe_verify_entry() is called with hash >= ppe_num_entries/2,
it writes beyond the allocated buffer, causing heap buffer overflow and
potential kernel crash.
Fixes: 6d5b601d52a2 ("net: airoha: ppe: Dynamically allocate foe_check_time array in airoha_ppe struct")
Signed-off-by: Wayen Yan <win847@gmail.com>
---
drivers/net/ethernet/airoha/airoha_ppe.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 5c9dff6bcc..8fb8ecf909 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -1578,7 +1578,8 @@ int airoha_ppe_init(struct airoha_eth *eth)
return -ENOMEM;
}
- ppe->foe_check_time = devm_kzalloc(eth->dev, ppe_num_entries,
+ ppe->foe_check_time = devm_kzalloc(eth->dev,
+ ppe_num_entries * sizeof(*ppe->foe_check_time),
GFP_KERNEL);
if (!ppe->foe_check_time)
return -ENOMEM;
--
2.51.0
^ permalink raw reply related
* [PATCH v10 2/2] scsi: ufs: core: Add support for static TX Equalization settings
From: Can Guo @ 2026-06-16 11:33 UTC (permalink / raw)
To: krzk, bvanassche, beanhuo, peter.wang, martin.petersen, mani
Cc: linux-scsi, Can Guo, Alim Akhtar, Avri Altman,
James E.J. Bottomley, Matthias Brugger,
AngeloGioacchino Del Regno, Nitin Rawat, Ram Kumar Dwivedi,
open list,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek
In-Reply-To: <20260616113348.1168248-1-can.guo@oss.qualcomm.com>
Parse board-specific static TX Equalization settings from Device Tree for
each HS gear and store them in hba->tx_eq_params.
Parse txeq-preshoot-g[1-6] and txeq-deemphasis-g[1-6] as per-lane tuples:
<Host_Lane0 Device_Lane0>, [<Host_Lane1 Device_Lane1>].
For HS-G6, parse optional tx-precode-enable-g6 using the same per-lane
Host/Device tuple format. If provided, it must contain values for all
active lanes, and each value must be 0 or 1.
Introduce from_dt in struct ufshcd_tx_eq_params to track whether TX EQ
values came from static Device Tree data.
When adaptive TX Equalization is used, these static settings are not final:
- If valid settings are retrieved from qTxEQGnSettings/wTxEQGnSettingsExt,
those retrieved settings override static Device Tree settings.
- If retrieval is not available/valid, TX EQTR runs and trained settings
override static Device Tree settings.
So static Device Tree settings are a fallback for cases where adaptive TX
Equalization is not enabled or not used. Adaptive TX Equalization remains
the primary path when enabled.
No behavior changes for platforms that do not provide these properties.
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Can Guo <can.guo@oss.qualcomm.com>
---
drivers/ufs/core/ufs-txeq.c | 15 ++-
drivers/ufs/host/ufshcd-pltfrm.c | 154 +++++++++++++++++++++++++++++++
include/ufs/ufshcd.h | 2 +
3 files changed, 170 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c
index 3a2fb5329d27..3c94b94dd7b7 100644
--- a/drivers/ufs/core/ufs-txeq.c
+++ b/drivers/ufs/core/ufs-txeq.c
@@ -1297,7 +1297,13 @@ int ufshcd_config_tx_eq_settings(struct ufs_hba *hba,
}
params = &hba->tx_eq_params[gear - 1];
- if (!params->is_valid || force_tx_eqtr) {
+ /*
+ * TX EQTR must run for the following cases:
+ * 1. TX EQ settings are invalid.
+ * 2. TX EQ settings are from Device Tree.
+ * 3. TX EQTR procedure is forced.
+ */
+ if (!params->is_valid || params->from_dt || force_tx_eqtr) {
int ret;
ret = ufshcd_tx_eqtr(hba, params, pwr_mode);
@@ -1310,6 +1316,8 @@ int ufshcd_config_tx_eq_settings(struct ufs_hba *hba,
/* Mark TX Equalization settings as valid */
params->is_valid = true;
params->is_trained = true;
+ /* TX EQTR succeeds, clear from_dt flag */
+ params->from_dt = false;
params->is_applied = false;
}
@@ -1495,6 +1503,11 @@ static void ufshcd_extract_tx_eq_settings_attrs(struct ufs_hba *hba, u8 gear)
}
params->is_valid = true;
+ /*
+ * Optimal TX EQ settings are retrieved from UFS device attributes,
+ * clear from_dt flag to avoid TX EQTR procedure.
+ */
+ params->from_dt = false;
}
void ufshcd_retrieve_tx_eq_settings(struct ufs_hba *hba)
diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
index c2dafb583cf5..5ac7afe75934 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.c
+++ b/drivers/ufs/host/ufshcd-pltfrm.c
@@ -210,6 +210,158 @@ static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
}
}
+static int ufshcd_parse_tx_precode_enable(struct ufs_hba *hba,
+ bool host_precode_en[UFS_MAX_LANES],
+ bool device_precode_en[UFS_MAX_LANES])
+{
+ const char *prop_name = "tx-precode-enable-g6";
+ u32 num_elems = 2 * hba->lanes_per_direction;
+ const u32 lpd = hba->lanes_per_direction;
+ u32 precode[UFS_MAX_LANES * 2];
+ struct device *dev = hba->dev;
+ int count, err, i;
+
+ count = of_property_count_u32_elems(dev->of_node, prop_name);
+ if (count == -EINVAL || count == -ENODATA)
+ return 0;
+
+ if (count < 0)
+ return count;
+
+ if (count != num_elems) {
+ dev_err(dev, "Property %s has invalid count (%d), expecting %u\n",
+ prop_name, count, num_elems);
+ return -EINVAL;
+ }
+
+ err = of_property_read_u32_array(dev->of_node, prop_name, precode, num_elems);
+ if (err) {
+ dev_err(dev, "Failed to read %s property, %d\n", prop_name, err);
+ return err;
+ }
+
+ for (i = 0; i < num_elems; i++) {
+ if (precode[i] > 1) {
+ dev_err(dev, "Invalid TX precode value (%u) in %s property\n",
+ precode[i], prop_name);
+ return -EINVAL;
+ }
+ }
+
+ for (i = 0; i < lpd; i++) {
+ host_precode_en[i] = precode[i * 2];
+ device_precode_en[i] = precode[i * 2 + 1];
+ }
+
+ return 0;
+}
+
+static int ufshcd_parse_tx_eq_value_array(struct ufs_hba *hba,
+ const char *prop_name,
+ const u32 max_value,
+ u32 values[UFS_MAX_LANES * 2])
+{
+ u32 num_elems = 2 * hba->lanes_per_direction;
+ struct device *dev = hba->dev;
+ int count, err, i;
+
+ count = of_property_count_u32_elems(dev->of_node, prop_name);
+ if (count < 0)
+ return count;
+
+ if (count != num_elems) {
+ dev_err(dev, "Property %s has invalid count (%d), expecting %u\n",
+ prop_name, count, num_elems);
+ return -EINVAL;
+ }
+
+ err = of_property_read_u32_array(dev->of_node, prop_name, values, num_elems);
+ if (err) {
+ dev_err(dev, "Failed to read %s property, %d\n", prop_name, err);
+ return err;
+ }
+
+ for (i = 0; i < num_elems; i++) {
+ if (values[i] >= max_value) {
+ dev_err(dev, "Invalid TX EQ value (%u) in %s property\n",
+ values[i], prop_name);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * ufshcd_parse_tx_eq_settings_for_gear - Parse static TX EQ DT settings for one gear
+ * @hba: per adapter instance
+ * @gear: target HS gear
+ *
+ * Reads the txeq-preshoot-gN, txeq-deemphasis-gN, and (for G6)
+ * tx-precode-enable-g6 device-tree properties.
+ * If all present values are valid, stores them as static TX Equalization
+ * settings for the given gear.
+ */
+static void ufshcd_parse_tx_eq_settings_for_gear(struct ufs_hba *hba, int gear)
+{
+ bool device_precode_en[UFS_MAX_LANES] = { false };
+ bool host_precode_en[UFS_MAX_LANES] = { false };
+ const u32 lpd = hba->lanes_per_direction;
+ struct ufshcd_tx_eq_params *params;
+ u32 deemphasis[UFS_MAX_LANES * 2];
+ u32 preshoot[UFS_MAX_LANES * 2];
+ char prop_name[MAX_PROP_SIZE];
+ int err, lane;
+
+ snprintf(prop_name, MAX_PROP_SIZE, "txeq-preshoot-g%d", gear);
+ err = ufshcd_parse_tx_eq_value_array(hba, prop_name, TX_HS_NUM_PRESHOOT, preshoot);
+ if (err)
+ return;
+
+ snprintf(prop_name, MAX_PROP_SIZE, "txeq-deemphasis-g%d", gear);
+ err = ufshcd_parse_tx_eq_value_array(hba, prop_name, TX_HS_NUM_DEEMPHASIS, deemphasis);
+ if (err)
+ return;
+
+ if (gear == UFS_HS_G6) {
+ err = ufshcd_parse_tx_precode_enable(hba, host_precode_en, device_precode_en);
+ if (err)
+ return;
+ }
+
+ params = &hba->tx_eq_params[gear - 1];
+ for (lane = 0; lane < lpd; lane++) {
+ params->host[lane].preshoot = preshoot[lane * 2];
+ params->host[lane].deemphasis = deemphasis[lane * 2];
+ params->host[lane].precode_en = host_precode_en[lane];
+
+ params->device[lane].preshoot = preshoot[lane * 2 + 1];
+ params->device[lane].deemphasis = deemphasis[lane * 2 + 1];
+ params->device[lane].precode_en = device_precode_en[lane];
+ }
+
+ params->is_valid = true;
+ params->from_dt = true;
+}
+
+static void ufshcd_parse_static_tx_eq_settings(struct ufs_hba *hba)
+{
+ const u32 lpd = hba->lanes_per_direction;
+ int gear;
+
+ if (!lpd)
+ return;
+
+ if (lpd > UFS_MAX_LANES) {
+ dev_warn(hba->dev, "lanes_per_direction (%u) exceeds UFS_MAX_LANES (%u)\n",
+ lpd, UFS_MAX_LANES);
+ return;
+ }
+
+ for (gear = UFS_HS_G1; gear <= UFS_HS_GEAR_MAX; gear++)
+ ufshcd_parse_tx_eq_settings_for_gear(hba, gear);
+}
+
/**
* ufshcd_parse_clock_min_max_freq - Parse MIN and MAX clocks freq
* @hba: per adapter instance
@@ -528,6 +680,8 @@ int ufshcd_pltfrm_init(struct platform_device *pdev,
ufshcd_init_lanes_per_dir(hba);
+ ufshcd_parse_static_tx_eq_settings(hba);
+
err = ufshcd_parse_operating_points(hba);
if (err) {
dev_err(dev, "%s: OPP parse failed %d\n", __func__, err);
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index f48d6416e299..0f87b081b2ff 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -359,6 +359,7 @@ struct ufshcd_tx_eqtr_record {
* @is_valid: True if parameter contains valid TX Equalization settings
* @is_applied: True if settings have been applied to UniPro of both sides
* @is_trained: True if parameters obtained from TX EQTR procedure
+ * @from_dt: True if settings are from Device Tree
*/
struct ufshcd_tx_eq_params {
struct ufshcd_tx_eq_settings host[UFS_MAX_LANES];
@@ -367,6 +368,7 @@ struct ufshcd_tx_eq_params {
bool is_valid;
bool is_applied;
bool is_trained;
+ bool from_dt;
};
/**
--
2.34.1
^ permalink raw reply related
* [PATCH v10 1/2] dt-bindings: ufs: Document static TX Equalization settings properties
From: Can Guo @ 2026-06-16 11:33 UTC (permalink / raw)
To: krzk, bvanassche, beanhuo, peter.wang, martin.petersen, mani
Cc: linux-scsi, Can Guo, Krzysztof Kozlowski, Alim Akhtar,
Avri Altman, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Ram Kumar Dwivedi,
Zhaoming Luo,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek,
moderated list:ARM/Mediatek SoC support:Keyword:mediatek
In-Reply-To: <20260616113348.1168248-1-can.guo@oss.qualcomm.com>
UFS v5.0/UFSHCI v5.0 adds HS-G6 support (46.6 Gbps/lane) via UniPro
v3.0 and M-PHY v6.0. These specs define TX Equalization for all
High-Speed Gears (not only HS-G6) to compensate channel loss and
improve signal integrity at high speed.
For HS-G6, M-PHY uses PAM4 1b1b line coding. Pre-Coding may also be
required depending on channel characteristics.
Document vendor-neutral properties in ufs-common.yaml:
- txeq-preshoot-g[1-6]
- txeq-deemphasis-g[1-6]
- tx-precode-enable-g6
Values are per-lane Host/Device tuples (2 values for x1, 4 values for
x2). PreShoot/DeEmphasis range from 0..7, and Precode is 0/1.
These are board-specific signal-integrity tuning values. They depend on
channel SI/PHY characterization and validation (host PHY, device PHY,
package, and board routing), and are determined by HW/PHY designers.
Although UFSHCI v5.0 supports TX Equalization Training via UniPro v3.0,
which allows host software to determine optimal TX Equalization at
runtime, static board-specific TX Equalization settings in the Device
Tree are still necessary because:
- TX Equalization Training is not supported for HS-G3 and below
- TX Equalization Training is disabled on some platforms
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Can Guo <can.guo@oss.qualcomm.com>
---
.../devicetree/bindings/ufs/ufs-common.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
index ed97f5682509..cc32e1189d50 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml
+++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml
@@ -105,6 +105,64 @@ properties:
Restricts the UFS controller to rate-a or rate-b for both TX and
RX directions.
+ tx-precode-enable-g6:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ items:
+ - items:
+ - description: Host_Lane0 precode
+ enum: [0, 1]
+ - description: Device_Lane0 precode
+ enum: [0, 1]
+ - items:
+ - description: Host_Lane1 precode
+ enum: [0, 1]
+ - description: Device_Lane1 precode
+ enum: [0, 1]
+ description:
+ Static TX Precode enable values for HS-G6 only.
+
+patternProperties:
+ "^txeq-preshoot-g[1-6]$":
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ items:
+ - items:
+ - description: Host_Lane0 Preshoot value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ - description: Device_Lane0 Preshoot value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ - items:
+ - description: Host_Lane1 Preshoot value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ - description: Device_Lane1 Preshoot value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ description: |
+ Static TX Equalization PreShoot settings for High Speed Gears. These
+ values are programmed to the corresponding UniPro PA layer attribute
+ PA_TxEQG[1-6]Setting. Each value selects a Pre-Shoot level as defined
+ by the MIPI M-PHY specification (TX_HS_PreShoot_Setting).
+
+ "^txeq-deemphasis-g[1-6]$":
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ items:
+ - items:
+ - description: Host_Lane0 DeEmphasis value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ - description: Device_Lane0 DeEmphasis value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ - items:
+ - description: Host_Lane1 DeEmphasis value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ - description: Device_Lane1 DeEmphasis value
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ description: |
+ Static TX Equalization DeEmphasis settings for High Speed Gears. These
+ values are programmed to the corresponding UniPro PA layer attribute
+ PA_TxEQG[1-6]Setting. Each value selects a De-Emphasis level as defined
+ by the MIPI M-PHY specification (TX_HS_DeEmphasis_Setting).
+
dependencies:
freq-table-hz: [ clocks ]
operating-points-v2: [ clocks, clock-names ]
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/3] Bluetooth: btmtksdio: call cancel_work_sync() outside of host lock scope
From: Sergey Senozhatsky @ 2026-06-16 11:12 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, Mark-yw Chen, Sean Wang
Cc: Tomasz Figa, linux-bluetooth, linux-kernel, linux-arm-kernel,
linux-mediatek, Sergey Senozhatsky, stable
In-Reply-To: <20260616111224.152140-1-senozhatsky@chromium.org>
cancel_work_sync() should be called outside of host lock scope
in order to avoid circular locking scenario:
CPU0 CPU1
close()/reset()
sdio_claim_host()
txrx_work
sdio_claim_host() // sleeps
cancel_work_sync() // sleeps
In addition, when txrx_work() runs concurrently with close()/reset()
it better not to re-enable interrupts by testing for BTMTKSDIO_FUNC_ENABLED
and not BTMTKSDIO_HW_RESET_ACTIVE before C_INT_EN_SET write. However,
btmtksdio_close() clears the BTMTKSDIO_FUNC_ENABLED too late (after
cancel_work_sync() call). Move BTMTKSDIO_FUNC_ENABLED bit-clear earlier
so that txrx_work can see concurrent close().
Fixes: 26270bc189ea4 ("Bluetooth: btmtksdio: move interrupt service to work")
Cc: stable@vger.kernel.org
Signed-off-by: Sergey Senozhatsky <senozhatsky@chromium.org>
---
drivers/bluetooth/btmtksdio.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/bluetooth/btmtksdio.c b/drivers/bluetooth/btmtksdio.c
index d8c8d2857527..207d04cc2282 100644
--- a/drivers/bluetooth/btmtksdio.c
+++ b/drivers/bluetooth/btmtksdio.c
@@ -625,7 +625,9 @@ static void btmtksdio_txrx_work(struct work_struct *work)
} while (int_status && time_is_after_jiffies(txrx_timeout));
/* Enable interrupt */
- if (bdev->func->irq_handler)
+ if (bdev->func->irq_handler &&
+ test_bit(BTMTKSDIO_FUNC_ENABLED, &bdev->tx_state) &&
+ !test_bit(BTMTKSDIO_HW_RESET_ACTIVE, &bdev->tx_state))
sdio_writel(bdev->func, C_INT_EN_SET, MTK_REG_CHLPCR, NULL);
sdio_release_host(bdev->func);
@@ -741,6 +743,8 @@ static int btmtksdio_close(struct hci_dev *hdev)
if (!test_bit(BTMTKSDIO_FUNC_ENABLED, &bdev->tx_state))
return 0;
+ clear_bit(BTMTKSDIO_FUNC_ENABLED, &bdev->tx_state);
+
sdio_claim_host(bdev->func);
/* Disable interrupt */
@@ -748,11 +752,12 @@ static int btmtksdio_close(struct hci_dev *hdev)
sdio_release_irq(bdev->func);
+ sdio_release_host(bdev->func);
cancel_work_sync(&bdev->txrx_work);
+ sdio_claim_host(bdev->func);
btmtksdio_fw_pmctrl(bdev);
- clear_bit(BTMTKSDIO_FUNC_ENABLED, &bdev->tx_state);
sdio_disable_func(bdev->func);
sdio_release_host(bdev->func);
@@ -1295,7 +1300,10 @@ static void btmtksdio_reset(struct hci_dev *hdev)
sdio_writel(bdev->func, C_INT_EN_CLR, MTK_REG_CHLPCR, NULL);
skb_queue_purge(&bdev->txq);
+
+ sdio_release_host(bdev->func);
cancel_work_sync(&bdev->txrx_work);
+ sdio_claim_host(bdev->func);
gpiod_set_value_cansleep(bdev->reset, 1);
msleep(100);
--
2.54.0.1136.gdb2ca164c4-goog
^ permalink raw reply related
* [PATCH v2 2/3] Bluetooth: btmtksdio: test for bug IO errors in btmtksdio_txrx_work()
From: Sergey Senozhatsky @ 2026-06-16 11:12 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, Mark-yw Chen, Sean Wang
Cc: Tomasz Figa, linux-bluetooth, linux-kernel, linux-arm-kernel,
linux-mediatek, Sergey Senozhatsky, stable
In-Reply-To: <20260616111224.152140-1-senozhatsky@chromium.org>
btmtksdio_txrx_work() loop termination condition checks for
int_status being non-zero, however, this evaluates to true
even when sdio_readl() encounters BUS I/O error (in which
case int_status is 0xffffffff). Break out of the loop if
sdio_readl() errors out.
Fixes: 26270bc189ea4 ("Bluetooth: btmtksdio: move interrupt service to work")
Cc: stable@vger.kernel.org
Signed-off-by: Sergey Senozhatsky <senozhatsky@chromium.org>
---
drivers/bluetooth/btmtksdio.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/bluetooth/btmtksdio.c b/drivers/bluetooth/btmtksdio.c
index c6f80c419e90..d8c8d2857527 100644
--- a/drivers/bluetooth/btmtksdio.c
+++ b/drivers/bluetooth/btmtksdio.c
@@ -574,7 +574,9 @@ static void btmtksdio_txrx_work(struct work_struct *work)
txrx_timeout = jiffies + 5 * HZ;
do {
- int_status = sdio_readl(bdev->func, MTK_REG_CHISR, NULL);
+ int_status = sdio_readl(bdev->func, MTK_REG_CHISR, &err);
+ if (err < 0 || int_status == 0xffffffff)
+ break;
/* Ack an interrupt as soon as possible before any operation on
* hardware.
--
2.54.0.1136.gdb2ca164c4-goog
^ permalink raw reply related
* [PATCH v2 1/3] Bluetooth: btmtksdio: correct btmtksdio_txrx_work() loop timeout check
From: Sergey Senozhatsky @ 2026-06-16 11:12 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, Mark-yw Chen, Sean Wang
Cc: Tomasz Figa, linux-bluetooth, linux-kernel, linux-arm-kernel,
linux-mediatek, Sergey Senozhatsky, stable
In-Reply-To: <20260616111224.152140-1-senozhatsky@chromium.org>
The btmtksdio_txrx_work() loop is expected to be terminated if running
for longer than 5*HZ. However the timeout check is reversed:
time_is_before_jiffies(old_jiffies + 5*HZ) evaluates to true when
old_jiffies + 5*HZ is in the past i.e. when a timeout has occurred.
Using OR with time_is_before_jiffies(txrx_timeout) means that:
- before the 5-second timeout: the condition is `int_status || false`,
so it loops as long as there are pending interrupts.
- after the 5-second timeout: the condition becomes `int_status || true`,
which is always true.
Fix loop termination condition to actually enforce a 5*HZ timeout.
Fixes: 26270bc189ea4 ("Bluetooth: btmtksdio: move interrupt service to work")
Cc: stable@vger.kernel.org
Signed-off-by: Sergey Senozhatsky <senozhatsky@chromium.org>
---
drivers/bluetooth/btmtksdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bluetooth/btmtksdio.c b/drivers/bluetooth/btmtksdio.c
index 5b0fab7b89b5..c6f80c419e90 100644
--- a/drivers/bluetooth/btmtksdio.c
+++ b/drivers/bluetooth/btmtksdio.c
@@ -620,7 +620,7 @@ static void btmtksdio_txrx_work(struct work_struct *work)
if (btmtksdio_rx_packet(bdev, rx_size) < 0)
bdev->hdev->stat.err_rx++;
}
- } while (int_status || time_is_before_jiffies(txrx_timeout));
+ } while (int_status && time_is_after_jiffies(txrx_timeout));
/* Enable interrupt */
if (bdev->func->irq_handler)
--
2.54.0.1136.gdb2ca164c4-goog
^ permalink raw reply related
* [PATCH v2 0/3] Bluetooth: btmtksdio: teardown fixes
From: Sergey Senozhatsky @ 2026-06-16 11:12 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, Mark-yw Chen, Sean Wang
Cc: Tomasz Figa, linux-bluetooth, linux-kernel, linux-arm-kernel,
linux-mediatek, Sergey Senozhatsky
This is v2 of teardown fixes.
We noticed a number of cases when btmtk close/teardown would hung:
INFO: task kworker/u17:0:189 blocked for more than 122 seconds.
__cancel_work_timer+0x3f4/0x460
cancel_work_sync+0x1c/0x2c
btmtksdio_flush+0x2c/0x40
hci_dev_open_sync+0x10c4/0x2190
[..]
There are several issues with the teardown (close/reset) code
in the driver. First, the btmtksdio_txrx_work() potentially
can spin forever (infinite loop). Second, close/flush can
deadlock when run concurrently with btmtksdio_txrx_work().
v1 -> v2:
- added two more patches (deadlock fix, interrupts re-enabling
enhancement)
Sergey Senozhatsky (3):
Bluetooth: btmtksdio: correct btmtksdio_txrx_work() loop timeout check
Bluetooth: btmtksdio: test for bug IO errors in btmtksdio_txrx_work()
Bluetooth: btmtksdio: call cancel_work_sync() outside of host lock
scope
drivers/bluetooth/btmtksdio.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
--
2.54.0.1136.gdb2ca164c4-goog
^ permalink raw reply
* [PATCH] net: airoha: Clean up RX queues in airoha_dev_stop
From: Wayen Yan @ 2026-06-16 10:50 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
When the last port is stopped, airoha_dev_stop() clears TX queues
but neglects to clean up RX queues. This can lead to:
- RX ring buffer descriptors remaining valid after device close
- Potential DMA synchronization issues on device reopen
- Risk of use-after-free if pages are freed while DMA is still active
Add cleanup loop for RX queues to mirror the TX queue cleanup,
ensuring symmetric resource management.
Fixes: 20bf7d07c956 ("net: airoha: add QDMA support for Airoha EN7581 Ethernet")
Signed-off-by: Wayen Yan <win847@gmail.com>
---
drivers/net/ethernet/airoha/airoha_eth.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 31cdb11cd7..9ca5bbf64d 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1771,6 +1771,13 @@ static int airoha_dev_stop(struct net_device *dev)
airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
}
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
+ if (!qdma->q_rx[i].ndesc)
+ continue;
+
+ airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]);
+ }
}
return 0;
--
2.51.0
^ permalink raw reply related
* [PATCH] net: airoha: Stop TX queues on error path in airoha_dev_open
From: Wayen Yan @ 2026-06-16 10:50 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
In airoha_dev_open(), if airoha_set_vip_for_gdm_port() fails after
netif_tx_start_all_queues() has been called, the TX queues remain
started while the device configuration is incomplete. This leaves
the device in an inconsistent state where packets could be
transmitted before the VIP/IFC port configuration is complete.
Add netif_tx_stop_all_queues() call on the error path to properly
roll back the TX queue state.
Fixes: 20bf7d07c956 ("net: airoha: add QDMA support for Airoha EN7581 Ethernet")
Signed-off-by: Wayen Yan <win847@gmail.com>
---
drivers/net/ethernet/airoha/airoha_eth.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 31cdb11cd7..cf9c366907 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1715,8 +1715,10 @@ static int airoha_dev_open(struct net_device *dev)
netif_tx_start_all_queues(dev);
err = airoha_set_vip_for_gdm_port(port, true);
- if (err)
+ if (err) {
+ netif_tx_stop_all_queues(dev);
return err;
+ }
if (netdev_uses_dsa(dev))
airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
--
2.51.0
^ permalink raw reply related
* [PATCH] net: airoha: Fix QoS counter configuration for Tx-fwd channels
From: Wayen Yan @ 2026-06-16 10:50 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
In airoha_qdma_init_qos_stats(), the Tx-fwd counter was incorrectly
using register index (i << 1) instead of ((i << 1) + 1). This caused
the Tx-fwd configuration to overwrite the Tx-cpu configuration for
each QoS channel, resulting in incorrect QoS statistics.
Fix by using the correct register index ((i << 1) + 1) for Tx-fwd
counter configuration.
Fixes: 20bf7d07c956 ("net: airoha: add QDMA support for Airoha EN7581 Ethernet")
Signed-off-by: Wayen Yan <win847@gmail.com>
---
drivers/net/ethernet/airoha/airoha_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 31cdb11cd7..329988a840 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1256,7 +1256,7 @@ static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma)
FIELD_PREP(CNTR_CHAN_MASK, i));
/* Tx-fwd transferred count */
airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0);
- airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
+ airoha_qdma_wr(qdma, REG_CNTR_CFG((i << 1) + 1),
CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
CNTR_ALL_DSCP_RING_EN_MASK |
FIELD_PREP(CNTR_SRC_MASK, 1) |
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v1] Bluetooth: btmtk: Add MT7928 support
From: Paul Menzel @ 2026-06-16 10:24 UTC (permalink / raw)
To: Chris Lu
Cc: Marcel Holtmann, Johan Hedberg, Luiz Von Dentz, Sean Wang,
Will Lee, SS Wu, Steve Lee, linux-bluetooth, linux-kernel,
linux-mediatek
In-Reply-To: <20260616030132.532184-1-chris.lu@mediatek.com>
Dear Chris,
Thank you for your patch.
Am 16.06.26 um 05:01 schrieb Chris Lu:
> Add support for MT7928 (device ID 0x7935) which requires additional
> firmware (CBMCU firmware) loading before Bluetooth firmware.
Please detail what CBMCU firmware is.
> Implement two-phase CBMCU firmware download: Phase 1 loads
> section with type 0x5 containing global descriptor,
> section maps and signature data; Phase 2 loads remaining
> firmware sections. Add retry mechanism for concurrent download
> protection.
What is type 0x5? How big is the firmware, and how long does it take?
> After CBMCU firmware loads successfully, the driver continues
> to load corresponding BT firmware based on device ID through
> fallthrough to case 0x7922/0x7925.
Please add the new log message to the commit message.
> Signed-off-by: Chris Lu <chris.lu@mediatek.com>
> ---
> drivers/bluetooth/btmtk.c | 342 +++++++++++++++++++++++++++++++++++++-
> drivers/bluetooth/btmtk.h | 3 +
> 2 files changed, 344 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/bluetooth/btmtk.c b/drivers/bluetooth/btmtk.c
> index 02a96342e964..a68c67d1df4b 100644
> --- a/drivers/bluetooth/btmtk.c
> +++ b/drivers/bluetooth/btmtk.c
> @@ -21,6 +21,7 @@
> #define MTK_FW_ROM_PATCH_SEC_MAP_SIZE 64
> #define MTK_SEC_MAP_COMMON_SIZE 12
> #define MTK_SEC_MAP_NEED_SEND_SIZE 52
> +#define MTK_SEC_MAP_LENGTH_SIZE 4
>
> /* It is for mt79xx iso data transmission setting */
> #define MTK_ISO_THRESHOLD 264
> @@ -120,6 +121,10 @@ void btmtk_fw_get_filename(char *buf, size_t size, u32 dev_id, u32 fw_ver,
> snprintf(buf, size,
> "mediatek/mt%04x/BT_RAM_CODE_MT%04x_1_%x_hdr.bin",
> dev_id & 0xffff, dev_id & 0xffff, (fw_ver & 0xff) + 1);
> + else if (dev_id == 0x7935)
> + snprintf(buf, size,
> + "mediatek/mt7928/BT_RAM_CODE_MT%04x_1_1_hdr.bin",
> + dev_id & 0xffff);
> else if (dev_id == 0x7961 && fw_flavor)
> snprintf(buf, size,
> "mediatek/BT_RAM_CODE_MT%04x_1a_%x_hdr.bin",
> @@ -734,6 +739,7 @@ static int btmtk_usb_hci_wmt_sync(struct hci_dev *hdev,
> status = BTMTK_WMT_ON_UNDONE;
> break;
> case BTMTK_WMT_PATCH_DWNLD:
> + case BTMTK_WMT_CBMCU_DWNLD:
> if (wmt_evt->whdr.flag == 2)
> status = BTMTK_WMT_PATCH_DONE;
> else if (wmt_evt->whdr.flag == 1)
> @@ -870,6 +876,329 @@ static u32 btmtk_usb_reset_done(struct hci_dev *hdev)
> return val & MTK_BT_RST_DONE;
> }
>
> +static int btmtk_cbmcu_patch_status(struct hci_dev *hdev,
> + wmt_cmd_sync_func_t wmt_cmd_sync,
> + u8 *patch_status)
> +{
> + struct btmtk_hci_wmt_params wmt_params;
> + int status, err, retry = 20;
> +
> + do {
> + wmt_params.op = BTMTK_WMT_CBMCU_DWNLD;
> + wmt_params.flag = 0xF0;
> + wmt_params.dlen = 0;
> + wmt_params.data = NULL;
> + wmt_params.status = &status;
> +
> + err = wmt_cmd_sync(hdev, &wmt_params);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to query CBMCU patch status (%d)", err);
> + return err;
> + }
> +
> + *patch_status = (u8)status;
> +
> + if (*patch_status == BTMTK_WMT_PATCH_PROGRESS) {
> + msleep(100);
> + retry--;
> + } else {
> + break;
> + }
> + } while (retry > 0);
> +
> + return 0;
> +}
> +
> +static int btmtk_query_cbmcu_section(struct hci_dev *hdev,
> + wmt_cmd_sync_func_t wmt_cmd_sync,
> + u8 cbmcu_type,
> + const u8 *section_map,
> + u32 cert_len)
> +{
> + struct btmtk_hci_wmt_params wmt_params;
> + u8 cmd[64];
> + int status, err;
> +
> + cmd[0] = 0;
> + cmd[1] = cbmcu_type;
> +
> + if (cbmcu_type == 0)
> + put_unaligned_le32(cert_len, &cmd[2]);
> + else
> + memcpy(&cmd[2], section_map, MTK_SEC_MAP_NEED_SEND_SIZE);
> +
> + wmt_params.op = BTMTK_WMT_CBMCU_DWNLD;
> + wmt_params.flag = 0;
> + wmt_params.dlen = cbmcu_type ?
> + MTK_SEC_MAP_NEED_SEND_SIZE + 2 :
> + MTK_SEC_MAP_LENGTH_SIZE + 2;
> + wmt_params.data = cmd;
> + wmt_params.status = &status;
> +
> + err = wmt_cmd_sync(hdev, &wmt_params);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to query CBMCU section (%d)", err);
> + return err;
> + }
> +
> + /* Query should return UNDONE status for successful section query */
> + if (status != BTMTK_WMT_PATCH_UNDONE) {
> + bt_dev_err(hdev, "CBMCU section query status error (%d)", status);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int btmtk_download_cbmcu_section(struct hci_dev *hdev,
> + wmt_cmd_sync_func_t wmt_cmd_sync,
> + const u8 *fw_data,
> + u32 dl_size)
> +{
> + struct btmtk_hci_wmt_params wmt_params;
> + u32 sent_len, total_size = dl_size;
> + int err;
> +
> + wmt_params.op = BTMTK_WMT_CBMCU_DWNLD;
> + wmt_params.status = NULL;
> +
> + while (dl_size > 0) {
> + sent_len = min_t(u32, 250, dl_size);
> +
> + if (dl_size == total_size)
> + wmt_params.flag = 1;
> + else if (dl_size == sent_len)
> + wmt_params.flag = 3;
> + else
> + wmt_params.flag = 2;
> +
> + wmt_params.dlen = sent_len;
> + wmt_params.data = fw_data;
> +
> + err = wmt_cmd_sync(hdev, &wmt_params);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to send CBMCU section data (%d)", err);
> + return err;
> + }
> +
> + dl_size -= sent_len;
> + fw_data += sent_len;
> + }
> +
> + return 0;
> +}
> +
> +static int btmtk_enable_cbmcu_patch(struct hci_dev *hdev,
> + wmt_cmd_sync_func_t wmt_cmd_sync)
> +{
> + struct btmtk_hci_wmt_params wmt_params;
> + int err;
> +
> + wmt_params.op = BTMTK_WMT_CBMCU_DWNLD;
> + wmt_params.flag = 0xF1;
> + wmt_params.dlen = 0;
> + wmt_params.data = NULL;
> + wmt_params.status = NULL;
> +
> + err = wmt_cmd_sync(hdev, &wmt_params);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to enable CBMCU patch (%d)", err);
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +static int btmtk_load_cbmcu_firmware(struct hci_dev *hdev,
> + const char *fwname,
> + wmt_cmd_sync_func_t wmt_cmd_sync)
> +{
> + struct btmtk_patch_header *hdr;
> + struct btmtk_global_desc *globaldesc;
> + struct btmtk_section_map *sectionmap;
> + const struct firmware *fw;
> + const u8 *fw_ptr;
> + u8 *cert_buf = NULL;
> + u32 section_num, section_offset, dl_size, cert_len;
> + int i, err;
> +
> + err = request_firmware(&fw, fwname, &hdev->dev);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to load CBMCU firmware file (%d)", err);
Please add fwname to the error message.
> + return err;
> + }
> +
> + if (fw->size < MTK_FW_ROM_PATCH_HEADER_SIZE + MTK_FW_ROM_PATCH_GD_SIZE) {
> + bt_dev_err(hdev, "CBMCU firmware too small (%zu bytes)", fw->size);
Please add the limit to the error message.
> + err = -EINVAL;
> + goto err_release_fw;
> + }
> +
> + fw_ptr = fw->data;
> + hdr = (struct btmtk_patch_header *)fw_ptr;
> + globaldesc = (struct btmtk_global_desc *)(fw_ptr + MTK_FW_ROM_PATCH_HEADER_SIZE);
> + section_num = le32_to_cpu(globaldesc->section_num);
> +
> + if (fw->size < MTK_FW_ROM_PATCH_HEADER_SIZE + MTK_FW_ROM_PATCH_GD_SIZE +
> + (size_t)MTK_FW_ROM_PATCH_SEC_MAP_SIZE * section_num) {
> + bt_dev_err(hdev, "CBMCU firmware truncated (section_num=%u)", section_num);
Please log the values from the if condition.
> + err = -EINVAL;
> + goto err_release_fw;
> + }
> +
> + bt_dev_info(hdev, "CBMCU Version: 0x%04x%04x, Build Time: %s",
> + le16_to_cpu(hdr->hwver), le16_to_cpu(hdr->swver), hdr->datetime);
> +
> + /* Phase 1: Download section type 0x5 */
Please define a macro or enum for 0x5.
> + for (i = 0; i < section_num; i++) {
> + sectionmap = (struct btmtk_section_map *)
> + (fw_ptr + MTK_FW_ROM_PATCH_HEADER_SIZE +
> + MTK_FW_ROM_PATCH_GD_SIZE +
> + MTK_FW_ROM_PATCH_SEC_MAP_SIZE * i);
> +
> + /* Only process type 0x5 section in Phase 1 */
> + if ((le32_to_cpu(sectionmap->sectype) & 0xFFFF) != 0x5)
> + continue;
> +
> + section_offset = le32_to_cpu(sectionmap->secoffset);
> + dl_size = le32_to_cpu(sectionmap->secsize);
> +
> + if (dl_size == 0)
> + continue;
> +
> + if (section_offset > fw->size ||
> + dl_size > fw->size - section_offset) {
> + bt_dev_err(hdev, "CBMCU Phase 1 section out of bounds");
> + err = -EINVAL;
> + goto err_release_fw;
> + }
> +
> + cert_len = MTK_FW_ROM_PATCH_GD_SIZE +
> + MTK_FW_ROM_PATCH_SEC_MAP_SIZE * section_num +
> + dl_size;
> +
> + /* Query cbmcu section */
> + err = btmtk_query_cbmcu_section(hdev, wmt_cmd_sync, 0, NULL,
> + cert_len);
> + if (err < 0)
> + goto err_release_fw;
> +
> + cert_buf = kmalloc(cert_len, GFP_KERNEL);
> + if (!cert_buf) {
> + err = -ENOMEM;
> + goto err_release_fw;
> + }
> +
> + /* Copy Global Descriptor + All Section Maps */
> + memcpy(cert_buf,
> + fw_ptr + MTK_FW_ROM_PATCH_HEADER_SIZE,
> + MTK_FW_ROM_PATCH_GD_SIZE + MTK_FW_ROM_PATCH_SEC_MAP_SIZE * section_num);
> +
> + /* Copy Phase 1 section data */
> + memcpy(cert_buf + MTK_FW_ROM_PATCH_GD_SIZE +
> + MTK_FW_ROM_PATCH_SEC_MAP_SIZE * section_num,
> + fw_ptr + section_offset,
> + dl_size);
> +
> + /* Download Phase 1 section */
> + err = btmtk_download_cbmcu_section(hdev, wmt_cmd_sync,
> + cert_buf, cert_len);
> + kfree(cert_buf);
> + cert_buf = NULL;
> +
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to download CBMCU Phase 1 section (%d)", err);
> + goto err_release_fw;
> + }
> +
> + break;
> + }
> +
> + /* Phase 2: Download other sections (type != 0x5) */
> + for (i = 0; i < section_num; i++) {
> + sectionmap = (struct btmtk_section_map *)
> + (fw_ptr + MTK_FW_ROM_PATCH_HEADER_SIZE +
> + MTK_FW_ROM_PATCH_GD_SIZE +
> + MTK_FW_ROM_PATCH_SEC_MAP_SIZE * i);
> +
> + /* Skip type 0x5 section in Phase 2 */
> + if ((le32_to_cpu(sectionmap->sectype) & 0xFFFF) == 0x5)
> + continue;
> +
> + section_offset = le32_to_cpu(sectionmap->secoffset);
> + dl_size = le32_to_cpu(sectionmap->bin_info_spec.dlsize);
> +
> + if (dl_size == 0)
> + continue;
> +
> + if (section_offset > fw->size ||
> + dl_size > fw->size - section_offset) {
> + bt_dev_err(hdev, "CBMCU Phase 2 section %d out of bounds", i);
> + err = -EINVAL;
> + goto err_release_fw;
> + }
> +
> + /* Query cbmcu section */
> + err = btmtk_query_cbmcu_section(hdev, wmt_cmd_sync, 1,
> + (u8 *)§ionmap->bin_info_spec,
> + 0);
> + if (err < 0)
> + goto err_release_fw;
> +
> + /* Download section data */
> + err = btmtk_download_cbmcu_section(hdev, wmt_cmd_sync,
> + fw_ptr + section_offset,
> + dl_size);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to download CBMCU section %d (%d)", i, err);
> + goto err_release_fw;
> + }
> + }
> +
> + /* Wait for firmware activation */
> + usleep_range(100000, 120000);
> +
> + bt_dev_info(hdev, "CBMCU firmware download completed");
> +
> +err_release_fw:
> + release_firmware(fw);
> + return err;
> +}
> +
> +static int btmtk_setup_cbmcu_firmware(struct hci_dev *hdev,
> + wmt_cmd_sync_func_t wmt_cmd_sync,
> + u32 dev_id)
> +{
> + char cbmcu_fwname[64];
> + u8 patch_status;
> + int err;
> +
> + err = btmtk_cbmcu_patch_status(hdev, wmt_cmd_sync, &patch_status);
> + if (err < 0)
> + return err;
> +
> + bt_dev_dbg(hdev, "CBMCU patch status: 0x%02x", patch_status);
> +
> + if (patch_status != BTMTK_WMT_PATCH_UNDONE)
> + return 0;
> +
> + snprintf(cbmcu_fwname, sizeof(cbmcu_fwname),
> + "mediatek/mt7928/CBMCU_CODE_MT%04x_1_1.bin",
> + dev_id & 0xffff);
> +
> + err = btmtk_load_cbmcu_firmware(hdev, cbmcu_fwname, wmt_cmd_sync);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to download CBMCU firmware (%d)", err);
> + return err;
> + }
> +
> + err = btmtk_enable_cbmcu_patch(hdev, wmt_cmd_sync);
> + if (err < 0)
> + return err;
> +
> + return 0;
> +}
> +
> int btmtk_usb_subsys_reset(struct hci_dev *hdev, u32 dev_id)
> {
> u32 val;
> @@ -894,7 +1223,7 @@ int btmtk_usb_subsys_reset(struct hci_dev *hdev, u32 dev_id)
> if (err < 0)
> return err;
> msleep(100);
> - } else if (dev_id == 0x7925 || dev_id == 0x6639) {
> + } else if (dev_id == 0x7925 || dev_id == 0x6639 || dev_id == 0x7935) {
> err = btmtk_usb_uhw_reg_read(hdev, MTK_BT_RESET_REG_CONNV3, &val);
> if (err < 0)
> return err;
> @@ -1379,6 +1708,15 @@ int btmtk_usb_setup(struct hci_dev *hdev)
> case 0x7668:
> fwname = FIRMWARE_MT7668;
> break;
> + case 0x7935:
> + /* Requires CBMCU firmware before BT firmware */
> + err = btmtk_setup_cbmcu_firmware(hdev, btmtk_usb_hci_wmt_sync,
> + dev_id);
> + if (err < 0) {
> + bt_dev_err(hdev, "Failed to set up CBMCU firmware (%d)", err);
> + return err;
> + }
> + fallthrough;
> case 0x7922:
> case 0x7925:
> /*
> @@ -1596,3 +1934,5 @@ MODULE_FIRMWARE(FIRMWARE_MT7922);
> MODULE_FIRMWARE(FIRMWARE_MT7961);
> MODULE_FIRMWARE(FIRMWARE_MT7925);
> MODULE_FIRMWARE(FIRMWARE_MT7927);
> +MODULE_FIRMWARE(FIRMWARE_MT7928);
> +MODULE_FIRMWARE(FIRMWARE_MT7928_CBMCU);
> diff --git a/drivers/bluetooth/btmtk.h b/drivers/bluetooth/btmtk.h
> index c83c24897c95..6d3bf6b74a1d 100644
> --- a/drivers/bluetooth/btmtk.h
> +++ b/drivers/bluetooth/btmtk.h
> @@ -9,6 +9,8 @@
> #define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin"
> #define FIRMWARE_MT7925 "mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin"
> #define FIRMWARE_MT7927 "mediatek/mt7927/BT_RAM_CODE_MT6639_2_1_hdr.bin"
> +#define FIRMWARE_MT7928 "mediatek/mt7928/BT_RAM_CODE_MT7935_1_1_hdr.bin"
> +#define FIRMWARE_MT7928_CBMCU "mediatek/mt7928/CBMCU_CODE_MT7935_1_1.bin"
>
> #define HCI_EV_WMT 0xe4
> #define HCI_WMT_MAX_EVENT_SIZE 64
> @@ -54,6 +56,7 @@ enum {
> BTMTK_WMT_RST = 0x7,
> BTMTK_WMT_REGISTER = 0x8,
> BTMTK_WMT_SEMAPHORE = 0x17,
> + BTMTK_WMT_CBMCU_DWNLD = 0x58,
> };
>
> enum {
Kind regards,
Paul
^ permalink raw reply
* [PATCH] net: airoha: fix foe_check_time allocation size
From: Wayen Yan @ 2026-06-16 9:49 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
foe_check_time is declared as u16 pointer but was allocated with
only ppe_num_entries bytes instead of ppe_num_entries * sizeof(u16).
When airoha_ppe_foe_verify_entry() is called with hash >= ppe_num_entries/2,
it writes beyond the allocated buffer, causing heap buffer overflow and
potential kernel crash.
Signed-off-by: Wayen Yan <win847@gmail.com>
---
drivers/net/ethernet/airoha/airoha_ppe.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 5c9dff6bcc..8fb8ecf909 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -1578,7 +1578,8 @@ int airoha_ppe_init(struct airoha_eth *eth)
return -ENOMEM;
}
- ppe->foe_check_time = devm_kzalloc(eth->dev, ppe_num_entries,
+ ppe->foe_check_time = devm_kzalloc(eth->dev,
+ ppe_num_entries * sizeof(*ppe->foe_check_time),
GFP_KERNEL);
if (!ppe->foe_check_time)
return -ENOMEM;
--
2.51.0
^ permalink raw reply related
* Re: [PATCH net-next v5 0/3] airoha: add the capability to configure GDM3/GDM4 as WAN/LAN on demand
From: Lorenzo Bianconi @ 2026-06-16 9:12 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Paolo Abeni,
linux-arm-kernel, linux-mediatek, netdev, Madhur Agrawal,
Alexander Lobakin
In-Reply-To: <20260615163713.665271a2@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 435 bytes --]
> On Thu, 11 Jun 2026 23:55:50 +0200 Lorenzo Bianconi wrote:
> > net: airoha: use int instead of atomic_t for qdma users counter
> > net: airoha: refactor QDMA start/stop into reusable helpers
> > net: airoha: defer GDM3/GDM4 WAN mode and GDM2 loopback to QoS offload
>
> only the first patch applies cleanly right now
ack, I will repost missing ones as soon as net-next is open again.
Regards,
Lorenzo
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH] media: mediatek: vcodec: fix use-after-free in decoder release path
From: Doruk Tan Ozturk @ 2026-06-16 7:56 UTC (permalink / raw)
To: tiffany.lin, andrew-ct.chen, yunfei.dong, mchehab, matthias.bgg,
angelogioacchino.delregno
Cc: hverkuil+cisco, linux-media, linux-mediatek, linux-arm-kernel,
linux-kernel, Doruk Tan Ozturk, stable
fops_vcodec_release() frees the decoder context with kfree(ctx) but
never cancels the per-context decode_work worker first. Although
v4l2_m2m_ctx_release() waits for any in-flight m2m job to finish, the
workqueue handler (mtk_vdec_worker) may still be running and accessing
the context after v4l2_m2m_job_finish() returns. Once kfree(ctx) runs,
that worker dereferences freed memory, resulting in a use-after-free.
Cancel the pending decode work with cancel_work_sync(&ctx->decode_work)
after the controls and m2m context are torn down and before kfree(ctx),
mirroring the fix already applied to the encoder release path in
commit 76e35091ffc7 ("media: mediatek: vcodec: fix use-after-free in
encoder release path").
decode_work is always initialised before release can run:
fops_vcodec_open() calls mtk_vcodec_dec_set_default_params() (its only
caller) unconditionally after a successful v4l2_m2m_ctx_init(), and that
function runs INIT_WORK(&ctx->decode_work, ...). A context can only reach
fops_vcodec_release() via an open() that returned 0, i.e. one that passed
that INIT_WORK. cancel_work_sync() on a properly initialised work_struct
is therefore always safe, even if the work was never queued. This is
unlike the 2023 msg_queue->core_work regression, where the work item
could be uninitialised at cancel time.
Fixes: 590577a4e525 ("[media] vcodec: mediatek: Add Mediatek V4L2 Video Decoder Driver")
Cc: stable@vger.kernel.org
Signed-off-by: Doruk Tan Ozturk <doruk@0sec.ai>
---
v2: reword the commit message to stay within 75 columns (no functional
change; checkpatch).
v1: https://lore.kernel.org/linux-media/20260615140526.52617-1-doruk@0sec.ai/
.../mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
index e936ed8dffbaf..30906b24c608a 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
@@ -313,6 +313,15 @@ static int fops_vcodec_release(struct file *file)
v4l2_fh_exit(&ctx->fh);
v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
+ /*
+ * Cancel any pending decode work before freeing the context.
+ * Although v4l2_m2m_ctx_release() waits for m2m job completion,
+ * the workqueue handler (mtk_vdec_worker) may still be accessing
+ * the context after v4l2_m2m_job_finish() returns. Without this,
+ * a use-after-free occurs when the worker accesses ctx after kfree.
+ */
+ cancel_work_sync(&ctx->decode_work);
+
mtk_vcodec_dbgfs_remove(dev, ctx->id);
spin_lock_irqsave(&dev->dev_ctx_lock, flags);
list_del_init(&ctx->list);
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 3/4] mfd: mt6397-core: add mt6323 AUXADC support
From: Andy Shevchenko @ 2026-06-16 7:18 UTC (permalink / raw)
To: Roman Vivchar
Cc: Lee Jones, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, linux-iio,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Ben Grisdale
In-Reply-To: <ycj3k-vV_tQv6u9OfCTP9G9kkeeE-_dbzg_oeHPXn2pb1oZe_Sa1BH6GUGuSd_gD6uPSJiTX7tz6MTlFcqGdWX-f3GMfyW2sLgAOCw6YeNE=@protonmail.com>
On Mon, Jun 15, 2026 at 11:10:20PM +0000, Roman Vivchar wrote:
> On Thursday, June 11th, 2026 at 7:37 PM, Lee Jones <lee@kernel.org> wrote:
> > On Tue, 02 Jun 2026, Roman Vivchar via B4 Relay wrote:
...
> > > + .of_compatible = "mediatek,mt6323-auxadc",
> >
> > [Severity: High]
> > Does adding this compatible string expose an unhandled edge case in the
> > auxadc driver?
> >
> > If this device is instantiated directly from a Device Tree without an MFD
> > parent (e.g., at the DT root), dev->parent could be the platform bus
> > (which has a NULL parent) or NULL itself.
> >
> > Looking at mt6323_auxadc_probe() in drivers/iio/adc/mt6323-auxadc.c:
> >
> > regmap = dev_get_regmap(dev->parent->parent, NULL);
> >
> > Could blindly dereferencing dev->parent->parent here, or passing a NULL
> > device to dev_get_regmap() (which calls devres_find()), result in a
> > kernel oops if probed as a root node?
>
> This is intended behavior, ADC always should be probed as a child of
> the mt6323 MFD because it doesn't have own MMIO space. Otherwise the
> devicetree is malformed. Recent mt6359 ADC driver has same thing with
> dev->parent->parent regmap.
I think Sashiko is overprotective here, but if changing, the whole lot of MFD
drivers should be changed (like Rafael recently has done for driver_override
issue in ACPI related drivers).
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2 2/4] iio: adc: mt6323-auxadc: add mt6323 PMIC AUXADC driver
From: Andy Shevchenko @ 2026-06-16 7:15 UTC (permalink / raw)
To: Roman Vivchar
Cc: Jonathan Cameron, Roman Vivchar via B4 Relay, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Lee Jones, linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Ben Grisdale
In-Reply-To: <E5H72l1Cg-JQGpaYAFl5TIyITmghqMsTaHQTR8VkuFtlzmfCGTpVlceNp8c2BDW7UoheO0Fx6NLJHmu56WHRNWdPNLsaoIKMCftj_bnyvEI=@protonmail.com>
On Mon, Jun 15, 2026 at 10:52:57PM +0000, Roman Vivchar wrote:
> On Sunday, June 14th, 2026 at 8:22 PM, Jonathan Cameron <jic23@kernel.org> wrote:
> > On Tue, 09 Jun 2026 16:31:59 +0300
> > Roman Vivchar via B4 Relay <devnull+rva333.protonmail.com@kernel.org> wrote:
...
> > > +/*
> > > + * The MediaTek MT6323 (as well as a lot of other PMICs) has the following hierarchy:
> > > + * PMIC AUXADC <- PMIC MFD <- SoC PWRAP (wrapper for PWRAP FSM)
> > > + *
> > > + * Therefore, PWRAP regmap should be obtained using dev->parent->parent.
> > > + */
> > > +struct mt6323_auxadc {
> > > + struct regmap *regmap;
> > > + struct mutex lock;
> > Locks should always have a comment on what data they are protecting.
> > I think this one is about protecting the state of a device during a channel read
> > by serializing those reads.
>
> Nuno said kerneldoc looks unnecessary on v1 [1]. How the comment should
> look?
The comment near to the member:
/* Why this lock? */
struct mutex lock;
...
> After these changes, should I keep or drop Andy's Reviewed-by?
Keep it, the above mentioned changes does not affect on that.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH v3 13/13] pinctrl: airoha: try to find chip scu node by phandle first
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
The "airoha,en7581-chip-scu" is not a good compatible string in the en7523
case. Let's search chip scu regmap with "airoha,chip-scu" phangle first
and fallback to SoC specific chip scu compatible string on failure.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/airoha-common.h | 1 +
drivers/pinctrl/airoha/pinctrl-airoha.c | 9 ++++++---
drivers/pinctrl/airoha/pinctrl-an7581.c | 1 +
drivers/pinctrl/airoha/pinctrl-an7583.c | 1 +
drivers/pinctrl/airoha/pinctrl-en7523.c | 1 +
5 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index abd4d2fcd227..79ece49b0c48 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -189,6 +189,7 @@ struct airoha_pinctrl {
};
struct airoha_pinctrl_match_data {
+ const char *chip_scu_compatible;
const struct pinctrl_pin_desc *pins;
const unsigned int num_pins;
const struct pingroup *grps;
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index 6f7e65b7792b..2513fe210e03 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -651,9 +651,12 @@ int airoha_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(pinctrl->regmap))
return PTR_ERR(pinctrl->regmap);
- map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
- if (IS_ERR(map))
- return PTR_ERR(map);
+ map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "airoha,chip-scu");
+ if (IS_ERR_OR_NULL(map)) {
+ map = syscon_regmap_lookup_by_compatible(data->chip_scu_compatible);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+ }
pinctrl->chip_scu = map;
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index d31de7ebbdf9..1b0a3c19f023 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -1420,6 +1420,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
};
static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .chip_scu_compatible = "airoha,en7581-chip-scu",
.pins = pinctrl_pins,
.num_pins = ARRAY_SIZE(pinctrl_pins),
.grps = pinctrl_groups,
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 6e1746ac0ce5..5acd76224699 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -1424,6 +1424,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
};
static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .chip_scu_compatible = "airoha,en7581-chip-scu",
.pins = pinctrl_pins,
.num_pins = ARRAY_SIZE(pinctrl_pins),
.grps = pinctrl_groups,
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
index d23aa8f826d6..9ef93d87d444 100644
--- a/drivers/pinctrl/airoha/pinctrl-en7523.c
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -1072,6 +1072,7 @@ static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
};
static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .chip_scu_compatible = "airoha,en7523-chip-scu",
.pins = pinctrl_pins,
.num_pins = ARRAY_SIZE(pinctrl_pins),
.grps = pinctrl_groups,
--
2.53.0
^ permalink raw reply related
* [PATCH v3 12/13] pinctrl: airoha: add support of en7523 SoC
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
This patch adds support of Airoha en7523 SoC pin controller.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/Kconfig | 6 +
drivers/pinctrl/airoha/Makefile | 1 +
drivers/pinctrl/airoha/pinctrl-en7523.c | 1122 +++++++++++++++++++++++
3 files changed, 1129 insertions(+)
create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 08038a5b11c6..159b4496f64a 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -15,6 +15,7 @@ config PINCTRL_AIROHA
select REGMAP_MMIO
imply PINCTRL_AIROHA_AN7581
imply PINCTRL_AIROHA_AN7583
+ imply PINCTRL_AIROHA_EN7523
help
Say yes here to support pin controller and gpio driver
on Airoha SoC.
@@ -29,4 +30,9 @@ config PINCTRL_AIROHA_AN7583
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_AIROHA
+config PINCTRL_AIROHA_EN7523
+ tristate "EN7523 pinctrl"
+ depends on ARM || COMPILE_TEST
+ depends on PINCTRL_AIROHA
+
endmenu
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index cfd68c45ae0f..8b9202321ba8 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
# SoC drivers
obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
+obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
new file mode 100644
index 000000000000..d23aa8f826d6
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -0,0 +1,1122 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com>
+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+ */
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE 0x0210
+#define GPIO_I2S_MODE_MASK BIT(12)
+#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define PON_TOD_1PPS_MODE_MASK BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+#define GPIO_2ND_I2C_MODE_MASK BIT(0)
+
+#define REG_GPIO_SPI_CS1_MODE 0x0214
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x0218
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+#define GPIO_PCIE_RESET1_MASK BIT(10)
+#define GPIO_PCIE_RESET0_MASK BIT(9)
+#define GPIO_UART2_MODE_MASK BIT(3)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+#define REG_NPU_UART_EN 0x0220
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+#define NPU_UART_EN_MASK BIT(2)
+
+#define REG_FORCE_GPIO_EN 0x0224
+#define FORCE_GPIO_EN(n) BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING 0x0278
+#define REG_LAN_LED1_MAPPING 0x027c
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2 0x001c
+#define SPI_MISO_E2_MASK BIT(13)
+#define SPI_MOSI_E2_MASK BIT(12)
+#define SPI_CLK_E2_MASK BIT(11)
+#define SPI_CS0_E2_MASK BIT(10)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define SPI_MISO_E4_MASK BIT(13)
+#define SPI_MOSI_E4_MASK BIT(12)
+#define SPI_CLK_E4_MASK BIT(11)
+#define SPI_CS0_E4_MASK BIT(10)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+
+#define REG_I2C_SDA_PU 0x0044
+#define SPI_MISO_PU_MASK BIT(13)
+#define SPI_MOSI_PU_MASK BIT(12)
+#define SPI_CLK_PU_MASK BIT(11)
+#define SPI_CS0_PU_MASK BIT(10)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define SPI_MISO_PD_MASK BIT(13)
+#define SPI_MOSI_PD_MASK BIT(12)
+#define SPI_CLK_PD_MASK BIT(11)
+#define SPI_CS0_PD_MASK BIT(10)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO51_FLASH_MODE_CFG BIT(31)
+#define GPIO50_FLASH_MODE_CFG BIT(30)
+#define GPIO49_FLASH_MODE_CFG BIT(29)
+#define GPIO48_FLASH_MODE_CFG BIT(28)
+#define GPIO47_FLASH_MODE_CFG BIT(27)
+#define GPIO46_FLASH_MODE_CFG BIT(26)
+#define GPIO45_FLASH_MODE_CFG BIT(25)
+#define GPIO44_FLASH_MODE_CFG BIT(24)
+#define GPIO43_FLASH_MODE_CFG BIT(23)
+#define GPIO42_FLASH_MODE_CFG BIT(22)
+#define GPIO41_FLASH_MODE_CFG BIT(21)
+#define GPIO40_FLASH_MODE_CFG BIT(20)
+#define GPIO39_FLASH_MODE_CFG BIT(19)
+#define GPIO38_FLASH_MODE_CFG BIT(18)
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static struct pinctrl_pin_desc pinctrl_pins[] = {
+ PINCTRL_PIN(2, "i2c_sda"),
+ PINCTRL_PIN(3, "i2c_scl"),
+ PINCTRL_PIN(4, "spi_cs0"),
+ PINCTRL_PIN(5, "spi_clk"),
+ PINCTRL_PIN(6, "spi_mosi"),
+ PINCTRL_PIN(7, "spi_miso"),
+ PINCTRL_PIN(8, "uart1_txd"),
+ PINCTRL_PIN(9, "uart1_rxd"),
+ PINCTRL_PIN(12, "gpio0"),
+ PINCTRL_PIN(13, "gpio1"),
+ PINCTRL_PIN(14, "gpio2"),
+ PINCTRL_PIN(15, "gpio3"),
+ PINCTRL_PIN(16, "gpio4"),
+ PINCTRL_PIN(17, "gpio5"),
+ PINCTRL_PIN(18, "gpio6"),
+ PINCTRL_PIN(19, "gpio7"),
+ PINCTRL_PIN(20, "gpio8"),
+ PINCTRL_PIN(21, "gpio9"),
+ PINCTRL_PIN(22, "gpio10"),
+ PINCTRL_PIN(23, "gpio11"),
+ PINCTRL_PIN(24, "gpio12"),
+ PINCTRL_PIN(25, "gpio13"),
+ PINCTRL_PIN(26, "gpio14"),
+ PINCTRL_PIN(27, "gpio15"),
+ PINCTRL_PIN(28, "gpio16"),
+ PINCTRL_PIN(29, "gpio17"),
+ PINCTRL_PIN(30, "gpio18"),
+ PINCTRL_PIN(31, "gpio19"),
+ PINCTRL_PIN(32, "gpio20"),
+ PINCTRL_PIN(33, "gpio21"),
+ PINCTRL_PIN(34, "gpio22"),
+ PINCTRL_PIN(35, "gpio23"),
+ PINCTRL_PIN(36, "gpio24"),
+ PINCTRL_PIN(37, "gpio25"),
+ PINCTRL_PIN(38, "gpio26"),
+ PINCTRL_PIN(39, "gpio27"),
+ PINCTRL_PIN(40, "pcie_reset0"),
+ PINCTRL_PIN(41, "pcie_reset1"),
+};
+
+static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 };
+static const int pon_tod_1pps_pins[] = { 21 };
+static const int gsw_tod_1pps_pins[] = { 21 };
+static const int sipo_pins[] = { 13, 38 };
+static const int sipo_rclk_pins[] = { 13, 30, 38 };
+static const int mdio_pins[] = { 20, 21 };
+static const int uart2_pins[] = { 20, 21 };
+static const int npu_uart_pins[] = { 13, 38 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 };
+static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 };
+static const int i2s_pins[] = { 16, 17, 18, 19 };
+static const int pcm1_pins[] = { 24, 25, 26, 27 };
+static const int pcm2_pins[] = { 16, 17, 18, 19 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_quad_pins[] = { 14, 15 };
+static const int spi_cs1_pins[] = { 21 };
+static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 };
+static const int pcm_spi_int_pins[] = { 15 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 22 };
+static const int pcm_spi_cs2_p128_pins[] = { 39 };
+static const int pcm_spi_cs2_p156_pins[] = { 39 };
+static const int pcm_spi_cs3_pins[] = { 20 };
+static const int pcm_spi_cs4_pins[] = { 23 };
+static const int gpio0_pins[] = { 12 };
+static const int gpio1_pins[] = { 13 };
+static const int gpio2_pins[] = { 14 };
+static const int gpio3_pins[] = { 15 };
+static const int gpio4_pins[] = { 16 };
+static const int gpio5_pins[] = { 17 };
+static const int gpio6_pins[] = { 18 };
+static const int gpio7_pins[] = { 19 };
+static const int gpio8_pins[] = { 20 };
+static const int gpio9_pins[] = { 21 };
+static const int gpio10_pins[] = { 22 };
+static const int gpio11_pins[] = { 23 };
+static const int gpio12_pins[] = { 24 };
+static const int gpio13_pins[] = { 25 };
+static const int gpio14_pins[] = { 26 };
+static const int gpio15_pins[] = { 27 };
+static const int gpio16_pins[] = { 28 };
+static const int gpio17_pins[] = { 29 };
+static const int gpio18_pins[] = { 30 };
+static const int gpio19_pins[] = { 31 };
+static const int gpio20_pins[] = { 32 };
+static const int gpio21_pins[] = { 33 };
+static const int gpio22_pins[] = { 34 };
+static const int gpio23_pins[] = { 35 };
+static const int gpio24_pins[] = { 36 };
+static const int gpio25_pins[] = { 37 };
+static const int gpio26_pins[] = { 38 };
+static const int gpio27_pins[] = { 39 };
+static const int gpio28_pins[] = { 40 };
+static const int gpio29_pins[] = { 41 };
+static const int pcie_reset0_pins[] = { 40 };
+static const int pcie_reset1_pins[] = { 41 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", i2s),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+ "pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = { "uart2", "npu_uart" };
+static const char *const i2c_groups[] = { "i2c1" };
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pcm_spi_groups[] = {
+ "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
+ "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4"
+};
+static const char *const i2s_groups[] = { "i2s" };
+static const char *const gpio_groups[] = { "gpio28", "gpio29" };
+static const char *const pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1"
+};
+static const char *const pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29"
+};
+static const char *const phy1_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy2_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy3_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy4_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy1_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy2_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy3_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy4_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+ {
+ .name = "pon_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ PON_TOD_1PPS_MODE_MASK,
+ PON_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "gsw_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GSW_TOD_1PPS_MODE_MASK,
+ GSW_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SGMII_MDIO_MODE_MASK,
+ GPIO_SGMII_MDIO_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK,
+ GPIO_UART2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "npu_uart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ NPU_UART_EN_MASK,
+ NPU_UART_EN_MASK
+ },
+ .regmap_size = 1,
+ }
+};
+
+static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+ {
+ .name = "i2c1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_2ND_I2C_MODE_MASK,
+ GPIO_2ND_I2C_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_MODE_MASK,
+ GPIO_PCM_SPI_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_int",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK,
+ GPIO_PCM_INT_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK,
+ GPIO_PCM_RESET_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK,
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p128",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p156",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK,
+ GPIO_PCM_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK,
+ GPIO_PCM_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+ {
+ .name = "i2s",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_I2S_MODE_MASK,
+ GPIO_I2S_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+};
+
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("i2c", i2c),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+ PINCTRL_FUNC_DESC("i2s", i2s),
+ PINCTRL_FUNC_DESC("gpio", gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(29)),
+};
+
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-en7523",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_AUTHOR("Matheus Sampaio Queiroga <srherobrine20@gmail.com>");
+MODULE_AUTHOR("Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC");
--
2.53.0
^ permalink raw reply related
* [PATCH v3 11/13] pinctrl: airoha: an7583: add support for pon_alt pinmux
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
add support for pon pin function for pon_alt pin group.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7583.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 959eed06fead..6e1746ac0ce5 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -38,6 +38,7 @@
#define GPIO_SPI_CS1_MODE_MASK BIT(0)
#define REG_GPIO_PON_MODE 0x021c
+#define GPIO_PON_ALT_MODE_MASK BIT(27)
#define MDIO_0_GPIO_MODE_MASK BIT(26)
#define MDC_0_GPIO_MODE_MASK BIT(25)
#define UART_RXD_GPIO_MODE_MASK BIT(24)
@@ -391,6 +392,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = {
};
static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
static const int pon_tod_1pps_pins[] = { 32 };
static const int gsw_tod_1pps_pins[] = { 32 };
static const int sipo_pins[] = { 34, 35 };
@@ -479,6 +481,7 @@ static const int pcie_reset1_pins[] = { 52 };
static const struct pingroup pinctrl_groups[] = {
PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_alt", pon_alt),
PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
PINCTRL_PIN_GROUP("sipo", sipo),
@@ -562,7 +565,7 @@ static const struct pingroup pinctrl_groups[] = {
PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
};
-static const char *const pon_groups[] = { "pon" };
+static const char *const pon_groups[] = { "pon", "pon_alt" };
static const char *const tod_1pps_groups[] = {
"pon_tod_1pps", "gsw_tod_1pps"
};
@@ -629,10 +632,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
- GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
GPIO_PON_MODE_MASK
},
.regmap_size = 1,
+ }, {
+ .name = "pon_alt",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
+ GPIO_PON_ALT_MODE_MASK
+ },
+ .regmap_size = 1,
},
};
--
2.53.0
^ permalink raw reply related
* [PATCH v3 10/13] pinctrl: airoha: an7583: add support for npu_uart pinmux
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
add support for uart pin function for npu_uart pin group.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7583.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index d4fbb12fc639..959eed06fead 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -68,6 +68,7 @@
#define REG_NPU_UART_EN 0x0224
#define JTAG_UDI_EN_MASK BIT(4)
#define JTAG_DFD_EN_MASK BIT(3)
+#define NPU_UART_EN_MASK BIT(2)
#define REG_FORCE_GPIO_EN 0x0228
#define FORCE_GPIO_EN(n) BIT(n)
@@ -569,7 +570,7 @@ static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
static const char *const mdio_groups[] = { "mdio" };
static const char *const uart_groups[] = {
"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
- "uart4", "uart5"
+ "uart4", "uart5", "npu_uart"
};
static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
static const char *const pcm_groups[] = { "pcm1", "pcm2" };
@@ -754,6 +755,15 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
GPIO_UART5_MODE_MASK
},
.regmap_size = 1,
+ }, {
+ .name = "npu_uart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ NPU_UART_EN_MASK,
+ NPU_UART_EN_MASK
+ },
+ .regmap_size = 1,
},
};
--
2.53.0
^ permalink raw reply related
* [PATCH v3 09/13] pinctrl: airoha: an7583: remove an7583 prefix from variable names and definitions
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
We have only an7583 specific code in the pinctrl-an7583 kernel module,
so an7583 prefix is not necessary anymore. Remove it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7583.c | 599 ++++++++++++------------
1 file changed, 300 insertions(+), 299 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 07a86aae3459..d4fbb12fc639 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -24,7 +24,7 @@
#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22)
#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
+#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
#define GPIO_PCM_SPI_MODE_MASK BIT(16)
#define GPIO_PCM2_MODE_MASK BIT(13)
@@ -38,18 +38,18 @@
#define GPIO_SPI_CS1_MODE_MASK BIT(0)
#define REG_GPIO_PON_MODE 0x021c
-#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
-#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
-#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
-#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
-#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
-#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
-#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
-#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
-#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
-#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
-#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
-#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
+#define MDIO_0_GPIO_MODE_MASK BIT(26)
+#define MDC_0_GPIO_MODE_MASK BIT(25)
+#define UART_RXD_GPIO_MODE_MASK BIT(24)
+#define UART_TXD_GPIO_MODE_MASK BIT(23)
+#define SPI_MISO_GPIO_MODE_MASK BIT(22)
+#define SPI_MOSI_GPIO_MODE_MASK BIT(21)
+#define SPI_CS_GPIO_MODE_MASK BIT(20)
+#define SPI_CLK_GPIO_MODE_MASK BIT(19)
+#define I2C1_SDA_GPIO_MODE_MASK BIT(18)
+#define I2C1_SCL_GPIO_MODE_MASK BIT(17)
+#define I2C0_SDA_GPIO_MODE_MASK BIT(16)
+#define I2C0_SCL_GPIO_MODE_MASK BIT(15)
#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
#define SIPO_RCLK_MODE_MASK BIT(11)
@@ -93,32 +93,32 @@
/* CONF */
#define REG_I2C_SDA_E2 0x001c
-#define AN7583_I2C1_SCL_E2_MASK BIT(16)
-#define AN7583_I2C1_SDA_E2_MASK BIT(15)
+#define I2C1_SCL_E2_MASK BIT(16)
+#define I2C1_SDA_E2_MASK BIT(15)
#define SPI_MISO_E2_MASK BIT(14)
#define SPI_MOSI_E2_MASK BIT(13)
#define SPI_CLK_E2_MASK BIT(12)
#define SPI_CS0_E2_MASK BIT(11)
#define PCIE1_RESET_E2_MASK BIT(9)
#define PCIE0_RESET_E2_MASK BIT(8)
-#define AN7583_MDIO_0_E2_MASK BIT(5)
-#define AN7583_MDC_0_E2_MASK BIT(4)
+#define MDIO_0_E2_MASK BIT(5)
+#define MDC_0_E2_MASK BIT(4)
#define UART1_RXD_E2_MASK BIT(3)
#define UART1_TXD_E2_MASK BIT(2)
#define I2C_SCL_E2_MASK BIT(1)
#define I2C_SDA_E2_MASK BIT(0)
#define REG_I2C_SDA_E4 0x0020
-#define AN7583_I2C1_SCL_E4_MASK BIT(16)
-#define AN7583_I2C1_SDA_E4_MASK BIT(15)
+#define I2C1_SCL_E4_MASK BIT(16)
+#define I2C1_SDA_E4_MASK BIT(15)
#define SPI_MISO_E4_MASK BIT(14)
#define SPI_MOSI_E4_MASK BIT(13)
#define SPI_CLK_E4_MASK BIT(12)
#define SPI_CS0_E4_MASK BIT(11)
#define PCIE1_RESET_E4_MASK BIT(9)
#define PCIE0_RESET_E4_MASK BIT(8)
-#define AN7583_MDIO_0_E4_MASK BIT(5)
-#define AN7583_MDC_0_E4_MASK BIT(4)
+#define MDIO_0_E4_MASK BIT(5)
+#define MDC_0_E4_MASK BIT(4)
#define UART1_RXD_E4_MASK BIT(3)
#define UART1_TXD_E4_MASK BIT(2)
#define I2C_SCL_E4_MASK BIT(1)
@@ -130,32 +130,32 @@
#define REG_GPIO_H_E4 0x0030
#define REG_I2C_SDA_PU 0x0044
-#define AN7583_I2C1_SCL_PU_MASK BIT(16)
-#define AN7583_I2C1_SDA_PU_MASK BIT(15)
+#define I2C1_SCL_PU_MASK BIT(16)
+#define I2C1_SDA_PU_MASK BIT(15)
#define SPI_MISO_PU_MASK BIT(14)
#define SPI_MOSI_PU_MASK BIT(13)
#define SPI_CLK_PU_MASK BIT(12)
#define SPI_CS0_PU_MASK BIT(11)
#define PCIE1_RESET_PU_MASK BIT(9)
#define PCIE0_RESET_PU_MASK BIT(8)
-#define AN7583_MDIO_0_PU_MASK BIT(5)
-#define AN7583_MDC_0_PU_MASK BIT(4)
+#define MDIO_0_PU_MASK BIT(5)
+#define MDC_0_PU_MASK BIT(4)
#define UART1_RXD_PU_MASK BIT(3)
#define UART1_TXD_PU_MASK BIT(2)
#define I2C_SCL_PU_MASK BIT(1)
#define I2C_SDA_PU_MASK BIT(0)
#define REG_I2C_SDA_PD 0x0048
-#define AN7583_I2C1_SCL_PD_MASK BIT(16)
-#define AN7583_I2C1_SDA_PD_MASK BIT(15)
+#define I2C1_SCL_PD_MASK BIT(16)
+#define I2C1_SDA_PD_MASK BIT(15)
#define SPI_MISO_PD_MASK BIT(14)
#define SPI_MOSI_PD_MASK BIT(13)
#define SPI_CLK_PD_MASK BIT(12)
#define SPI_CS0_PD_MASK BIT(11)
#define PCIE1_RESET_PD_MASK BIT(9)
#define PCIE0_RESET_PD_MASK BIT(8)
-#define AN7583_MDIO_0_PD_MASK BIT(5)
-#define AN7583_MDC_0_PD_MASK BIT(4)
+#define MDIO_0_PD_MASK BIT(5)
+#define MDC_0_PD_MASK BIT(4)
#define UART1_RXD_PD_MASK BIT(3)
#define UART1_TXD_PD_MASK BIT(2)
#define I2C_SCL_PD_MASK BIT(1)
@@ -333,7 +333,7 @@
.regmap_size = 2, \
}
-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
PINCTRL_PIN(2, "gpio0"),
PINCTRL_PIN(3, "gpio1"),
PINCTRL_PIN(4, "gpio2"),
@@ -389,176 +389,176 @@ static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
PINCTRL_PIN(54, "mdio_0"),
};
-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-static const int an7583_pon_tod_1pps_pins[] = { 32 };
-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-static const int an7583_sipo_pins[] = { 34, 35 };
-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-static const int an7583_mdio_pins[] = { 43, 44 };
-static const int an7583_uart2_pins[] = { 34, 35 };
-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-static const int an7583_hsuart_pins[] = { 30, 31 };
-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-static const int an7583_npu_uart_pins[] = { 7, 8 };
-static const int an7583_uart4_pins[] = { 7, 8 };
-static const int an7583_uart5_pins[] = { 23, 24 };
-static const int an7583_i2c0_pins[] = { 41, 42 };
-static const int an7583_i2c1_pins[] = { 43, 44 };
-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-static const int an7583_spi_quad_pins[] = { 25, 26 };
-static const int an7583_spi_cs1_pins[] = { 27 };
-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-static const int an7583_pcm_spi_rst_pins[] = { 14 };
-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-static const int an7583_emmc_pins[] = {
+static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int pon_tod_1pps_pins[] = { 32 };
+static const int gsw_tod_1pps_pins[] = { 32 };
+static const int sipo_pins[] = { 34, 35 };
+static const int sipo_rclk_pins[] = { 34, 35, 33 };
+static const int mdio_pins[] = { 43, 44 };
+static const int uart2_pins[] = { 34, 35 };
+static const int uart2_cts_rts_pins[] = { 32, 33 };
+static const int hsuart_pins[] = { 30, 31 };
+static const int hsuart_cts_rts_pins[] = { 28, 29 };
+static const int npu_uart_pins[] = { 7, 8 };
+static const int uart4_pins[] = { 7, 8 };
+static const int uart5_pins[] = { 23, 24 };
+static const int i2c0_pins[] = { 41, 42 };
+static const int i2c1_pins[] = { 43, 44 };
+static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int spi_pins[] = { 28, 29, 30, 31 };
+static const int spi_quad_pins[] = { 25, 26 };
+static const int spi_cs1_pins[] = { 27 };
+static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 24 };
+static const int emmc_pins[] = {
7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
};
-static const int an7583_pnand_pins[] = {
+static const int pnand_pins[] = {
7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
};
-static const int an7583_gpio0_pins[] = { 2 };
-static const int an7583_gpio1_pins[] = { 3 };
-static const int an7583_gpio2_pins[] = { 4 };
-static const int an7583_gpio3_pins[] = { 5 };
-static const int an7583_gpio4_pins[] = { 6 };
-static const int an7583_gpio5_pins[] = { 7 };
-static const int an7583_gpio6_pins[] = { 8 };
-static const int an7583_gpio7_pins[] = { 9 };
-static const int an7583_gpio8_pins[] = { 10 };
-static const int an7583_gpio9_pins[] = { 11 };
-static const int an7583_gpio10_pins[] = { 12 };
-static const int an7583_gpio11_pins[] = { 13 };
-static const int an7583_gpio12_pins[] = { 14 };
-static const int an7583_gpio13_pins[] = { 15 };
-static const int an7583_gpio14_pins[] = { 16 };
-static const int an7583_gpio15_pins[] = { 17 };
-static const int an7583_gpio16_pins[] = { 18 };
-static const int an7583_gpio17_pins[] = { 19 };
-static const int an7583_gpio18_pins[] = { 20 };
-static const int an7583_gpio19_pins[] = { 21 };
-static const int an7583_gpio20_pins[] = { 22 };
-static const int an7583_gpio21_pins[] = { 23 };
-static const int an7583_gpio22_pins[] = { 24 };
-static const int an7583_gpio23_pins[] = { 25 };
-static const int an7583_gpio24_pins[] = { 26 };
-static const int an7583_gpio25_pins[] = { 27 };
-static const int an7583_gpio26_pins[] = { 28 };
-static const int an7583_gpio27_pins[] = { 29 };
-static const int an7583_gpio28_pins[] = { 30 };
-static const int an7583_gpio29_pins[] = { 31 };
-static const int an7583_gpio30_pins[] = { 32 };
-static const int an7583_gpio31_pins[] = { 33 };
-static const int an7583_gpio32_pins[] = { 34 };
-static const int an7583_gpio33_pins[] = { 35 };
-static const int an7583_gpio34_pins[] = { 36 };
-static const int an7583_gpio35_pins[] = { 37 };
-static const int an7583_gpio36_pins[] = { 38 };
-static const int an7583_gpio37_pins[] = { 39 };
-static const int an7583_gpio38_pins[] = { 40 };
-static const int an7583_gpio39_pins[] = { 41 };
-static const int an7583_gpio40_pins[] = { 42 };
-static const int an7583_gpio41_pins[] = { 43 };
-static const int an7583_gpio42_pins[] = { 44 };
-static const int an7583_gpio43_pins[] = { 45 };
-static const int an7583_gpio44_pins[] = { 46 };
-static const int an7583_gpio45_pins[] = { 47 };
-static const int an7583_gpio46_pins[] = { 48 };
-static const int an7583_gpio47_pins[] = { 49 };
-static const int an7583_gpio48_pins[] = { 50 };
-static const int an7583_gpio49_pins[] = { 51 };
-static const int an7583_gpio50_pins[] = { 52 };
-static const int an7583_gpio51_pins[] = { 53 };
-static const int an7583_gpio52_pins[] = { 54 };
-static const int an7583_pcie_reset0_pins[] = { 51 };
-static const int an7583_pcie_reset1_pins[] = { 52 };
-
-static const struct pingroup an7583_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", an7583_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", an7583_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", an7583_mdio),
- PINCTRL_PIN_GROUP("uart2", an7583_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
- PINCTRL_PIN_GROUP("uart4", an7583_uart4),
- PINCTRL_PIN_GROUP("uart5", an7583_uart5),
- PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
- PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
- PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
- PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
- PINCTRL_PIN_GROUP("spi", an7583_spi),
- PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("emmc", an7583_emmc),
- PINCTRL_PIN_GROUP("pnand", an7583_pnand),
- PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
- PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
- PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
- PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
- PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
- PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
- PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
- PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
- PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
- PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
- PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
- PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
- PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
- PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
- PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
- PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
- PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
- PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
- PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
- PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
- PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
- PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
- PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
- PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
- PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
- PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
- PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
- PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
- PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
- PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
- PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
- PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
- PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
- PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
- PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
- PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
- PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
- PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
- PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
- PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
- PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
- PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
- PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
- PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
- PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
- PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
- PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
- PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
- PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
- PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
- PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
- PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
- PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
- PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+static const int gpio0_pins[] = { 2 };
+static const int gpio1_pins[] = { 3 };
+static const int gpio2_pins[] = { 4 };
+static const int gpio3_pins[] = { 5 };
+static const int gpio4_pins[] = { 6 };
+static const int gpio5_pins[] = { 7 };
+static const int gpio6_pins[] = { 8 };
+static const int gpio7_pins[] = { 9 };
+static const int gpio8_pins[] = { 10 };
+static const int gpio9_pins[] = { 11 };
+static const int gpio10_pins[] = { 12 };
+static const int gpio11_pins[] = { 13 };
+static const int gpio12_pins[] = { 14 };
+static const int gpio13_pins[] = { 15 };
+static const int gpio14_pins[] = { 16 };
+static const int gpio15_pins[] = { 17 };
+static const int gpio16_pins[] = { 18 };
+static const int gpio17_pins[] = { 19 };
+static const int gpio18_pins[] = { 20 };
+static const int gpio19_pins[] = { 21 };
+static const int gpio20_pins[] = { 22 };
+static const int gpio21_pins[] = { 23 };
+static const int gpio22_pins[] = { 24 };
+static const int gpio23_pins[] = { 25 };
+static const int gpio24_pins[] = { 26 };
+static const int gpio25_pins[] = { 27 };
+static const int gpio26_pins[] = { 28 };
+static const int gpio27_pins[] = { 29 };
+static const int gpio28_pins[] = { 30 };
+static const int gpio29_pins[] = { 31 };
+static const int gpio30_pins[] = { 32 };
+static const int gpio31_pins[] = { 33 };
+static const int gpio32_pins[] = { 34 };
+static const int gpio33_pins[] = { 35 };
+static const int gpio34_pins[] = { 36 };
+static const int gpio35_pins[] = { 37 };
+static const int gpio36_pins[] = { 38 };
+static const int gpio37_pins[] = { 39 };
+static const int gpio38_pins[] = { 40 };
+static const int gpio39_pins[] = { 41 };
+static const int gpio40_pins[] = { 42 };
+static const int gpio41_pins[] = { 43 };
+static const int gpio42_pins[] = { 44 };
+static const int gpio43_pins[] = { 45 };
+static const int gpio44_pins[] = { 46 };
+static const int gpio45_pins[] = { 47 };
+static const int gpio46_pins[] = { 48 };
+static const int gpio47_pins[] = { 49 };
+static const int gpio48_pins[] = { 50 };
+static const int gpio49_pins[] = { 51 };
+static const int gpio50_pins[] = { 52 };
+static const int gpio51_pins[] = { 53 };
+static const int gpio52_pins[] = { 54 };
+static const int pcie_reset0_pins[] = { 51 };
+static const int pcie_reset1_pins[] = { 52 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+ PINCTRL_PIN_GROUP("uart4", uart4),
+ PINCTRL_PIN_GROUP("uart5", uart5),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("emmc", emmc),
+ PINCTRL_PIN_GROUP("pnand", pnand),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("gpio30", gpio30),
+ PINCTRL_PIN_GROUP("gpio31", gpio31),
+ PINCTRL_PIN_GROUP("gpio32", gpio32),
+ PINCTRL_PIN_GROUP("gpio33", gpio33),
+ PINCTRL_PIN_GROUP("gpio34", gpio34),
+ PINCTRL_PIN_GROUP("gpio35", gpio35),
+ PINCTRL_PIN_GROUP("gpio36", gpio36),
+ PINCTRL_PIN_GROUP("gpio37", gpio37),
+ PINCTRL_PIN_GROUP("gpio38", gpio38),
+ PINCTRL_PIN_GROUP("gpio39", gpio39),
+ PINCTRL_PIN_GROUP("gpio40", gpio40),
+ PINCTRL_PIN_GROUP("gpio41", gpio41),
+ PINCTRL_PIN_GROUP("gpio42", gpio42),
+ PINCTRL_PIN_GROUP("gpio43", gpio43),
+ PINCTRL_PIN_GROUP("gpio44", gpio44),
+ PINCTRL_PIN_GROUP("gpio45", gpio45),
+ PINCTRL_PIN_GROUP("gpio46", gpio46),
+ PINCTRL_PIN_GROUP("gpio47", gpio47),
+ PINCTRL_PIN_GROUP("gpio48", gpio48),
+ PINCTRL_PIN_GROUP("gpio49", gpio49),
+ PINCTRL_PIN_GROUP("gpio50", gpio50),
+ PINCTRL_PIN_GROUP("gpio51", gpio51),
+ PINCTRL_PIN_GROUP("gpio52", gpio52),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
};
static const char *const pon_groups[] = { "pon" };
@@ -566,7 +566,7 @@ static const char *const tod_1pps_groups[] = {
"pon_tod_1pps", "gsw_tod_1pps"
};
static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
-static const char *const an7583_mdio_groups[] = { "mdio" };
+static const char *const mdio_groups[] = { "mdio" };
static const char *const uart_groups[] = {
"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
"uart4", "uart5"
@@ -574,20 +574,20 @@ static const char *const uart_groups[] = {
static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
static const char *const pcm_groups[] = { "pcm1", "pcm2" };
static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-static const char *const an7583_pcm_spi_groups[] = {
+static const char *const pcm_spi_groups[] = {
"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
};
static const char *const emmc_groups[] = { "emmc" };
static const char *const pnand_groups[] = { "pnand" };
-static const char *const an7583_gpio_groups[] = {
+static const char *const gpio_groups[] = {
"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
"gpio49", "gpio50", "gpio51", "gpio52"
};
-static const char *const an7583_pcie_reset_groups[] = {
+static const char *const pcie_reset_groups[] = {
"pcie_reset0", "pcie_reset1"
};
-static const char *const an7583_pwm_groups[] = {
+static const char *const pwm_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
@@ -597,28 +597,28 @@ static const char *const an7583_pwm_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
};
-static const char *const an7583_phy1_led0_groups[] = {
+static const char *const phy1_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy2_led0_groups[] = {
+static const char *const phy2_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy3_led0_groups[] = {
+static const char *const phy3_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy4_led0_groups[] = {
+static const char *const phy4_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy1_led1_groups[] = {
+static const char *const phy1_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
-static const char *const an7583_phy2_led1_groups[] = {
+static const char *const phy2_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
-static const char *const an7583_phy3_led1_groups[] = {
+static const char *const phy3_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
-static const char *const an7583_phy4_led1_groups[] = {
+static const char *const phy4_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
@@ -679,7 +679,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
{
.name = "mdio",
.regmap[0] = {
@@ -850,7 +850,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
{
.name = "pcm_spi",
.regmap[0] = {
@@ -892,8 +892,8 @@ static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_SPI_CS1_MODE,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+ GPIO_PCM_SPI_CS2_MODE_MASK,
+ GPIO_PCM_SPI_CS2_MODE_MASK
},
.regmap_size = 1,
}, {
@@ -943,37 +943,37 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ I2C0_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ I2C0_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ I2C1_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ I2C1_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
+ SPI_CLK_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
+ SPI_CS_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ SPI_MOSI_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
+ SPI_MISO_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
+ UART_TXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
+ UART_RXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
GPIO_PCIE_RESET0_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
GPIO_PCIE_RESET1_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+ MDC_0_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK),
};
-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
{
.name = "pcie_reset0",
.regmap[0] = {
@@ -995,7 +995,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
@@ -1032,34 +1032,34 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ I2C0_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ I2C0_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ I2C1_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ I2C1_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
+ SPI_CLK_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
+ SPI_CS_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ SPI_MOSI_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
+ SPI_MISO_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
+ UART_TXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
+ UART_RXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
GPIO_PCIE_RESET0_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
GPIO_PCIE_RESET1_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
+ MDC_0_GPIO_MODE_MASK),
};
-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1070,7 +1070,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1081,7 +1081,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1092,7 +1092,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1103,7 +1103,7 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1114,7 +1114,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1125,7 +1125,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1136,7 +1136,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1147,31 +1147,32 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
PINCTRL_FUNC_DESC("sipo", sipo),
- PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+ PINCTRL_FUNC_DESC("mdio", mdio),
PINCTRL_FUNC_DESC("uart", uart),
PINCTRL_FUNC_DESC("jtag", jtag),
PINCTRL_FUNC_DESC("pcm", pcm),
PINCTRL_FUNC_DESC("spi", spi),
- PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
PINCTRL_FUNC_DESC("emmc", emmc),
PINCTRL_FUNC_DESC("pnand", pnand),
- PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
- PINCTRL_FUNC_DESC("pwm", an7583_pwm),
- PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
- PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
- PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
- PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
- PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
- PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
- PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
- PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+ PINCTRL_FUNC_DESC("gpio", gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
@@ -1213,8 +1214,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
@@ -1223,11 +1224,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
@@ -1269,8 +1270,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
@@ -1279,11 +1280,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
@@ -1325,8 +1326,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
@@ -1335,11 +1336,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
@@ -1381,8 +1382,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
@@ -1391,48 +1392,48 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
};
-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
- .pins = an7583_pinctrl_pins,
- .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
- .grps = an7583_pinctrl_groups,
- .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
- .funcs = an7583_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = an7583_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
},
[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = an7583_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = an7583_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = an7583_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
},
[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = an7583_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
},
},
};
static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+ { .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
--
2.53.0
^ permalink raw reply related
* [PATCH v3 08/13] pinctrl: airoha: an7581: remove en7581 prefix from variable names
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
We have only an7581 specific code in the pinctrl-an7581 kernel module,
so 'en7581_' prefix is not necessary anymore. Remove it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7581.c | 386 ++++++++++++------------
1 file changed, 193 insertions(+), 193 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index 355d557dbdce..d31de7ebbdf9 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -316,7 +316,7 @@
.regmap_size = 2, \
}
-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
PINCTRL_PIN(0, "uart1_txd"),
PINCTRL_PIN(1, "uart1_rxd"),
PINCTRL_PIN(2, "i2c_scl"),
@@ -374,178 +374,178 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
PINCTRL_PIN(59, "pcie_reset2"),
};
-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int en7581_pon_tod_1pps_pins[] = { 46 };
-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-static const int en7581_sipo_pins[] = { 16, 17 };
-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-static const int en7581_mdio_pins[] = { 14, 15 };
-static const int en7581_uart2_pins[] = { 48, 55 };
-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-static const int en7581_hsuart_pins[] = { 28, 29 };
-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-static const int en7581_uart4_pins[] = { 38, 39 };
-static const int en7581_uart5_pins[] = { 18, 19 };
-static const int en7581_i2c0_pins[] = { 2, 3 };
-static const int en7581_i2c1_pins[] = { 14, 15 };
-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-static const int en7581_spi_quad_pins[] = { 32, 33 };
-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-static const int en7581_spi_cs1_pins[] = { 34 };
-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int en7581_pcm_spi_int_pins[] = { 14 };
-static const int en7581_pcm_spi_rst_pins[] = { 15 };
-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-static const int en7581_emmc_pins[] = {
+static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int pon_tod_1pps_pins[] = { 46 };
+static const int gsw_tod_1pps_pins[] = { 46 };
+static const int sipo_pins[] = { 16, 17 };
+static const int sipo_rclk_pins[] = { 16, 17, 43 };
+static const int mdio_pins[] = { 14, 15 };
+static const int uart2_pins[] = { 48, 55 };
+static const int uart2_cts_rts_pins[] = { 46, 47 };
+static const int hsuart_pins[] = { 28, 29 };
+static const int hsuart_cts_rts_pins[] = { 26, 27 };
+static const int uart4_pins[] = { 38, 39 };
+static const int uart5_pins[] = { 18, 19 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int i2s_pins[] = { 26, 27, 28, 29 };
+static const int pcm1_pins[] = { 22, 23, 24, 25 };
+static const int pcm2_pins[] = { 18, 19, 20, 21 };
+static const int spi_quad_pins[] = { 32, 33 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_cs1_pins[] = { 34 };
+static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int pcm_spi_int_pins[] = { 14 };
+static const int pcm_spi_rst_pins[] = { 15 };
+static const int pcm_spi_cs1_pins[] = { 43 };
+static const int pcm_spi_cs2_pins[] = { 40 };
+static const int pcm_spi_cs2_p128_pins[] = { 40 };
+static const int pcm_spi_cs2_p156_pins[] = { 40 };
+static const int pcm_spi_cs3_pins[] = { 41 };
+static const int pcm_spi_cs4_pins[] = { 42 };
+static const int emmc_pins[] = {
4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
};
-static const int en7581_pnand_pins[] = {
+static const int pnand_pins[] = {
4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
};
-static const int en7581_gpio0_pins[] = { 13 };
-static const int en7581_gpio1_pins[] = { 14 };
-static const int en7581_gpio2_pins[] = { 15 };
-static const int en7581_gpio3_pins[] = { 16 };
-static const int en7581_gpio4_pins[] = { 17 };
-static const int en7581_gpio5_pins[] = { 18 };
-static const int en7581_gpio6_pins[] = { 19 };
-static const int en7581_gpio7_pins[] = { 20 };
-static const int en7581_gpio8_pins[] = { 21 };
-static const int en7581_gpio9_pins[] = { 22 };
-static const int en7581_gpio10_pins[] = { 23 };
-static const int en7581_gpio11_pins[] = { 24 };
-static const int en7581_gpio12_pins[] = { 25 };
-static const int en7581_gpio13_pins[] = { 26 };
-static const int en7581_gpio14_pins[] = { 27 };
-static const int en7581_gpio15_pins[] = { 28 };
-static const int en7581_gpio16_pins[] = { 29 };
-static const int en7581_gpio17_pins[] = { 30 };
-static const int en7581_gpio18_pins[] = { 31 };
-static const int en7581_gpio19_pins[] = { 32 };
-static const int en7581_gpio20_pins[] = { 33 };
-static const int en7581_gpio21_pins[] = { 34 };
-static const int en7581_gpio22_pins[] = { 35 };
-static const int en7581_gpio23_pins[] = { 36 };
-static const int en7581_gpio24_pins[] = { 37 };
-static const int en7581_gpio25_pins[] = { 38 };
-static const int en7581_gpio26_pins[] = { 39 };
-static const int en7581_gpio27_pins[] = { 40 };
-static const int en7581_gpio28_pins[] = { 41 };
-static const int en7581_gpio29_pins[] = { 42 };
-static const int en7581_gpio30_pins[] = { 43 };
-static const int en7581_gpio31_pins[] = { 44 };
-static const int en7581_gpio32_pins[] = { 45 };
-static const int en7581_gpio33_pins[] = { 46 };
-static const int en7581_gpio34_pins[] = { 47 };
-static const int en7581_gpio35_pins[] = { 48 };
-static const int en7581_gpio36_pins[] = { 49 };
-static const int en7581_gpio37_pins[] = { 50 };
-static const int en7581_gpio38_pins[] = { 51 };
-static const int en7581_gpio39_pins[] = { 52 };
-static const int en7581_gpio40_pins[] = { 53 };
-static const int en7581_gpio41_pins[] = { 54 };
-static const int en7581_gpio42_pins[] = { 55 };
-static const int en7581_gpio43_pins[] = { 56 };
-static const int en7581_gpio44_pins[] = { 57 };
-static const int en7581_gpio45_pins[] = { 58 };
-static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_pcie_reset0_pins[] = { 57 };
-static const int en7581_pcie_reset1_pins[] = { 58 };
-static const int en7581_pcie_reset2_pins[] = { 59 };
-
-static const struct pingroup en7581_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", en7581_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", en7581_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", en7581_mdio),
- PINCTRL_PIN_GROUP("uart2", en7581_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("uart4", en7581_uart4),
- PINCTRL_PIN_GROUP("uart5", en7581_uart5),
- PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
- PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
- PINCTRL_PIN_GROUP("i2s", en7581_i2s),
- PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
- PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
- PINCTRL_PIN_GROUP("spi", en7581_spi),
- PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
- PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
- PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
- PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
- PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
- PINCTRL_PIN_GROUP("emmc", en7581_emmc),
- PINCTRL_PIN_GROUP("pnand", en7581_pnand),
- PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
- PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
- PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
- PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
- PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
- PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
- PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
- PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
- PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
- PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
- PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
- PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
- PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
- PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
- PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
- PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
- PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
- PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
- PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
- PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
- PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
- PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
- PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
- PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
- PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
- PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
- PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
- PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
- PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
- PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
- PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
- PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
- PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
- PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
- PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
- PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
- PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
- PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
- PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
- PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
- PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
- PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
- PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
- PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
- PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
- PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
- PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
- PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
- PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+static const int gpio0_pins[] = { 13 };
+static const int gpio1_pins[] = { 14 };
+static const int gpio2_pins[] = { 15 };
+static const int gpio3_pins[] = { 16 };
+static const int gpio4_pins[] = { 17 };
+static const int gpio5_pins[] = { 18 };
+static const int gpio6_pins[] = { 19 };
+static const int gpio7_pins[] = { 20 };
+static const int gpio8_pins[] = { 21 };
+static const int gpio9_pins[] = { 22 };
+static const int gpio10_pins[] = { 23 };
+static const int gpio11_pins[] = { 24 };
+static const int gpio12_pins[] = { 25 };
+static const int gpio13_pins[] = { 26 };
+static const int gpio14_pins[] = { 27 };
+static const int gpio15_pins[] = { 28 };
+static const int gpio16_pins[] = { 29 };
+static const int gpio17_pins[] = { 30 };
+static const int gpio18_pins[] = { 31 };
+static const int gpio19_pins[] = { 32 };
+static const int gpio20_pins[] = { 33 };
+static const int gpio21_pins[] = { 34 };
+static const int gpio22_pins[] = { 35 };
+static const int gpio23_pins[] = { 36 };
+static const int gpio24_pins[] = { 37 };
+static const int gpio25_pins[] = { 38 };
+static const int gpio26_pins[] = { 39 };
+static const int gpio27_pins[] = { 40 };
+static const int gpio28_pins[] = { 41 };
+static const int gpio29_pins[] = { 42 };
+static const int gpio30_pins[] = { 43 };
+static const int gpio31_pins[] = { 44 };
+static const int gpio32_pins[] = { 45 };
+static const int gpio33_pins[] = { 46 };
+static const int gpio34_pins[] = { 47 };
+static const int gpio35_pins[] = { 48 };
+static const int gpio36_pins[] = { 49 };
+static const int gpio37_pins[] = { 50 };
+static const int gpio38_pins[] = { 51 };
+static const int gpio39_pins[] = { 52 };
+static const int gpio40_pins[] = { 53 };
+static const int gpio41_pins[] = { 54 };
+static const int gpio42_pins[] = { 55 };
+static const int gpio43_pins[] = { 56 };
+static const int gpio44_pins[] = { 57 };
+static const int gpio45_pins[] = { 58 };
+static const int gpio46_pins[] = { 59 };
+static const int pcie_reset0_pins[] = { 57 };
+static const int pcie_reset1_pins[] = { 58 };
+static const int pcie_reset2_pins[] = { 59 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("uart4", uart4),
+ PINCTRL_PIN_GROUP("uart5", uart5),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", i2s),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("emmc", emmc),
+ PINCTRL_PIN_GROUP("pnand", pnand),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("gpio30", gpio30),
+ PINCTRL_PIN_GROUP("gpio31", gpio31),
+ PINCTRL_PIN_GROUP("gpio32", gpio32),
+ PINCTRL_PIN_GROUP("gpio33", gpio33),
+ PINCTRL_PIN_GROUP("gpio34", gpio34),
+ PINCTRL_PIN_GROUP("gpio35", gpio35),
+ PINCTRL_PIN_GROUP("gpio36", gpio36),
+ PINCTRL_PIN_GROUP("gpio37", gpio37),
+ PINCTRL_PIN_GROUP("gpio38", gpio38),
+ PINCTRL_PIN_GROUP("gpio39", gpio39),
+ PINCTRL_PIN_GROUP("gpio40", gpio40),
+ PINCTRL_PIN_GROUP("gpio41", gpio41),
+ PINCTRL_PIN_GROUP("gpio42", gpio42),
+ PINCTRL_PIN_GROUP("gpio43", gpio43),
+ PINCTRL_PIN_GROUP("gpio44", gpio44),
+ PINCTRL_PIN_GROUP("gpio45", gpio45),
+ PINCTRL_PIN_GROUP("gpio46", gpio46),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+ PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2),
};
static const char *const pon_groups[] = { "pon" };
@@ -1142,7 +1142,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
PINCTRL_FUNC_DESC("sipo", sipo),
@@ -1169,7 +1169,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
@@ -1230,7 +1230,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
@@ -1291,7 +1291,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
@@ -1352,7 +1352,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
@@ -1413,45 +1413,45 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
};
-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
- .pins = en7581_pinctrl_pins,
- .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
- .grps = en7581_pinctrl_groups,
- .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
- .funcs = en7581_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = en7581_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
},
[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = en7581_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = en7581_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = en7581_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
},
[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = en7581_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
},
},
};
static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+ { .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
--
2.53.0
^ permalink raw reply related
* [PATCH v3 07/13] pinctrl: airoha: split driver on shared code and SoC specific drivers
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
Split combined an7581/an7583 source file on a
* shared pinctrl code (pinctrl-airoha.c)
* an7581 specific pinctrl driver (pinctrl-an7581.c)
* an7583 specific pinctrl driver (pinctrl-an7583.c)
No functional changes.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/Kconfig | 18 +-
drivers/pinctrl/airoha/Makefile | 5 +
drivers/pinctrl/airoha/airoha-common.h | 2 +
drivers/pinctrl/airoha/pinctrl-airoha.c | 2360 +----------------------
drivers/pinctrl/airoha/pinctrl-an7581.c | 1472 ++++++++++++++
drivers/pinctrl/airoha/pinctrl-an7583.c | 1453 ++++++++++++++
6 files changed, 2950 insertions(+), 2360 deletions(-)
create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 03adaeae8fc3..08038a5b11c6 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
depends on ARCH_AIROHA || COMPILE_TEST
config PINCTRL_AIROHA
- tristate "Airoha EN7581 pin control"
+ tristate "Airoha pin control"
depends on OF
- depends on ARM64 || COMPILE_TEST
+ depends on ARCH_AIROHA || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
@@ -13,8 +13,20 @@ config PINCTRL_AIROHA
select GPIOLIB
select GPIOLIB_IRQCHIP
select REGMAP_MMIO
+ imply PINCTRL_AIROHA_AN7581
+ imply PINCTRL_AIROHA_AN7583
help
Say yes here to support pin controller and gpio driver
- on Airoha EN7581 SoC.
+ on Airoha SoC.
+
+config PINCTRL_AIROHA_AN7581
+ tristate "AN7581 pinctrl"
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_AIROHA
+
+config PINCTRL_AIROHA_AN7583
+ tristate "AN7583 pinctrl"
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_AIROHA
endmenu
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index a25b744dd7a8..cfd68c45ae0f 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -1,3 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
+# shared code
obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
+
+# SoC drivers
+obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
+obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index b0c48653a0e2..abd4d2fcd227 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -198,4 +198,6 @@ struct airoha_pinctrl_match_data {
const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
};
+int airoha_pinctrl_probe(struct platform_device *pdev);
+
#endif
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index a5bcf158d711..6f7e65b7792b 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -7,367 +7,6 @@
#include "airoha-common.h"
-/* MUX */
-#define REG_GPIO_2ND_I2C_MODE 0x0214
-#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14)
-#define GPIO_I2C_MASTER_MODE_MODE BIT(13)
-#define GPIO_I2S_MODE_MASK BIT(12)
-#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
-#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
-#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
-#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
-#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
-#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
-#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
-#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
-#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
-#define PON_TOD_1PPS_MODE_MASK BIT(2)
-#define GSW_TOD_1PPS_MODE_MASK BIT(1)
-#define GPIO_2ND_I2C_MODE_MASK BIT(0)
-
-#define REG_GPIO_SPI_CS1_MODE 0x0218
-#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
-#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
-#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
-#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
-#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
-#define GPIO_PCM_SPI_MODE_MASK BIT(16)
-#define GPIO_PCM2_MODE_MASK BIT(13)
-#define GPIO_PCM1_MODE_MASK BIT(12)
-#define GPIO_PCM_INT_MODE_MASK BIT(9)
-#define GPIO_PCM_RESET_MODE_MASK BIT(8)
-#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
-#define GPIO_SPI_CS4_MODE_MASK BIT(3)
-#define GPIO_SPI_CS3_MODE_MASK BIT(2)
-#define GPIO_SPI_CS2_MODE_MASK BIT(1)
-#define GPIO_SPI_CS1_MODE_MASK BIT(0)
-
-#define REG_GPIO_PON_MODE 0x021c
-#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
-#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
-#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
-#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
-#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
-#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
-#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
-#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
-#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
-#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
-#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
-#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
-#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
-#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
-#define GPIO_PCIE_RESET2_MASK BIT(12)
-#define SIPO_RCLK_MODE_MASK BIT(11)
-#define GPIO_PCIE_RESET1_MASK BIT(10)
-#define GPIO_PCIE_RESET0_MASK BIT(9)
-#define GPIO_UART5_MODE_MASK BIT(8)
-#define GPIO_UART4_MODE_MASK BIT(7)
-#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
-#define GPIO_HSUART_MODE_MASK BIT(5)
-#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
-#define GPIO_UART2_MODE_MASK BIT(3)
-#define GPIO_SIPO_MODE_MASK BIT(2)
-#define GPIO_EMMC_MODE_MASK BIT(1)
-#define GPIO_PON_MODE_MASK BIT(0)
-
-#define REG_NPU_UART_EN 0x0224
-#define JTAG_UDI_EN_MASK BIT(4)
-#define JTAG_DFD_EN_MASK BIT(3)
-
-#define REG_FORCE_GPIO_EN 0x0228
-#define FORCE_GPIO_EN(n) BIT(n)
-
-/* LED MAP */
-#define REG_LAN_LED0_MAPPING 0x027c
-#define REG_LAN_LED1_MAPPING 0x0280
-
-#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
-#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
-
-#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
-#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
-
-#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
-#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
-
-#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
-#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
-
-#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
-#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
-
-/* CONF */
-#define REG_I2C_SDA_E2 0x001c
-#define AN7583_I2C1_SCL_E2_MASK BIT(16)
-#define AN7583_I2C1_SDA_E2_MASK BIT(15)
-#define SPI_MISO_E2_MASK BIT(14)
-#define SPI_MOSI_E2_MASK BIT(13)
-#define SPI_CLK_E2_MASK BIT(12)
-#define SPI_CS0_E2_MASK BIT(11)
-#define PCIE2_RESET_E2_MASK BIT(10)
-#define PCIE1_RESET_E2_MASK BIT(9)
-#define PCIE0_RESET_E2_MASK BIT(8)
-#define AN7583_MDIO_0_E2_MASK BIT(5)
-#define AN7583_MDC_0_E2_MASK BIT(4)
-#define UART1_RXD_E2_MASK BIT(3)
-#define UART1_TXD_E2_MASK BIT(2)
-#define I2C_SCL_E2_MASK BIT(1)
-#define I2C_SDA_E2_MASK BIT(0)
-
-#define REG_I2C_SDA_E4 0x0020
-#define AN7583_I2C1_SCL_E4_MASK BIT(16)
-#define AN7583_I2C1_SDA_E4_MASK BIT(15)
-#define SPI_MISO_E4_MASK BIT(14)
-#define SPI_MOSI_E4_MASK BIT(13)
-#define SPI_CLK_E4_MASK BIT(12)
-#define SPI_CS0_E4_MASK BIT(11)
-#define PCIE2_RESET_E4_MASK BIT(10)
-#define PCIE1_RESET_E4_MASK BIT(9)
-#define PCIE0_RESET_E4_MASK BIT(8)
-#define AN7583_MDIO_0_E4_MASK BIT(5)
-#define AN7583_MDC_0_E4_MASK BIT(4)
-#define UART1_RXD_E4_MASK BIT(3)
-#define UART1_TXD_E4_MASK BIT(2)
-#define I2C_SCL_E4_MASK BIT(1)
-#define I2C_SDA_E4_MASK BIT(0)
-
-#define REG_GPIO_L_E2 0x0024
-#define REG_GPIO_L_E4 0x0028
-#define REG_GPIO_H_E2 0x002c
-#define REG_GPIO_H_E4 0x0030
-
-#define REG_I2C_SDA_PU 0x0044
-#define AN7583_I2C1_SCL_PU_MASK BIT(16)
-#define AN7583_I2C1_SDA_PU_MASK BIT(15)
-#define SPI_MISO_PU_MASK BIT(14)
-#define SPI_MOSI_PU_MASK BIT(13)
-#define SPI_CLK_PU_MASK BIT(12)
-#define SPI_CS0_PU_MASK BIT(11)
-#define PCIE2_RESET_PU_MASK BIT(10)
-#define PCIE1_RESET_PU_MASK BIT(9)
-#define PCIE0_RESET_PU_MASK BIT(8)
-#define AN7583_MDIO_0_PU_MASK BIT(5)
-#define AN7583_MDC_0_PU_MASK BIT(4)
-#define UART1_RXD_PU_MASK BIT(3)
-#define UART1_TXD_PU_MASK BIT(2)
-#define I2C_SCL_PU_MASK BIT(1)
-#define I2C_SDA_PU_MASK BIT(0)
-
-#define REG_I2C_SDA_PD 0x0048
-#define AN7583_I2C1_SCL_PD_MASK BIT(16)
-#define AN7583_I2C1_SDA_PD_MASK BIT(15)
-#define SPI_MISO_PD_MASK BIT(14)
-#define SPI_MOSI_PD_MASK BIT(13)
-#define SPI_CLK_PD_MASK BIT(12)
-#define SPI_CS0_PD_MASK BIT(11)
-#define PCIE2_RESET_PD_MASK BIT(10)
-#define PCIE1_RESET_PD_MASK BIT(9)
-#define PCIE0_RESET_PD_MASK BIT(8)
-#define AN7583_MDIO_0_PD_MASK BIT(5)
-#define AN7583_MDC_0_PD_MASK BIT(4)
-#define UART1_RXD_PD_MASK BIT(3)
-#define UART1_TXD_PD_MASK BIT(2)
-#define I2C_SCL_PD_MASK BIT(1)
-#define I2C_SDA_PD_MASK BIT(0)
-
-#define REG_GPIO_L_PU 0x004c
-#define REG_GPIO_L_PD 0x0050
-#define REG_GPIO_H_PU 0x0054
-#define REG_GPIO_H_PD 0x0058
-
-#define REG_PCIE_RESET_OD 0x018c
-#define PCIE2_RESET_OD_MASK BIT(2)
-#define PCIE1_RESET_OD_MASK BIT(1)
-#define PCIE0_RESET_OD_MASK BIT(0)
-
-/* GPIOs */
-#define REG_GPIO_CTRL 0x0000
-#define REG_GPIO_DATA 0x0004
-#define REG_GPIO_INT 0x0008
-#define REG_GPIO_INT_EDGE 0x000c
-#define REG_GPIO_INT_LEVEL 0x0010
-#define REG_GPIO_OE 0x0014
-#define REG_GPIO_CTRL1 0x0020
-#define REG_GPIO_CTRL2 0x0060
-#define REG_GPIO_CTRL3 0x0064
-
-/* PWM MODE CONF */
-#define REG_GPIO_FLASH_MODE_CFG 0x0034
-#define GPIO15_FLASH_MODE_CFG BIT(15)
-#define GPIO14_FLASH_MODE_CFG BIT(14)
-#define GPIO13_FLASH_MODE_CFG BIT(13)
-#define GPIO12_FLASH_MODE_CFG BIT(12)
-#define GPIO11_FLASH_MODE_CFG BIT(11)
-#define GPIO10_FLASH_MODE_CFG BIT(10)
-#define GPIO9_FLASH_MODE_CFG BIT(9)
-#define GPIO8_FLASH_MODE_CFG BIT(8)
-#define GPIO7_FLASH_MODE_CFG BIT(7)
-#define GPIO6_FLASH_MODE_CFG BIT(6)
-#define GPIO5_FLASH_MODE_CFG BIT(5)
-#define GPIO4_FLASH_MODE_CFG BIT(4)
-#define GPIO3_FLASH_MODE_CFG BIT(3)
-#define GPIO2_FLASH_MODE_CFG BIT(2)
-#define GPIO1_FLASH_MODE_CFG BIT(1)
-#define GPIO0_FLASH_MODE_CFG BIT(0)
-
-/* PWM MODE CONF EXT */
-#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
-#define GPIO51_FLASH_MODE_CFG BIT(31)
-#define GPIO50_FLASH_MODE_CFG BIT(30)
-#define GPIO49_FLASH_MODE_CFG BIT(29)
-#define GPIO48_FLASH_MODE_CFG BIT(28)
-#define GPIO47_FLASH_MODE_CFG BIT(27)
-#define GPIO46_FLASH_MODE_CFG BIT(26)
-#define GPIO45_FLASH_MODE_CFG BIT(25)
-#define GPIO44_FLASH_MODE_CFG BIT(24)
-#define GPIO43_FLASH_MODE_CFG BIT(23)
-#define GPIO42_FLASH_MODE_CFG BIT(22)
-#define GPIO41_FLASH_MODE_CFG BIT(21)
-#define GPIO40_FLASH_MODE_CFG BIT(20)
-#define GPIO39_FLASH_MODE_CFG BIT(19)
-#define GPIO38_FLASH_MODE_CFG BIT(18)
-#define GPIO37_FLASH_MODE_CFG BIT(17)
-#define GPIO36_FLASH_MODE_CFG BIT(16)
-#define GPIO31_FLASH_MODE_CFG BIT(15)
-#define GPIO30_FLASH_MODE_CFG BIT(14)
-#define GPIO29_FLASH_MODE_CFG BIT(13)
-#define GPIO28_FLASH_MODE_CFG BIT(12)
-#define GPIO27_FLASH_MODE_CFG BIT(11)
-#define GPIO26_FLASH_MODE_CFG BIT(10)
-#define GPIO25_FLASH_MODE_CFG BIT(9)
-#define GPIO24_FLASH_MODE_CFG BIT(8)
-#define GPIO23_FLASH_MODE_CFG BIT(7)
-#define GPIO22_FLASH_MODE_CFG BIT(6)
-#define GPIO21_FLASH_MODE_CFG BIT(5)
-#define GPIO20_FLASH_MODE_CFG BIT(4)
-#define GPIO19_FLASH_MODE_CFG BIT(3)
-#define GPIO18_FLASH_MODE_CFG BIT(2)
-#define GPIO17_FLASH_MODE_CFG BIT(1)
-#define GPIO16_FLASH_MODE_CFG BIT(0)
-
-#define REG_GPIO_DATA1 0x0070
-#define REG_GPIO_OE1 0x0078
-#define REG_GPIO_INT1 0x007c
-#define REG_GPIO_INT_EDGE1 0x0080
-#define REG_GPIO_INT_EDGE2 0x0084
-#define REG_GPIO_INT_EDGE3 0x0088
-#define REG_GPIO_INT_LEVEL1 0x008c
-#define REG_GPIO_INT_LEVEL2 0x0090
-#define REG_GPIO_INT_LEVEL3 0x0094
-
-#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- }
-
-#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- 0 \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (smux_val), \
- (smux_val) \
- }, \
- .regmap_size = 2, \
- }
-
-/* PWM */
-#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_MUX, \
- REG_GPIO_FLASH_MODE_CFG, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- } \
-
-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- } \
-
-#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (smux_val), \
- (smux_val) \
- }, \
- .regmap_size = 2, \
- }
-
-
-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED0_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED1_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
-
static const u32 gpio_data_regs[] = {
REG_GPIO_DATA,
REG_GPIO_DATA1
@@ -404,1922 +43,6 @@ static const u32 irq_edge_regs[] = {
REG_GPIO_INT_EDGE3
};
-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
- PINCTRL_PIN(0, "uart1_txd"),
- PINCTRL_PIN(1, "uart1_rxd"),
- PINCTRL_PIN(2, "i2c_scl"),
- PINCTRL_PIN(3, "i2c_sda"),
- PINCTRL_PIN(4, "spi_cs0"),
- PINCTRL_PIN(5, "spi_clk"),
- PINCTRL_PIN(6, "spi_mosi"),
- PINCTRL_PIN(7, "spi_miso"),
- PINCTRL_PIN(13, "gpio0"),
- PINCTRL_PIN(14, "gpio1"),
- PINCTRL_PIN(15, "gpio2"),
- PINCTRL_PIN(16, "gpio3"),
- PINCTRL_PIN(17, "gpio4"),
- PINCTRL_PIN(18, "gpio5"),
- PINCTRL_PIN(19, "gpio6"),
- PINCTRL_PIN(20, "gpio7"),
- PINCTRL_PIN(21, "gpio8"),
- PINCTRL_PIN(22, "gpio9"),
- PINCTRL_PIN(23, "gpio10"),
- PINCTRL_PIN(24, "gpio11"),
- PINCTRL_PIN(25, "gpio12"),
- PINCTRL_PIN(26, "gpio13"),
- PINCTRL_PIN(27, "gpio14"),
- PINCTRL_PIN(28, "gpio15"),
- PINCTRL_PIN(29, "gpio16"),
- PINCTRL_PIN(30, "gpio17"),
- PINCTRL_PIN(31, "gpio18"),
- PINCTRL_PIN(32, "gpio19"),
- PINCTRL_PIN(33, "gpio20"),
- PINCTRL_PIN(34, "gpio21"),
- PINCTRL_PIN(35, "gpio22"),
- PINCTRL_PIN(36, "gpio23"),
- PINCTRL_PIN(37, "gpio24"),
- PINCTRL_PIN(38, "gpio25"),
- PINCTRL_PIN(39, "gpio26"),
- PINCTRL_PIN(40, "gpio27"),
- PINCTRL_PIN(41, "gpio28"),
- PINCTRL_PIN(42, "gpio29"),
- PINCTRL_PIN(43, "gpio30"),
- PINCTRL_PIN(44, "gpio31"),
- PINCTRL_PIN(45, "gpio32"),
- PINCTRL_PIN(46, "gpio33"),
- PINCTRL_PIN(47, "gpio34"),
- PINCTRL_PIN(48, "gpio35"),
- PINCTRL_PIN(49, "gpio36"),
- PINCTRL_PIN(50, "gpio37"),
- PINCTRL_PIN(51, "gpio38"),
- PINCTRL_PIN(52, "gpio39"),
- PINCTRL_PIN(53, "gpio40"),
- PINCTRL_PIN(54, "gpio41"),
- PINCTRL_PIN(55, "gpio42"),
- PINCTRL_PIN(56, "gpio43"),
- PINCTRL_PIN(57, "pcie_reset0"),
- PINCTRL_PIN(58, "pcie_reset1"),
- PINCTRL_PIN(59, "pcie_reset2"),
-};
-
-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int en7581_pon_tod_1pps_pins[] = { 46 };
-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-static const int en7581_sipo_pins[] = { 16, 17 };
-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-static const int en7581_mdio_pins[] = { 14, 15 };
-static const int en7581_uart2_pins[] = { 48, 55 };
-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-static const int en7581_hsuart_pins[] = { 28, 29 };
-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-static const int en7581_uart4_pins[] = { 38, 39 };
-static const int en7581_uart5_pins[] = { 18, 19 };
-static const int en7581_i2c0_pins[] = { 2, 3 };
-static const int en7581_i2c1_pins[] = { 14, 15 };
-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-static const int en7581_spi_quad_pins[] = { 32, 33 };
-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-static const int en7581_spi_cs1_pins[] = { 34 };
-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int en7581_pcm_spi_int_pins[] = { 14 };
-static const int en7581_pcm_spi_rst_pins[] = { 15 };
-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
-static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
-static const int en7581_gpio0_pins[] = { 13 };
-static const int en7581_gpio1_pins[] = { 14 };
-static const int en7581_gpio2_pins[] = { 15 };
-static const int en7581_gpio3_pins[] = { 16 };
-static const int en7581_gpio4_pins[] = { 17 };
-static const int en7581_gpio5_pins[] = { 18 };
-static const int en7581_gpio6_pins[] = { 19 };
-static const int en7581_gpio7_pins[] = { 20 };
-static const int en7581_gpio8_pins[] = { 21 };
-static const int en7581_gpio9_pins[] = { 22 };
-static const int en7581_gpio10_pins[] = { 23 };
-static const int en7581_gpio11_pins[] = { 24 };
-static const int en7581_gpio12_pins[] = { 25 };
-static const int en7581_gpio13_pins[] = { 26 };
-static const int en7581_gpio14_pins[] = { 27 };
-static const int en7581_gpio15_pins[] = { 28 };
-static const int en7581_gpio16_pins[] = { 29 };
-static const int en7581_gpio17_pins[] = { 30 };
-static const int en7581_gpio18_pins[] = { 31 };
-static const int en7581_gpio19_pins[] = { 32 };
-static const int en7581_gpio20_pins[] = { 33 };
-static const int en7581_gpio21_pins[] = { 34 };
-static const int en7581_gpio22_pins[] = { 35 };
-static const int en7581_gpio23_pins[] = { 36 };
-static const int en7581_gpio24_pins[] = { 37 };
-static const int en7581_gpio25_pins[] = { 38 };
-static const int en7581_gpio26_pins[] = { 39 };
-static const int en7581_gpio27_pins[] = { 40 };
-static const int en7581_gpio28_pins[] = { 41 };
-static const int en7581_gpio29_pins[] = { 42 };
-static const int en7581_gpio30_pins[] = { 43 };
-static const int en7581_gpio31_pins[] = { 44 };
-static const int en7581_gpio32_pins[] = { 45 };
-static const int en7581_gpio33_pins[] = { 46 };
-static const int en7581_gpio34_pins[] = { 47 };
-static const int en7581_gpio35_pins[] = { 48 };
-static const int en7581_gpio36_pins[] = { 49 };
-static const int en7581_gpio37_pins[] = { 50 };
-static const int en7581_gpio38_pins[] = { 51 };
-static const int en7581_gpio39_pins[] = { 52 };
-static const int en7581_gpio40_pins[] = { 53 };
-static const int en7581_gpio41_pins[] = { 54 };
-static const int en7581_gpio42_pins[] = { 55 };
-static const int en7581_gpio43_pins[] = { 56 };
-static const int en7581_gpio44_pins[] = { 57 };
-static const int en7581_gpio45_pins[] = { 58 };
-static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_pcie_reset0_pins[] = { 57 };
-static const int en7581_pcie_reset1_pins[] = { 58 };
-static const int en7581_pcie_reset2_pins[] = { 59 };
-
-static const struct pingroup en7581_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", en7581_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", en7581_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", en7581_mdio),
- PINCTRL_PIN_GROUP("uart2", en7581_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("uart4", en7581_uart4),
- PINCTRL_PIN_GROUP("uart5", en7581_uart5),
- PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
- PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
- PINCTRL_PIN_GROUP("i2s", en7581_i2s),
- PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
- PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
- PINCTRL_PIN_GROUP("spi", en7581_spi),
- PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
- PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
- PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
- PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
- PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
- PINCTRL_PIN_GROUP("emmc", en7581_emmc),
- PINCTRL_PIN_GROUP("pnand", en7581_pnand),
- PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
- PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
- PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
- PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
- PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
- PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
- PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
- PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
- PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
- PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
- PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
- PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
- PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
- PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
- PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
- PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
- PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
- PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
- PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
- PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
- PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
- PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
- PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
- PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
- PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
- PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
- PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
- PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
- PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
- PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
- PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
- PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
- PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
- PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
- PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
- PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
- PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
- PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
- PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
- PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
- PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
- PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
- PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
- PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
- PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
- PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
- PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
- PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
- PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
-};
-
-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
- PINCTRL_PIN(2, "gpio0"),
- PINCTRL_PIN(3, "gpio1"),
- PINCTRL_PIN(4, "gpio2"),
- PINCTRL_PIN(5, "gpio3"),
- PINCTRL_PIN(6, "gpio4"),
- PINCTRL_PIN(7, "gpio5"),
- PINCTRL_PIN(8, "gpio6"),
- PINCTRL_PIN(9, "gpio7"),
- PINCTRL_PIN(10, "gpio8"),
- PINCTRL_PIN(11, "gpio9"),
- PINCTRL_PIN(12, "gpio10"),
- PINCTRL_PIN(13, "gpio11"),
- PINCTRL_PIN(14, "gpio12"),
- PINCTRL_PIN(15, "gpio13"),
- PINCTRL_PIN(16, "gpio14"),
- PINCTRL_PIN(17, "gpio15"),
- PINCTRL_PIN(18, "gpio16"),
- PINCTRL_PIN(19, "gpio17"),
- PINCTRL_PIN(20, "gpio18"),
- PINCTRL_PIN(21, "gpio19"),
- PINCTRL_PIN(22, "gpio20"),
- PINCTRL_PIN(23, "gpio21"),
- PINCTRL_PIN(24, "gpio22"),
- PINCTRL_PIN(25, "gpio23"),
- PINCTRL_PIN(26, "gpio24"),
- PINCTRL_PIN(27, "gpio25"),
- PINCTRL_PIN(28, "gpio26"),
- PINCTRL_PIN(29, "gpio27"),
- PINCTRL_PIN(30, "gpio28"),
- PINCTRL_PIN(31, "gpio29"),
- PINCTRL_PIN(32, "gpio30"),
- PINCTRL_PIN(33, "gpio31"),
- PINCTRL_PIN(34, "gpio32"),
- PINCTRL_PIN(35, "gpio33"),
- PINCTRL_PIN(36, "gpio34"),
- PINCTRL_PIN(37, "gpio35"),
- PINCTRL_PIN(38, "gpio36"),
- PINCTRL_PIN(39, "gpio37"),
- PINCTRL_PIN(40, "gpio38"),
- PINCTRL_PIN(41, "i2c0_scl"),
- PINCTRL_PIN(42, "i2c0_sda"),
- PINCTRL_PIN(43, "i2c1_scl"),
- PINCTRL_PIN(44, "i2c1_sda"),
- PINCTRL_PIN(45, "spi_clk"),
- PINCTRL_PIN(46, "spi_cs"),
- PINCTRL_PIN(47, "spi_mosi"),
- PINCTRL_PIN(48, "spi_miso"),
- PINCTRL_PIN(49, "uart_txd"),
- PINCTRL_PIN(50, "uart_rxd"),
- PINCTRL_PIN(51, "pcie_reset0"),
- PINCTRL_PIN(52, "pcie_reset1"),
- PINCTRL_PIN(53, "mdc_0"),
- PINCTRL_PIN(54, "mdio_0"),
-};
-
-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-static const int an7583_pon_tod_1pps_pins[] = { 32 };
-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-static const int an7583_sipo_pins[] = { 34, 35 };
-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-static const int an7583_mdio_pins[] = { 43, 44 };
-static const int an7583_uart2_pins[] = { 34, 35 };
-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-static const int an7583_hsuart_pins[] = { 30, 31 };
-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-static const int an7583_npu_uart_pins[] = { 7, 8 };
-static const int an7583_uart4_pins[] = { 7, 8 };
-static const int an7583_uart5_pins[] = { 23, 24 };
-static const int an7583_i2c0_pins[] = { 41, 42 };
-static const int an7583_i2c1_pins[] = { 43, 44 };
-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-static const int an7583_spi_quad_pins[] = { 25, 26 };
-static const int an7583_spi_cs1_pins[] = { 27 };
-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-static const int an7583_pcm_spi_rst_pins[] = { 14 };
-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
-static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
-static const int an7583_gpio0_pins[] = { 2 };
-static const int an7583_gpio1_pins[] = { 3 };
-static const int an7583_gpio2_pins[] = { 4 };
-static const int an7583_gpio3_pins[] = { 5 };
-static const int an7583_gpio4_pins[] = { 6 };
-static const int an7583_gpio5_pins[] = { 7 };
-static const int an7583_gpio6_pins[] = { 8 };
-static const int an7583_gpio7_pins[] = { 9 };
-static const int an7583_gpio8_pins[] = { 10 };
-static const int an7583_gpio9_pins[] = { 11 };
-static const int an7583_gpio10_pins[] = { 12 };
-static const int an7583_gpio11_pins[] = { 13 };
-static const int an7583_gpio12_pins[] = { 14 };
-static const int an7583_gpio13_pins[] = { 15 };
-static const int an7583_gpio14_pins[] = { 16 };
-static const int an7583_gpio15_pins[] = { 17 };
-static const int an7583_gpio16_pins[] = { 18 };
-static const int an7583_gpio17_pins[] = { 19 };
-static const int an7583_gpio18_pins[] = { 20 };
-static const int an7583_gpio19_pins[] = { 21 };
-static const int an7583_gpio20_pins[] = { 22 };
-static const int an7583_gpio21_pins[] = { 23 };
-static const int an7583_gpio22_pins[] = { 24 };
-static const int an7583_gpio23_pins[] = { 25 };
-static const int an7583_gpio24_pins[] = { 26 };
-static const int an7583_gpio25_pins[] = { 27 };
-static const int an7583_gpio26_pins[] = { 28 };
-static const int an7583_gpio27_pins[] = { 29 };
-static const int an7583_gpio28_pins[] = { 30 };
-static const int an7583_gpio29_pins[] = { 31 };
-static const int an7583_gpio30_pins[] = { 32 };
-static const int an7583_gpio31_pins[] = { 33 };
-static const int an7583_gpio32_pins[] = { 34 };
-static const int an7583_gpio33_pins[] = { 35 };
-static const int an7583_gpio34_pins[] = { 36 };
-static const int an7583_gpio35_pins[] = { 37 };
-static const int an7583_gpio36_pins[] = { 38 };
-static const int an7583_gpio37_pins[] = { 39 };
-static const int an7583_gpio38_pins[] = { 40 };
-static const int an7583_gpio39_pins[] = { 41 };
-static const int an7583_gpio40_pins[] = { 42 };
-static const int an7583_gpio41_pins[] = { 43 };
-static const int an7583_gpio42_pins[] = { 44 };
-static const int an7583_gpio43_pins[] = { 45 };
-static const int an7583_gpio44_pins[] = { 46 };
-static const int an7583_gpio45_pins[] = { 47 };
-static const int an7583_gpio46_pins[] = { 48 };
-static const int an7583_gpio47_pins[] = { 49 };
-static const int an7583_gpio48_pins[] = { 50 };
-static const int an7583_gpio49_pins[] = { 51 };
-static const int an7583_gpio50_pins[] = { 52 };
-static const int an7583_gpio51_pins[] = { 53 };
-static const int an7583_gpio52_pins[] = { 54 };
-static const int an7583_pcie_reset0_pins[] = { 51 };
-static const int an7583_pcie_reset1_pins[] = { 52 };
-
-static const struct pingroup an7583_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", an7583_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", an7583_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", an7583_mdio),
- PINCTRL_PIN_GROUP("uart2", an7583_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
- PINCTRL_PIN_GROUP("uart4", an7583_uart4),
- PINCTRL_PIN_GROUP("uart5", an7583_uart5),
- PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
- PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
- PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
- PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
- PINCTRL_PIN_GROUP("spi", an7583_spi),
- PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("emmc", an7583_emmc),
- PINCTRL_PIN_GROUP("pnand", an7583_pnand),
- PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
- PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
- PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
- PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
- PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
- PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
- PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
- PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
- PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
- PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
- PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
- PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
- PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
- PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
- PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
- PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
- PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
- PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
- PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
- PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
- PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
- PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
- PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
- PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
- PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
- PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
- PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
- PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
- PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
- PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
- PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
- PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
- PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
- PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
- PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
- PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
- PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
- PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
- PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
- PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
- PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
- PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
- PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
- PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
- PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
- PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
- PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
- PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
- PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
- PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
- PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
- PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
- PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
- PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
-};
-
-static const char *const pon_groups[] = { "pon" };
-static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
-static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
-static const char *const mdio_groups[] = { "mdio" };
-static const char *const an7583_mdio_groups[] = { "mdio" };
-static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
- "hsuart_cts_rts", "uart4",
- "uart5" };
-static const char *const i2c_groups[] = { "i2c1" };
-static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
-static const char *const pcm_groups[] = { "pcm1", "pcm2" };
-static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
- "pcm_spi_rst", "pcm_spi_cs1",
- "pcm_spi_cs2_p156",
- "pcm_spi_cs2_p128",
- "pcm_spi_cs3", "pcm_spi_cs4" };
-static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
- "pcm_spi_rst", "pcm_spi_cs1" };
-static const char *const i2s_groups[] = { "i2s" };
-static const char *const emmc_groups[] = { "emmc" };
-static const char *const pnand_groups[] = { "pnand" };
-static const char *const gpio_groups[] = { "gpio44", "gpio45", "gpio46" };
-static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
- "pcie_reset2" };
-static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
- "gpio42", "gpio43", "gpio44",
- "gpio45", "gpio46", "gpio47",
- "gpio48", "gpio49", "gpio50",
- "gpio51", "gpio52" };
-static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
-static const char *const pwm_groups[] = { "gpio0", "gpio1",
- "gpio2", "gpio3",
- "gpio4", "gpio5",
- "gpio6", "gpio7",
- "gpio8", "gpio9",
- "gpio10", "gpio11",
- "gpio12", "gpio13",
- "gpio14", "gpio15",
- "gpio16", "gpio17",
- "gpio18", "gpio19",
- "gpio20", "gpio21",
- "gpio22", "gpio23",
- "gpio24", "gpio25",
- "gpio26", "gpio27",
- "gpio28", "gpio29",
- "gpio30", "gpio31",
- "gpio36", "gpio37",
- "gpio38", "gpio39",
- "gpio40", "gpio41",
- "gpio42", "gpio43",
- "gpio44", "gpio45",
- "gpio46" };
-static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
- "gpio2", "gpio3",
- "gpio4", "gpio5",
- "gpio6", "gpio7",
- "gpio8", "gpio9",
- "gpio10", "gpio11",
- "gpio12", "gpio13",
- "gpio14", "gpio15",
- "gpio16", "gpio17",
- "gpio18", "gpio19",
- "gpio20", "gpio21",
- "gpio22", "gpio23",
- "gpio24", "gpio25",
- "gpio26", "gpio27",
- "gpio28", "gpio29",
- "gpio30", "gpio31",
- "gpio36", "gpio37",
- "gpio38", "gpio39",
- "gpio40", "gpio41",
- "gpio42", "gpio43",
- "gpio44", "gpio45",
- "gpio46", "gpio47",
- "gpio48", "gpio49",
- "gpio50", "gpio51" };
-static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-
-static const struct airoha_pinctrl_func_group pon_func_group[] = {
- {
- .name = "pon",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PON_MODE_MASK,
- GPIO_PON_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
- {
- .name = "pon_tod_1pps",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- PON_TOD_1PPS_MODE_MASK,
- PON_TOD_1PPS_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "gsw_tod_1pps",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GSW_TOD_1PPS_MODE_MASK,
- GSW_TOD_1PPS_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group sipo_func_group[] = {
- {
- .name = "sipo",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
- GPIO_SIPO_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "sipo_rclk",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
- GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group mdio_func_group[] = {
- {
- .name = "mdio",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GPIO_MDC_IO_MASTER_MODE_MASK,
- GPIO_MDC_IO_MASTER_MODE_MASK
- },
- .regmap[1] = {
- AIROHA_FUNC_MUX,
- REG_FORCE_GPIO_EN,
- FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
- FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
- },
- .regmap_size = 2,
- },
-};
-
-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
- {
- .name = "mdio",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_SGMII_MDIO_MODE_MASK,
- GPIO_SGMII_MDIO_MODE_MASK
- },
- .regmap[1] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_MDC_IO_MASTER_MODE_MASK,
- GPIO_MDC_IO_MASTER_MODE_MASK
- },
- .regmap_size = 2,
- },
-};
-
-static const struct airoha_pinctrl_func_group uart_func_group[] = {
- {
- .name = "uart2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART2_MODE_MASK,
- GPIO_UART2_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "uart2_cts_rts",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
- GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "hsuart",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
- GPIO_HSUART_MODE_MASK
- },
- .regmap_size = 1,
- },
- {
- .name = "hsuart_cts_rts",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
- GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "uart4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART4_MODE_MASK,
- GPIO_UART4_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "uart5",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART5_MODE_MASK,
- GPIO_UART5_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group i2c_func_group[] = {
- {
- .name = "i2c1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GPIO_2ND_I2C_MODE_MASK,
- GPIO_2ND_I2C_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group jtag_func_group[] = {
- {
- .name = "jtag_udi",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
- JTAG_UDI_EN_MASK,
- JTAG_UDI_EN_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "jtag_dfd",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
- JTAG_DFD_EN_MASK,
- JTAG_DFD_EN_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pcm_func_group[] = {
- {
- .name = "pcm1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM1_MODE_MASK,
- GPIO_PCM1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM2_MODE_MASK,
- GPIO_PCM2_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group spi_func_group[] = {
- {
- .name = "spi_quad",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_QUAD_MODE_MASK,
- GPIO_SPI_QUAD_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS1_MODE_MASK,
- GPIO_SPI_CS1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS2_MODE_MASK,
- GPIO_SPI_CS2_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs3",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS3_MODE_MASK,
- GPIO_SPI_CS3_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS4_MODE_MASK,
- GPIO_SPI_CS4_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
- {
- .name = "pcm_spi",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_MODE_MASK,
- GPIO_PCM_SPI_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_int",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_INT_MODE_MASK,
- GPIO_PCM_INT_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_rst",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_RESET_MODE_MASK,
- GPIO_PCM_RESET_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS1_MODE_MASK,
- GPIO_PCM_SPI_CS1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs2_p128",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS2_MODE_P128_MASK,
- GPIO_PCM_SPI_CS2_MODE_P128_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs2_p156",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS2_MODE_P156_MASK,
- GPIO_PCM_SPI_CS2_MODE_P156_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs3",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS3_MODE_MASK,
- GPIO_PCM_SPI_CS3_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS4_MODE_MASK,
- GPIO_PCM_SPI_CS4_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
- {
- .name = "pcm_spi",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_MODE_MASK,
- GPIO_PCM_SPI_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_int",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_INT_MODE_MASK,
- GPIO_PCM_INT_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_rst",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_RESET_MODE_MASK,
- GPIO_PCM_RESET_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS1_MODE_MASK,
- GPIO_PCM_SPI_CS1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs3",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS3_MODE_MASK,
- GPIO_PCM_SPI_CS3_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS4_MODE_MASK,
- GPIO_PCM_SPI_CS4_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group i2s_func_group[] = {
- {
- .name = "i2s",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GPIO_I2S_MODE_MASK,
- GPIO_I2S_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group emmc_func_group[] = {
- {
- .name = "emmc",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_EMMC_MODE_MASK,
- GPIO_EMMC_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pnand_func_group[] = {
- {
- .name = "pnand",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PARALLEL_NAND_MODE_MASK,
- GPIO_PARALLEL_NAND_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group gpio_func_group[] = {
- AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
- GPIO_PCIE_RESET2_MASK),
-};
-
-static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
- {
- .name = "pcie_reset0",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET0_MASK,
- 0
- },
- .regmap_size = 1,
- }, {
- .name = "pcie_reset1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET1_MASK,
- 0
- },
- .regmap_size = 1,
- }, {
- .name = "pcie_reset2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET2_MASK,
- 0
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
- AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
-};
-
-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
- {
- .name = "pcie_reset0",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET0_MASK,
- 0
- },
- .regmap_size = 1,
- }, {
- .name = "pcie_reset1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET1_MASK,
- 0
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pwm_func_group[] = {
- AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
- GPIO_PCIE_RESET2_MASK),
-};
-
-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
- AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
-};
-
-static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
- PINCTRL_FUNC_DESC("pon", pon),
- PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
- PINCTRL_FUNC_DESC("sipo", sipo),
- PINCTRL_FUNC_DESC("mdio", mdio),
- PINCTRL_FUNC_DESC("uart", uart),
- PINCTRL_FUNC_DESC("i2c", i2c),
- PINCTRL_FUNC_DESC("jtag", jtag),
- PINCTRL_FUNC_DESC("pcm", pcm),
- PINCTRL_FUNC_DESC("spi", spi),
- PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
- PINCTRL_FUNC_DESC("i2s", i2s),
- PINCTRL_FUNC_DESC("emmc", emmc),
- PINCTRL_FUNC_DESC("pnand", pnand),
- PINCTRL_FUNC_DESC("gpio", gpio),
- PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
- PINCTRL_FUNC_DESC("pwm", pwm),
- PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
- PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
- PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
- PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
- PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
- PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
- PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
- PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
-};
-
-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
- PINCTRL_FUNC_DESC("pon", pon),
- PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
- PINCTRL_FUNC_DESC("sipo", sipo),
- PINCTRL_FUNC_DESC("mdio", an7583_mdio),
- PINCTRL_FUNC_DESC("uart", uart),
- PINCTRL_FUNC_DESC("jtag", jtag),
- PINCTRL_FUNC_DESC("pcm", pcm),
- PINCTRL_FUNC_DESC("spi", spi),
- PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
- PINCTRL_FUNC_DESC("emmc", emmc),
- PINCTRL_FUNC_DESC("pnand", pnand),
- PINCTRL_FUNC_DESC("gpio", an7583_gpio),
- PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
- PINCTRL_FUNC_DESC("pwm", an7583_pwm),
- PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
- PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
- PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
- PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
- PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
- PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
- PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
- PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
- PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
- PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
- PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
- PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
- PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
- PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
-};
-
static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
int pin)
@@ -2910,7 +633,7 @@ static const struct pinctrl_ops airoha_pctlops = {
.dt_free_map = pinconf_generic_dt_free_map,
};
-static int airoha_pinctrl_probe(struct platform_device *pdev)
+int airoha_pinctrl_probe(struct platform_device *pdev)
{
const struct airoha_pinctrl_match_data *data;
struct device *dev = &pdev->dev;
@@ -2988,87 +711,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
/* build gpio-chip */
return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
}
-
-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
- .pins = en7581_pinctrl_pins,
- .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
- .grps = en7581_pinctrl_groups,
- .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
- .funcs = en7581_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
- .confs_info = {
- [AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = en7581_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
- },
- [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = en7581_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = en7581_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = en7581_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
- },
- [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = en7581_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
- },
- },
-};
-
-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
- .pins = an7583_pinctrl_pins,
- .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
- .grps = an7583_pinctrl_groups,
- .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
- .funcs = an7583_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
- .confs_info = {
- [AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = an7583_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
- },
- [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = an7583_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = an7583_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = an7583_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
- },
- [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = an7583_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
- },
- },
-};
-
-static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
- { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
-
-static struct platform_driver airoha_pinctrl_driver = {
- .probe = airoha_pinctrl_probe,
- .driver = {
- .name = "pinctrl-airoha",
- .of_match_table = airoha_pinctrl_of_match,
- },
-};
-module_platform_driver(airoha_pinctrl_driver);
+EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
-MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
+MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
new file mode 100644
index 000000000000..355d557dbdce
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -0,0 +1,1472 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14)
+#define GPIO_I2C_MASTER_MODE_MODE BIT(13)
+#define GPIO_I2S_MODE_MASK BIT(12)
+#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define PON_TOD_1PPS_MODE_MASK BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+#define GPIO_2ND_I2C_MODE_MASK BIT(0)
+
+#define REG_GPIO_SPI_CS1_MODE 0x0218
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x021c
+#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define GPIO_PCIE_RESET2_MASK BIT(12)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+#define GPIO_PCIE_RESET1_MASK BIT(10)
+#define GPIO_PCIE_RESET0_MASK BIT(9)
+#define GPIO_UART5_MODE_MASK BIT(8)
+#define GPIO_UART4_MODE_MASK BIT(7)
+#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
+#define GPIO_HSUART_MODE_MASK BIT(5)
+#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
+#define GPIO_UART2_MODE_MASK BIT(3)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_EMMC_MODE_MASK BIT(1)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+#define REG_NPU_UART_EN 0x0224
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+
+#define REG_FORCE_GPIO_EN 0x0228
+#define FORCE_GPIO_EN(n) BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING 0x027c
+#define REG_LAN_LED1_MAPPING 0x0280
+
+#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
+#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2 0x001c
+#define SPI_MISO_E2_MASK BIT(14)
+#define SPI_MOSI_E2_MASK BIT(13)
+#define SPI_CLK_E2_MASK BIT(12)
+#define SPI_CS0_E2_MASK BIT(11)
+#define PCIE2_RESET_E2_MASK BIT(10)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define SPI_MISO_E4_MASK BIT(14)
+#define SPI_MOSI_E4_MASK BIT(13)
+#define SPI_CLK_E4_MASK BIT(12)
+#define SPI_CS0_E4_MASK BIT(11)
+#define PCIE2_RESET_E4_MASK BIT(10)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+#define REG_GPIO_H_E2 0x002c
+#define REG_GPIO_H_E4 0x0030
+
+#define REG_I2C_SDA_PU 0x0044
+#define SPI_MISO_PU_MASK BIT(14)
+#define SPI_MOSI_PU_MASK BIT(13)
+#define SPI_CLK_PU_MASK BIT(12)
+#define SPI_CS0_PU_MASK BIT(11)
+#define PCIE2_RESET_PU_MASK BIT(10)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define SPI_MISO_PD_MASK BIT(14)
+#define SPI_MOSI_PD_MASK BIT(13)
+#define SPI_CLK_PD_MASK BIT(12)
+#define SPI_CS0_PD_MASK BIT(11)
+#define PCIE2_RESET_PD_MASK BIT(10)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+#define REG_GPIO_H_PU 0x0054
+#define REG_GPIO_H_PD 0x0058
+
+#define REG_PCIE_RESET_OD 0x018c
+#define PCIE2_RESET_OD_MASK BIT(2)
+#define PCIE1_RESET_OD_MASK BIT(1)
+#define PCIE0_RESET_OD_MASK BIT(0)
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO51_FLASH_MODE_CFG BIT(31)
+#define GPIO50_FLASH_MODE_CFG BIT(30)
+#define GPIO49_FLASH_MODE_CFG BIT(29)
+#define GPIO48_FLASH_MODE_CFG BIT(28)
+#define GPIO47_FLASH_MODE_CFG BIT(27)
+#define GPIO46_FLASH_MODE_CFG BIT(26)
+#define GPIO45_FLASH_MODE_CFG BIT(25)
+#define GPIO44_FLASH_MODE_CFG BIT(24)
+#define GPIO43_FLASH_MODE_CFG BIT(23)
+#define GPIO42_FLASH_MODE_CFG BIT(22)
+#define GPIO41_FLASH_MODE_CFG BIT(21)
+#define GPIO40_FLASH_MODE_CFG BIT(20)
+#define GPIO39_FLASH_MODE_CFG BIT(19)
+#define GPIO38_FLASH_MODE_CFG BIT(18)
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+ PINCTRL_PIN(0, "uart1_txd"),
+ PINCTRL_PIN(1, "uart1_rxd"),
+ PINCTRL_PIN(2, "i2c_scl"),
+ PINCTRL_PIN(3, "i2c_sda"),
+ PINCTRL_PIN(4, "spi_cs0"),
+ PINCTRL_PIN(5, "spi_clk"),
+ PINCTRL_PIN(6, "spi_mosi"),
+ PINCTRL_PIN(7, "spi_miso"),
+ PINCTRL_PIN(13, "gpio0"),
+ PINCTRL_PIN(14, "gpio1"),
+ PINCTRL_PIN(15, "gpio2"),
+ PINCTRL_PIN(16, "gpio3"),
+ PINCTRL_PIN(17, "gpio4"),
+ PINCTRL_PIN(18, "gpio5"),
+ PINCTRL_PIN(19, "gpio6"),
+ PINCTRL_PIN(20, "gpio7"),
+ PINCTRL_PIN(21, "gpio8"),
+ PINCTRL_PIN(22, "gpio9"),
+ PINCTRL_PIN(23, "gpio10"),
+ PINCTRL_PIN(24, "gpio11"),
+ PINCTRL_PIN(25, "gpio12"),
+ PINCTRL_PIN(26, "gpio13"),
+ PINCTRL_PIN(27, "gpio14"),
+ PINCTRL_PIN(28, "gpio15"),
+ PINCTRL_PIN(29, "gpio16"),
+ PINCTRL_PIN(30, "gpio17"),
+ PINCTRL_PIN(31, "gpio18"),
+ PINCTRL_PIN(32, "gpio19"),
+ PINCTRL_PIN(33, "gpio20"),
+ PINCTRL_PIN(34, "gpio21"),
+ PINCTRL_PIN(35, "gpio22"),
+ PINCTRL_PIN(36, "gpio23"),
+ PINCTRL_PIN(37, "gpio24"),
+ PINCTRL_PIN(38, "gpio25"),
+ PINCTRL_PIN(39, "gpio26"),
+ PINCTRL_PIN(40, "gpio27"),
+ PINCTRL_PIN(41, "gpio28"),
+ PINCTRL_PIN(42, "gpio29"),
+ PINCTRL_PIN(43, "gpio30"),
+ PINCTRL_PIN(44, "gpio31"),
+ PINCTRL_PIN(45, "gpio32"),
+ PINCTRL_PIN(46, "gpio33"),
+ PINCTRL_PIN(47, "gpio34"),
+ PINCTRL_PIN(48, "gpio35"),
+ PINCTRL_PIN(49, "gpio36"),
+ PINCTRL_PIN(50, "gpio37"),
+ PINCTRL_PIN(51, "gpio38"),
+ PINCTRL_PIN(52, "gpio39"),
+ PINCTRL_PIN(53, "gpio40"),
+ PINCTRL_PIN(54, "gpio41"),
+ PINCTRL_PIN(55, "gpio42"),
+ PINCTRL_PIN(56, "gpio43"),
+ PINCTRL_PIN(57, "pcie_reset0"),
+ PINCTRL_PIN(58, "pcie_reset1"),
+ PINCTRL_PIN(59, "pcie_reset2"),
+};
+
+static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int en7581_pon_tod_1pps_pins[] = { 46 };
+static const int en7581_gsw_tod_1pps_pins[] = { 46 };
+static const int en7581_sipo_pins[] = { 16, 17 };
+static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
+static const int en7581_mdio_pins[] = { 14, 15 };
+static const int en7581_uart2_pins[] = { 48, 55 };
+static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
+static const int en7581_hsuart_pins[] = { 28, 29 };
+static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
+static const int en7581_uart4_pins[] = { 38, 39 };
+static const int en7581_uart5_pins[] = { 18, 19 };
+static const int en7581_i2c0_pins[] = { 2, 3 };
+static const int en7581_i2c1_pins[] = { 14, 15 };
+static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
+static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
+static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
+static const int en7581_spi_quad_pins[] = { 32, 33 };
+static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
+static const int en7581_spi_cs1_pins[] = { 34 };
+static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int en7581_pcm_spi_int_pins[] = { 14 };
+static const int en7581_pcm_spi_rst_pins[] = { 15 };
+static const int en7581_pcm_spi_cs1_pins[] = { 43 };
+static const int en7581_pcm_spi_cs2_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
+static const int en7581_pcm_spi_cs3_pins[] = { 41 };
+static const int en7581_pcm_spi_cs4_pins[] = { 42 };
+static const int en7581_emmc_pins[] = {
+ 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
+};
+static const int en7581_pnand_pins[] = {
+ 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
+};
+static const int en7581_gpio0_pins[] = { 13 };
+static const int en7581_gpio1_pins[] = { 14 };
+static const int en7581_gpio2_pins[] = { 15 };
+static const int en7581_gpio3_pins[] = { 16 };
+static const int en7581_gpio4_pins[] = { 17 };
+static const int en7581_gpio5_pins[] = { 18 };
+static const int en7581_gpio6_pins[] = { 19 };
+static const int en7581_gpio7_pins[] = { 20 };
+static const int en7581_gpio8_pins[] = { 21 };
+static const int en7581_gpio9_pins[] = { 22 };
+static const int en7581_gpio10_pins[] = { 23 };
+static const int en7581_gpio11_pins[] = { 24 };
+static const int en7581_gpio12_pins[] = { 25 };
+static const int en7581_gpio13_pins[] = { 26 };
+static const int en7581_gpio14_pins[] = { 27 };
+static const int en7581_gpio15_pins[] = { 28 };
+static const int en7581_gpio16_pins[] = { 29 };
+static const int en7581_gpio17_pins[] = { 30 };
+static const int en7581_gpio18_pins[] = { 31 };
+static const int en7581_gpio19_pins[] = { 32 };
+static const int en7581_gpio20_pins[] = { 33 };
+static const int en7581_gpio21_pins[] = { 34 };
+static const int en7581_gpio22_pins[] = { 35 };
+static const int en7581_gpio23_pins[] = { 36 };
+static const int en7581_gpio24_pins[] = { 37 };
+static const int en7581_gpio25_pins[] = { 38 };
+static const int en7581_gpio26_pins[] = { 39 };
+static const int en7581_gpio27_pins[] = { 40 };
+static const int en7581_gpio28_pins[] = { 41 };
+static const int en7581_gpio29_pins[] = { 42 };
+static const int en7581_gpio30_pins[] = { 43 };
+static const int en7581_gpio31_pins[] = { 44 };
+static const int en7581_gpio32_pins[] = { 45 };
+static const int en7581_gpio33_pins[] = { 46 };
+static const int en7581_gpio34_pins[] = { 47 };
+static const int en7581_gpio35_pins[] = { 48 };
+static const int en7581_gpio36_pins[] = { 49 };
+static const int en7581_gpio37_pins[] = { 50 };
+static const int en7581_gpio38_pins[] = { 51 };
+static const int en7581_gpio39_pins[] = { 52 };
+static const int en7581_gpio40_pins[] = { 53 };
+static const int en7581_gpio41_pins[] = { 54 };
+static const int en7581_gpio42_pins[] = { 55 };
+static const int en7581_gpio43_pins[] = { 56 };
+static const int en7581_gpio44_pins[] = { 57 };
+static const int en7581_gpio45_pins[] = { 58 };
+static const int en7581_gpio46_pins[] = { 59 };
+static const int en7581_pcie_reset0_pins[] = { 57 };
+static const int en7581_pcie_reset1_pins[] = { 58 };
+static const int en7581_pcie_reset2_pins[] = { 59 };
+
+static const struct pingroup en7581_pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", en7581_pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", en7581_sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", en7581_mdio),
+ PINCTRL_PIN_GROUP("uart2", en7581_uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("uart4", en7581_uart4),
+ PINCTRL_PIN_GROUP("uart5", en7581_uart5),
+ PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
+ PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", en7581_i2s),
+ PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
+ PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
+ PINCTRL_PIN_GROUP("spi", en7581_spi),
+ PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("emmc", en7581_emmc),
+ PINCTRL_PIN_GROUP("pnand", en7581_pnand),
+ PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
+ PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
+ PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
+ PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
+ PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
+ PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
+ PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
+ PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
+ PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
+ PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
+ PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
+ PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
+ PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
+ PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
+ PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
+ PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
+ PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
+ PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
+ PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
+ PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
+ PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
+ PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
+ PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
+ PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
+ PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
+ PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
+ PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
+ PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
+ PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
+ PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
+ PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
+ PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
+ PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
+ PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
+ PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
+ PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
+ PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
+ PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
+ PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
+ PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
+ PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
+ PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
+ PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
+ PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
+ PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
+ PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
+ PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
+ PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
+ PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+ "pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+ "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+ "uart4", "uart5"
+};
+static const char *const i2c_groups[] = { "i2c1" };
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pcm_spi_groups[] = {
+ "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
+ "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
+ "pcm_spi_cs4"
+};
+static const char *const i2s_groups[] = { "i2s" };
+static const char *const emmc_groups[] = { "emmc" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const gpio_groups[] = { "gpio44", "gpio45", "gpio46" };
+static const char *const pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1", "pcie_reset2"
+};
+static const char *const pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
+ "gpio46"
+};
+static const char *const phy1_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy2_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy3_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy4_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy1_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy2_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy3_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy4_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+ {
+ .name = "pon_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ PON_TOD_1PPS_MODE_MASK,
+ PON_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "gsw_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GSW_TOD_1PPS_MODE_MASK,
+ GSW_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MASK,
+ GPIO_MDC_IO_MASTER_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
+ REG_FORCE_GPIO_EN,
+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
+ },
+ .regmap_size = 2,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK,
+ GPIO_UART2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart2_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "hsuart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+ {
+ .name = "hsuart_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART4_MODE_MASK,
+ GPIO_UART4_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart5",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART5_MODE_MASK,
+ GPIO_UART5_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+ {
+ .name = "i2c1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_2ND_I2C_MODE_MASK,
+ GPIO_2ND_I2C_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS2_MODE_MASK,
+ GPIO_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS3_MODE_MASK,
+ GPIO_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS4_MODE_MASK,
+ GPIO_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_MODE_MASK,
+ GPIO_PCM_SPI_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_int",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK,
+ GPIO_PCM_INT_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK,
+ GPIO_PCM_RESET_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK,
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p128",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p156",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK,
+ GPIO_PCM_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK,
+ GPIO_PCM_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+ {
+ .name = "i2s",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_I2S_MODE_MASK,
+ GPIO_I2S_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group emmc_func_group[] = {
+ {
+ .name = "emmc",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_EMMC_MODE_MASK,
+ GPIO_EMMC_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+ {
+ .name = "pnand",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PARALLEL_NAND_MODE_MASK,
+ GPIO_PARALLEL_NAND_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET2_MASK),
+};
+
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET2_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET2_MASK),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("i2c", i2c),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+ PINCTRL_FUNC_DESC("i2s", i2s),
+ PINCTRL_FUNC_DESC("emmc", emmc),
+ PINCTRL_FUNC_DESC("pnand", pnand),
+ PINCTRL_FUNC_DESC("gpio", gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
+ .pins = en7581_pinctrl_pins,
+ .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
+ .grps = en7581_pinctrl_groups,
+ .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
+ .funcs = en7581_pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = en7581_pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = en7581_pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = en7581_pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = en7581_pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+ .confs = en7581_pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-an7581",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
new file mode 100644
index 000000000000..07a86aae3459
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -0,0 +1,1453 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define PON_TOD_1PPS_MODE_MASK BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+
+#define REG_GPIO_SPI_CS1_MODE 0x0218
+#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22)
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x021c
+#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
+#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
+#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
+#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
+#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
+#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
+#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
+#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
+#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
+#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
+#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
+#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
+#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+#define GPIO_PCIE_RESET1_MASK BIT(10)
+#define GPIO_PCIE_RESET0_MASK BIT(9)
+#define GPIO_UART5_MODE_MASK BIT(8)
+#define GPIO_UART4_MODE_MASK BIT(7)
+#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
+#define GPIO_HSUART_MODE_MASK BIT(5)
+#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
+#define GPIO_UART2_MODE_MASK BIT(3)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_EMMC_MODE_MASK BIT(1)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+#define REG_NPU_UART_EN 0x0224
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+
+#define REG_FORCE_GPIO_EN 0x0228
+#define FORCE_GPIO_EN(n) BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING 0x027c
+#define REG_LAN_LED1_MAPPING 0x0280
+
+#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
+#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2 0x001c
+#define AN7583_I2C1_SCL_E2_MASK BIT(16)
+#define AN7583_I2C1_SDA_E2_MASK BIT(15)
+#define SPI_MISO_E2_MASK BIT(14)
+#define SPI_MOSI_E2_MASK BIT(13)
+#define SPI_CLK_E2_MASK BIT(12)
+#define SPI_CS0_E2_MASK BIT(11)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define AN7583_MDIO_0_E2_MASK BIT(5)
+#define AN7583_MDC_0_E2_MASK BIT(4)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define AN7583_I2C1_SCL_E4_MASK BIT(16)
+#define AN7583_I2C1_SDA_E4_MASK BIT(15)
+#define SPI_MISO_E4_MASK BIT(14)
+#define SPI_MOSI_E4_MASK BIT(13)
+#define SPI_CLK_E4_MASK BIT(12)
+#define SPI_CS0_E4_MASK BIT(11)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define AN7583_MDIO_0_E4_MASK BIT(5)
+#define AN7583_MDC_0_E4_MASK BIT(4)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+#define REG_GPIO_H_E2 0x002c
+#define REG_GPIO_H_E4 0x0030
+
+#define REG_I2C_SDA_PU 0x0044
+#define AN7583_I2C1_SCL_PU_MASK BIT(16)
+#define AN7583_I2C1_SDA_PU_MASK BIT(15)
+#define SPI_MISO_PU_MASK BIT(14)
+#define SPI_MOSI_PU_MASK BIT(13)
+#define SPI_CLK_PU_MASK BIT(12)
+#define SPI_CS0_PU_MASK BIT(11)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define AN7583_MDIO_0_PU_MASK BIT(5)
+#define AN7583_MDC_0_PU_MASK BIT(4)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define AN7583_I2C1_SCL_PD_MASK BIT(16)
+#define AN7583_I2C1_SDA_PD_MASK BIT(15)
+#define SPI_MISO_PD_MASK BIT(14)
+#define SPI_MOSI_PD_MASK BIT(13)
+#define SPI_CLK_PD_MASK BIT(12)
+#define SPI_CS0_PD_MASK BIT(11)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define AN7583_MDIO_0_PD_MASK BIT(5)
+#define AN7583_MDC_0_PD_MASK BIT(4)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+#define REG_GPIO_H_PU 0x0054
+#define REG_GPIO_H_PD 0x0058
+
+#define REG_PCIE_RESET_OD 0x018c
+#define PCIE1_RESET_OD_MASK BIT(1)
+#define PCIE0_RESET_OD_MASK BIT(0)
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO51_FLASH_MODE_CFG BIT(31)
+#define GPIO50_FLASH_MODE_CFG BIT(30)
+#define GPIO49_FLASH_MODE_CFG BIT(29)
+#define GPIO48_FLASH_MODE_CFG BIT(28)
+#define GPIO47_FLASH_MODE_CFG BIT(27)
+#define GPIO46_FLASH_MODE_CFG BIT(26)
+#define GPIO45_FLASH_MODE_CFG BIT(25)
+#define GPIO44_FLASH_MODE_CFG BIT(24)
+#define GPIO43_FLASH_MODE_CFG BIT(23)
+#define GPIO42_FLASH_MODE_CFG BIT(22)
+#define GPIO41_FLASH_MODE_CFG BIT(21)
+#define GPIO40_FLASH_MODE_CFG BIT(20)
+#define GPIO39_FLASH_MODE_CFG BIT(19)
+#define GPIO38_FLASH_MODE_CFG BIT(18)
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+ PINCTRL_PIN(2, "gpio0"),
+ PINCTRL_PIN(3, "gpio1"),
+ PINCTRL_PIN(4, "gpio2"),
+ PINCTRL_PIN(5, "gpio3"),
+ PINCTRL_PIN(6, "gpio4"),
+ PINCTRL_PIN(7, "gpio5"),
+ PINCTRL_PIN(8, "gpio6"),
+ PINCTRL_PIN(9, "gpio7"),
+ PINCTRL_PIN(10, "gpio8"),
+ PINCTRL_PIN(11, "gpio9"),
+ PINCTRL_PIN(12, "gpio10"),
+ PINCTRL_PIN(13, "gpio11"),
+ PINCTRL_PIN(14, "gpio12"),
+ PINCTRL_PIN(15, "gpio13"),
+ PINCTRL_PIN(16, "gpio14"),
+ PINCTRL_PIN(17, "gpio15"),
+ PINCTRL_PIN(18, "gpio16"),
+ PINCTRL_PIN(19, "gpio17"),
+ PINCTRL_PIN(20, "gpio18"),
+ PINCTRL_PIN(21, "gpio19"),
+ PINCTRL_PIN(22, "gpio20"),
+ PINCTRL_PIN(23, "gpio21"),
+ PINCTRL_PIN(24, "gpio22"),
+ PINCTRL_PIN(25, "gpio23"),
+ PINCTRL_PIN(26, "gpio24"),
+ PINCTRL_PIN(27, "gpio25"),
+ PINCTRL_PIN(28, "gpio26"),
+ PINCTRL_PIN(29, "gpio27"),
+ PINCTRL_PIN(30, "gpio28"),
+ PINCTRL_PIN(31, "gpio29"),
+ PINCTRL_PIN(32, "gpio30"),
+ PINCTRL_PIN(33, "gpio31"),
+ PINCTRL_PIN(34, "gpio32"),
+ PINCTRL_PIN(35, "gpio33"),
+ PINCTRL_PIN(36, "gpio34"),
+ PINCTRL_PIN(37, "gpio35"),
+ PINCTRL_PIN(38, "gpio36"),
+ PINCTRL_PIN(39, "gpio37"),
+ PINCTRL_PIN(40, "gpio38"),
+ PINCTRL_PIN(41, "i2c0_scl"),
+ PINCTRL_PIN(42, "i2c0_sda"),
+ PINCTRL_PIN(43, "i2c1_scl"),
+ PINCTRL_PIN(44, "i2c1_sda"),
+ PINCTRL_PIN(45, "spi_clk"),
+ PINCTRL_PIN(46, "spi_cs"),
+ PINCTRL_PIN(47, "spi_mosi"),
+ PINCTRL_PIN(48, "spi_miso"),
+ PINCTRL_PIN(49, "uart_txd"),
+ PINCTRL_PIN(50, "uart_rxd"),
+ PINCTRL_PIN(51, "pcie_reset0"),
+ PINCTRL_PIN(52, "pcie_reset1"),
+ PINCTRL_PIN(53, "mdc_0"),
+ PINCTRL_PIN(54, "mdio_0"),
+};
+
+static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int an7583_pon_tod_1pps_pins[] = { 32 };
+static const int an7583_gsw_tod_1pps_pins[] = { 32 };
+static const int an7583_sipo_pins[] = { 34, 35 };
+static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
+static const int an7583_mdio_pins[] = { 43, 44 };
+static const int an7583_uart2_pins[] = { 34, 35 };
+static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
+static const int an7583_hsuart_pins[] = { 30, 31 };
+static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
+static const int an7583_npu_uart_pins[] = { 7, 8 };
+static const int an7583_uart4_pins[] = { 7, 8 };
+static const int an7583_uart5_pins[] = { 23, 24 };
+static const int an7583_i2c0_pins[] = { 41, 42 };
+static const int an7583_i2c1_pins[] = { 43, 44 };
+static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
+static const int an7583_spi_quad_pins[] = { 25, 26 };
+static const int an7583_spi_cs1_pins[] = { 27 };
+static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int an7583_pcm_spi_rst_pins[] = { 14 };
+static const int an7583_pcm_spi_cs1_pins[] = { 24 };
+static const int an7583_emmc_pins[] = {
+ 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
+};
+static const int an7583_pnand_pins[] = {
+ 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
+};
+static const int an7583_gpio0_pins[] = { 2 };
+static const int an7583_gpio1_pins[] = { 3 };
+static const int an7583_gpio2_pins[] = { 4 };
+static const int an7583_gpio3_pins[] = { 5 };
+static const int an7583_gpio4_pins[] = { 6 };
+static const int an7583_gpio5_pins[] = { 7 };
+static const int an7583_gpio6_pins[] = { 8 };
+static const int an7583_gpio7_pins[] = { 9 };
+static const int an7583_gpio8_pins[] = { 10 };
+static const int an7583_gpio9_pins[] = { 11 };
+static const int an7583_gpio10_pins[] = { 12 };
+static const int an7583_gpio11_pins[] = { 13 };
+static const int an7583_gpio12_pins[] = { 14 };
+static const int an7583_gpio13_pins[] = { 15 };
+static const int an7583_gpio14_pins[] = { 16 };
+static const int an7583_gpio15_pins[] = { 17 };
+static const int an7583_gpio16_pins[] = { 18 };
+static const int an7583_gpio17_pins[] = { 19 };
+static const int an7583_gpio18_pins[] = { 20 };
+static const int an7583_gpio19_pins[] = { 21 };
+static const int an7583_gpio20_pins[] = { 22 };
+static const int an7583_gpio21_pins[] = { 23 };
+static const int an7583_gpio22_pins[] = { 24 };
+static const int an7583_gpio23_pins[] = { 25 };
+static const int an7583_gpio24_pins[] = { 26 };
+static const int an7583_gpio25_pins[] = { 27 };
+static const int an7583_gpio26_pins[] = { 28 };
+static const int an7583_gpio27_pins[] = { 29 };
+static const int an7583_gpio28_pins[] = { 30 };
+static const int an7583_gpio29_pins[] = { 31 };
+static const int an7583_gpio30_pins[] = { 32 };
+static const int an7583_gpio31_pins[] = { 33 };
+static const int an7583_gpio32_pins[] = { 34 };
+static const int an7583_gpio33_pins[] = { 35 };
+static const int an7583_gpio34_pins[] = { 36 };
+static const int an7583_gpio35_pins[] = { 37 };
+static const int an7583_gpio36_pins[] = { 38 };
+static const int an7583_gpio37_pins[] = { 39 };
+static const int an7583_gpio38_pins[] = { 40 };
+static const int an7583_gpio39_pins[] = { 41 };
+static const int an7583_gpio40_pins[] = { 42 };
+static const int an7583_gpio41_pins[] = { 43 };
+static const int an7583_gpio42_pins[] = { 44 };
+static const int an7583_gpio43_pins[] = { 45 };
+static const int an7583_gpio44_pins[] = { 46 };
+static const int an7583_gpio45_pins[] = { 47 };
+static const int an7583_gpio46_pins[] = { 48 };
+static const int an7583_gpio47_pins[] = { 49 };
+static const int an7583_gpio48_pins[] = { 50 };
+static const int an7583_gpio49_pins[] = { 51 };
+static const int an7583_gpio50_pins[] = { 52 };
+static const int an7583_gpio51_pins[] = { 53 };
+static const int an7583_gpio52_pins[] = { 54 };
+static const int an7583_pcie_reset0_pins[] = { 51 };
+static const int an7583_pcie_reset1_pins[] = { 52 };
+
+static const struct pingroup an7583_pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", an7583_pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", an7583_sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", an7583_mdio),
+ PINCTRL_PIN_GROUP("uart2", an7583_uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
+ PINCTRL_PIN_GROUP("uart4", an7583_uart4),
+ PINCTRL_PIN_GROUP("uart5", an7583_uart5),
+ PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
+ PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
+ PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
+ PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
+ PINCTRL_PIN_GROUP("spi", an7583_spi),
+ PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("emmc", an7583_emmc),
+ PINCTRL_PIN_GROUP("pnand", an7583_pnand),
+ PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
+ PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
+ PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
+ PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
+ PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
+ PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
+ PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
+ PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
+ PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
+ PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
+ PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
+ PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
+ PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
+ PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
+ PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
+ PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
+ PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
+ PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
+ PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
+ PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
+ PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
+ PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
+ PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
+ PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
+ PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
+ PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
+ PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
+ PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
+ PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
+ PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
+ PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
+ PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
+ PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
+ PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
+ PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
+ PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
+ PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
+ PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
+ PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
+ PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
+ PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
+ PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
+ PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
+ PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
+ PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
+ PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
+ PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
+ PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
+ PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+ PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
+ PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
+ PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
+ PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
+ PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+ "pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const an7583_mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+ "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+ "uart4", "uart5"
+};
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const an7583_pcm_spi_groups[] = {
+ "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
+};
+static const char *const emmc_groups[] = { "emmc" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const an7583_gpio_groups[] = {
+ "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
+ "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
+ "gpio49", "gpio50", "gpio51", "gpio52"
+};
+static const char *const an7583_pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1"
+};
+static const char *const an7583_pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
+};
+static const char *const an7583_phy1_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy2_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy3_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy4_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy1_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy2_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy3_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy4_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+ {
+ .name = "pon_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ PON_TOD_1PPS_MODE_MASK,
+ PON_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "gsw_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GSW_TOD_1PPS_MODE_MASK,
+ GSW_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SGMII_MDIO_MODE_MASK,
+ GPIO_SGMII_MDIO_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MASK,
+ GPIO_MDC_IO_MASTER_MODE_MASK
+ },
+ .regmap_size = 2,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK,
+ GPIO_UART2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart2_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "hsuart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+ {
+ .name = "hsuart_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART4_MODE_MASK,
+ GPIO_UART4_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart5",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART5_MODE_MASK,
+ GPIO_UART5_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS2_MODE_MASK,
+ GPIO_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS3_MODE_MASK,
+ GPIO_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS4_MODE_MASK,
+ GPIO_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_MODE_MASK,
+ GPIO_PCM_SPI_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_int",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK,
+ GPIO_PCM_INT_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK,
+ GPIO_PCM_RESET_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK,
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK,
+ GPIO_PCM_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK,
+ GPIO_PCM_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group emmc_func_group[] = {
+ {
+ .name = "emmc",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_EMMC_MODE_MASK,
+ GPIO_EMMC_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+ {
+ .name = "pnand",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PARALLEL_NAND_MODE_MASK,
+ GPIO_PARALLEL_NAND_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
+ AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
+ AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
+ AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
+ AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
+ AN7583_SPI_CLK_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+ AN7583_SPI_CS_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+ AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+ AN7583_SPI_MISO_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+ AN7583_UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+ AN7583_UART_RXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
+ AN7583_MDC_0_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+};
+
+static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
+ AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
+ AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
+ AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
+ AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
+ AN7583_SPI_CLK_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+ AN7583_SPI_CS_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+ AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+ AN7583_SPI_MISO_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+ AN7583_UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+ AN7583_UART_RXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
+ AN7583_MDC_0_GPIO_MODE_MASK),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+ PINCTRL_FUNC_DESC("emmc", emmc),
+ PINCTRL_FUNC_DESC("pnand", pnand),
+ PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", an7583_pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
+ .pins = an7583_pinctrl_pins,
+ .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
+ .grps = an7583_pinctrl_groups,
+ .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
+ .funcs = an7583_pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = an7583_pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = an7583_pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = an7583_pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = an7583_pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+ .confs = an7583_pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-an7583",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
--
2.53.0
^ permalink raw reply related
* [PATCH v3 06/13] pinctrl: airoha: move common definitions to the separate header
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
Let's move the SoC independent definitions and declarations of structures
required for Airoha SoC-specific pinctrl drivers to a common header. Later
we'll have several SoC-specific drivers, so this step is necessary.
Also move GPIO related register addresses. It's not changed across en7523/
an7581/an7583 chips and will be used by common gpio code.
We will not move to the common header file other register addresses, register
bitfields definitions and macroses that use SoC specific information.
We will keep SoC specific definitions inside SoC specific files.
No functional changes.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/airoha-common.h | 201 ++++++++++++
drivers/pinctrl/airoha/pinctrl-airoha.c | 388 +++++++-----------------
2 files changed, 315 insertions(+), 274 deletions(-)
create mode 100644 drivers/pinctrl/airoha/airoha-common.h
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
new file mode 100644
index 000000000000..b0c48653a0e2
--- /dev/null
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#ifndef __AIROHA_COMMON_HEADER__
+#define __AIROHA_COMMON_HEADER__
+
+#include <linux/types.h>
+#include <linux/gpio/driver.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+
+/* GPIOs */
+#define REG_GPIO_CTRL 0x0000
+#define REG_GPIO_DATA 0x0004
+#define REG_GPIO_INT 0x0008
+#define REG_GPIO_INT_EDGE 0x000c
+#define REG_GPIO_INT_LEVEL 0x0010
+#define REG_GPIO_OE 0x0014
+#define REG_GPIO_CTRL1 0x0020
+#define REG_GPIO_CTRL2 0x0060
+#define REG_GPIO_CTRL3 0x0064
+#define REG_GPIO_DATA1 0x0070
+#define REG_GPIO_OE1 0x0078
+#define REG_GPIO_INT1 0x007c
+#define REG_GPIO_INT_EDGE1 0x0080
+#define REG_GPIO_INT_EDGE2 0x0084
+#define REG_GPIO_INT_EDGE3 0x0088
+#define REG_GPIO_INT_LEVEL1 0x008c
+#define REG_GPIO_INT_LEVEL2 0x0090
+#define REG_GPIO_INT_LEVEL3 0x0094
+
+#define AIROHA_NUM_PINS 64
+#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2)
+#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4)
+
+#define PINCTRL_PIN_GROUP(id, table) \
+ PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
+
+#define PINCTRL_FUNC_DESC(id, table) \
+ { \
+ .desc = PINCTRL_PINFUNCTION(id, table##_groups, \
+ ARRAY_SIZE(table##_groups)),\
+ .groups = table##_func_group, \
+ .group_size = ARRAY_SIZE(table##_func_group), \
+ }
+
+#define PINCTRL_CONF_DESC(p, offset, mask) \
+ { \
+ .pin = p, \
+ .reg = { offset, mask }, \
+ }
+
+
+#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
+ (pin), (val))
+#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
+ (pin), (val))
+#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
+ (pin), (val))
+#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
+ (pin), (val))
+#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
+ (pin), (val))
+#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
+ (pin), (val))
+#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
+ (pin), (val))
+#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
+ (pin), (val))
+#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
+ (pin), (val))
+#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
+ (pin), (val))
+
+struct airoha_pinctrl_reg {
+ u32 offset;
+ u32 mask;
+};
+
+enum airoha_pinctrl_mux_func {
+ AIROHA_FUNC_MUX,
+ AIROHA_FUNC_PWM_MUX,
+ AIROHA_FUNC_PWM_EXT_MUX,
+};
+
+struct airoha_pinctrl_func_group {
+ const char *name;
+ struct {
+ enum airoha_pinctrl_mux_func mux;
+ u32 offset;
+ u32 mask;
+ u32 val;
+ } regmap[2];
+ int regmap_size;
+};
+
+struct airoha_pinctrl_func {
+ const struct pinfunction desc;
+ const struct airoha_pinctrl_func_group *groups;
+ u8 group_size;
+};
+
+struct airoha_pinctrl_conf {
+ u32 pin;
+ struct airoha_pinctrl_reg reg;
+};
+
+struct airoha_pinctrl_gpiochip {
+ struct gpio_chip chip;
+
+ /* gpio */
+ const u32 *data;
+ const u32 *dir;
+ const u32 *out;
+ /* irq */
+ const u32 *status;
+ const u32 *level;
+ const u32 *edge;
+
+ u32 irq_type[AIROHA_NUM_PINS];
+};
+
+struct airoha_pinctrl_confs_info {
+ const struct airoha_pinctrl_conf *confs;
+ unsigned int num_confs;
+};
+
+enum airoha_pinctrl_confs_type {
+ AIROHA_PINCTRL_CONFS_PULLUP,
+ AIROHA_PINCTRL_CONFS_PULLDOWN,
+ AIROHA_PINCTRL_CONFS_DRIVE_E2,
+ AIROHA_PINCTRL_CONFS_DRIVE_E4,
+ AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
+
+ AIROHA_PINCTRL_CONFS_MAX,
+};
+
+struct airoha_pinctrl {
+ struct pinctrl_dev *ctrl;
+
+ struct pinctrl_desc desc;
+ const struct pingroup *grps;
+ const struct airoha_pinctrl_func *funcs;
+ const struct airoha_pinctrl_confs_info *confs_info;
+
+ struct regmap *chip_scu;
+ struct regmap *regmap;
+
+ struct airoha_pinctrl_gpiochip gpiochip;
+};
+
+struct airoha_pinctrl_match_data {
+ const struct pinctrl_pin_desc *pins;
+ const unsigned int num_pins;
+ const struct pingroup *grps;
+ const unsigned int num_grps;
+ const struct airoha_pinctrl_func *funcs;
+ const unsigned int num_funcs;
+ const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
+};
+
+#endif
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index e3a8ecbb20bd..a5bcf158d711 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -5,47 +5,7 @@
* Author: Markus Gothe <markus.gothe@genexis.eu>
*/
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/bitfield.h>
-#include <linux/bits.h>
-#include <linux/cleanup.h>
-#include <linux/gpio/driver.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "../core.h"
-#include "../pinconf.h"
-#include "../pinmux.h"
-
-#define PINCTRL_PIN_GROUP(id, table) \
- PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
-
-#define PINCTRL_FUNC_DESC(id, table) \
- { \
- .desc = PINCTRL_PINFUNCTION(id, table##_groups, \
- ARRAY_SIZE(table##_groups)),\
- .groups = table##_func_group, \
- .group_size = ARRAY_SIZE(table##_func_group), \
- }
-
-#define PINCTRL_CONF_DESC(p, offset, mask) \
- { \
- .pin = p, \
- .reg = { offset, mask }, \
- }
+#include "airoha-common.h"
/* MUX */
#define REG_GPIO_2ND_I2C_MODE 0x0214
@@ -230,6 +190,8 @@
#define REG_GPIO_INT_LEVEL 0x0010
#define REG_GPIO_OE 0x0014
#define REG_GPIO_CTRL1 0x0020
+#define REG_GPIO_CTRL2 0x0060
+#define REG_GPIO_CTRL3 0x0064
/* PWM MODE CONF */
#define REG_GPIO_FLASH_MODE_CFG 0x0034
@@ -250,9 +212,6 @@
#define GPIO1_FLASH_MODE_CFG BIT(1)
#define GPIO0_FLASH_MODE_CFG BIT(0)
-#define REG_GPIO_CTRL2 0x0060
-#define REG_GPIO_CTRL3 0x0064
-
/* PWM MODE CONF EXT */
#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
#define GPIO51_FLASH_MODE_CFG BIT(31)
@@ -298,9 +257,116 @@
#define REG_GPIO_INT_LEVEL2 0x0090
#define REG_GPIO_INT_LEVEL3 0x0094
-#define AIROHA_NUM_PINS 64
-#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2)
-#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4)
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ } \
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ } \
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
static const u32 gpio_data_regs[] = {
REG_GPIO_DATA,
@@ -338,93 +404,6 @@ static const u32 irq_edge_regs[] = {
REG_GPIO_INT_EDGE3
};
-struct airoha_pinctrl_reg {
- u32 offset;
- u32 mask;
-};
-
-enum airoha_pinctrl_mux_func {
- AIROHA_FUNC_MUX,
- AIROHA_FUNC_PWM_MUX,
- AIROHA_FUNC_PWM_EXT_MUX,
-};
-
-struct airoha_pinctrl_func_group {
- const char *name;
- struct {
- enum airoha_pinctrl_mux_func mux;
- u32 offset;
- u32 mask;
- u32 val;
- } regmap[2];
- int regmap_size;
-};
-
-struct airoha_pinctrl_func {
- const struct pinfunction desc;
- const struct airoha_pinctrl_func_group *groups;
- u8 group_size;
-};
-
-struct airoha_pinctrl_conf {
- u32 pin;
- struct airoha_pinctrl_reg reg;
-};
-
-struct airoha_pinctrl_gpiochip {
- struct gpio_chip chip;
-
- /* gpio */
- const u32 *data;
- const u32 *dir;
- const u32 *out;
- /* irq */
- const u32 *status;
- const u32 *level;
- const u32 *edge;
-
- u32 irq_type[AIROHA_NUM_PINS];
-};
-
-struct airoha_pinctrl_confs_info {
- const struct airoha_pinctrl_conf *confs;
- unsigned int num_confs;
-};
-
-enum airoha_pinctrl_confs_type {
- AIROHA_PINCTRL_CONFS_PULLUP,
- AIROHA_PINCTRL_CONFS_PULLDOWN,
- AIROHA_PINCTRL_CONFS_DRIVE_E2,
- AIROHA_PINCTRL_CONFS_DRIVE_E4,
- AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
-
- AIROHA_PINCTRL_CONFS_MAX,
-};
-
-struct airoha_pinctrl {
- struct pinctrl_dev *ctrl;
-
- struct pinctrl_desc desc;
- const struct pingroup *grps;
- const struct airoha_pinctrl_func *funcs;
- const struct airoha_pinctrl_confs_info *confs_info;
-
- struct regmap *chip_scu;
- struct regmap *regmap;
-
- struct airoha_pinctrl_gpiochip gpiochip;
-};
-
-struct airoha_pinctrl_match_data {
- const struct pinctrl_pin_desc *pins;
- const unsigned int num_pins;
- const struct pingroup *grps;
- const unsigned int num_grps;
- const struct airoha_pinctrl_func *funcs;
- const unsigned int num_funcs;
- const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
-};
-
static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
PINCTRL_PIN(0, "uart1_txd"),
PINCTRL_PIN(1, "uart1_rxd"),
@@ -1429,36 +1408,6 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
},
};
-#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- }
-
-#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- 0 \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (smux_val), \
- (smux_val) \
- }, \
- .regmap_size = 2, \
- }
-
static const struct airoha_pinctrl_func_group gpio_func_group[] = {
AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
GPIO_PCIE_RESET0_MASK),
@@ -1551,49 +1500,6 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
},
};
-/* PWM */
-#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_MUX, \
- REG_GPIO_FLASH_MODE_CFG, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- } \
-
-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- } \
-
-#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (smux_val), \
- (smux_val) \
- }, \
- .regmap_size = 2, \
- }
-
static const struct airoha_pinctrl_func_group pwm_func_group[] = {
AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
@@ -1678,6 +1584,7 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
AN7583_I2C0_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
@@ -1706,42 +1613,6 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
AN7583_MDC_0_GPIO_MODE_MASK),
};
-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED0_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED1_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
@@ -2809,37 +2680,6 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
return 0;
}
-#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
- (pin), (val))
-#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
- (pin), (val))
-#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
- (pin), (val))
-#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
- (pin), (val))
-#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
- (pin), (val))
-#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
- (pin), (val))
-#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
- (pin), (val))
-#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
- (pin), (val))
-#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
- (pin), (val))
-#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
- (pin), (val))
-
static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
{
struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
--
2.53.0
^ permalink raw reply related
* [PATCH v3 05/13] pinctrl: airoha: an7583: fix muxing of non-gpio default pins
From: Mikhail Kshevetskiy @ 2026-06-16 6:10 UTC (permalink / raw)
To: Linus Walleij, Lorenzo Bianconi, Christian Marangi,
Benjamin Larsson, AngeloGioacchino Del Regno, linux-kernel,
linux-gpio, linux-mediatek, Markus Gothe,
Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260616061029.2630777-1-mikhail.kshevetskiy@iopsys.eu>
Current an7583 pinmux implementation have following issues:
* pins 51 and 52 can't be set as pcie_reset, current pcie_reset code
will sets pins to gpio mode instead.
* there is no proper way to set pins 41--54 to gpio mode.
* pins 41--53 can't be actually set as pwm pins. These pins must be
muxed to gpio mode as well.
This patch fixes above issues.
Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-airoha.c | 100 ++++++++++++++++++++----
1 file changed, 86 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index 97b6d46ccb2b..e3a8ecbb20bd 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -84,6 +84,18 @@
#define GPIO_SPI_CS1_MODE_MASK BIT(0)
#define REG_GPIO_PON_MODE 0x021c
+#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
+#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
+#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
+#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
+#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
+#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
+#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
+#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
+#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
+#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
+#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
+#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
#define GPIO_PCIE_RESET2_MASK BIT(12)
@@ -773,6 +785,10 @@ static const int an7583_gpio45_pins[] = { 47 };
static const int an7583_gpio46_pins[] = { 48 };
static const int an7583_gpio47_pins[] = { 49 };
static const int an7583_gpio48_pins[] = { 50 };
+static const int an7583_gpio49_pins[] = { 51 };
+static const int an7583_gpio50_pins[] = { 52 };
+static const int an7583_gpio51_pins[] = { 53 };
+static const int an7583_gpio52_pins[] = { 54 };
static const int an7583_pcie_reset0_pins[] = { 51 };
static const int an7583_pcie_reset1_pins[] = { 52 };
@@ -853,6 +869,10 @@ static const struct pingroup an7583_pinctrl_groups[] = {
PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+ PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
+ PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
+ PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
+ PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
};
@@ -882,6 +902,11 @@ static const char *const pnand_groups[] = { "pnand" };
static const char *const gpio_groups[] = { "gpio44", "gpio45", "gpio46" };
static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
"pcie_reset2" };
+static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
+ "gpio42", "gpio43", "gpio44",
+ "gpio45", "gpio46", "gpio47",
+ "gpio48", "gpio49", "gpio50",
+ "gpio51", "gpio52" };
static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
static const char *const pwm_groups[] = { "gpio0", "gpio1",
"gpio2", "gpio3",
@@ -927,7 +952,8 @@ static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
"gpio42", "gpio43",
"gpio44", "gpio45",
"gpio46", "gpio47",
- "gpio48" };
+ "gpio48", "gpio49",
+ "gpio50", "gpio51" };
static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
"gpio35", "gpio42" };
static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
@@ -1473,6 +1499,36 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
},
};
+static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
+ AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
+ AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
+ AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
+ AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
+ AN7583_SPI_CLK_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+ AN7583_SPI_CS_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+ AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+ AN7583_SPI_MISO_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+ AN7583_UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+ AN7583_UART_RXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
+ AN7583_MDC_0_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+};
+
static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
{
.name = "pcie_reset0",
@@ -1480,7 +1536,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
GPIO_PCIE_RESET0_MASK,
- GPIO_PCIE_RESET0_MASK
+ 0
},
.regmap_size = 1,
}, {
@@ -1489,7 +1545,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
GPIO_PCIE_RESET1_MASK,
- GPIO_PCIE_RESET1_MASK
+ 0
},
.regmap_size = 1,
},
@@ -1622,17 +1678,32 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
+ AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
+ AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
+ AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
+ AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
+ AN7583_SPI_CLK_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+ AN7583_SPI_CS_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+ AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+ AN7583_SPI_MISO_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+ AN7583_UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+ AN7583_UART_RXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
+ AN7583_MDC_0_GPIO_MODE_MASK),
};
#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
@@ -1886,6 +1957,7 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
PINCTRL_FUNC_DESC("emmc", emmc),
PINCTRL_FUNC_DESC("pnand", pnand),
+ PINCTRL_FUNC_DESC("gpio", an7583_gpio),
PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
PINCTRL_FUNC_DESC("pwm", an7583_pwm),
PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
--
2.53.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox