* Re: [PATCH 15/78] ASoC: codecs: cs42l43: Use guard() for mutex locks
From: David Laight @ 2026-06-19 9:13 UTC (permalink / raw)
To: Bui Duc Phuc
Cc: Charles Keepax, Mark Brown, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, Cheng-Yi Chiang, Tzung-Bi Shih, Guenter Roeck,
Benson Leung, David Rhodes, Richard Fitzgerald, povik+lin,
Support Opensource, Nick Li, Herve Codina, Srinivas Kandagatla,
Matthias Brugger, AngeloGioacchino Del Regno, Shenghao Ding,
Kevin Lu, Baojun Xu, Sen Wang, Oder Chiou, Lars-Peter Clausen,
nuno.sa, Steven Eckhoff, patches, chrome-platform, asahi,
linux-arm-msm, linux-sound, linux-kernel, linux-arm-kernel,
linux-mediatek
In-Reply-To: <CAABR9nG+6gOj4KnWmTyykgGN93xy6jKQh+-_f8Xxn=Jkv28vBA@mail.gmail.com>
On Fri, 19 Jun 2026 15:20:37 +0700
Bui Duc Phuc <phucduc.bui@gmail.com> wrote:
> Hi Charles, David,
>
> Thanks for the review.
>
> > >
> > > I believe you have to use scoped_guard here, as there is a return
> > > from the function above, if memory serves it attempts to release
> > > the mutex on that path despite it being above the guard.
> >
> > Indeed.
> > I believe clang will complain.
> > That makes these mechanical conversions of existing code dangerous churn.
> >
> > While using guard() (etc) can make it easier to ensure the lock is released
> > when functions have multiple error exits, I'm not convinced it makes the
> > code any easier to read (other people may disagree).
> >
>
> I built the code with both GCC and Clang and didn't see any warnings.
>
> My understanding was that the early return exits the function before
> the guard is instantiated, so it should not affect the guard's cleanup
> handling.
>
> Could you explain what issue you are referring to? I may be missing
> something.
When a variable is defined (and initialised) part way down a block the
compiler moves the definition to the top of the block but doesn't initialise
it at all, the first assignment happens where the code contains the
definition.
However the destructor is always called at the end of the block.
So if you return from a function before the definition the destructor
is called with an uninitialised argument.
This has always been a problem with C++.
It usually happens when you define a variable inside a switch statement.
David
>
> Best regards,
> Phuc
^ permalink raw reply
* Re: [PATCH 11/78] ASoC: codecs: cros_ec_codec: Use guard() for mutex locks
From: Bui Duc Phuc @ 2026-06-19 8:26 UTC (permalink / raw)
To: Tzung-Bi Shih
Cc: Mark Brown, Liam Girdwood, Jaroslav Kysela, Takashi Iwai,
Cheng-Yi Chiang, Guenter Roeck, Benson Leung, David Rhodes,
Richard Fitzgerald, povik+lin, Charles Keepax, Support Opensource,
Nick Li, Herve Codina, Srinivas Kandagatla, Matthias Brugger,
AngeloGioacchino Del Regno, Shenghao Ding, Kevin Lu, Baojun Xu,
Sen Wang, Oder Chiou, Lars-Peter Clausen, nuno.sa, Steven Eckhoff,
patches, chrome-platform, asahi, linux-arm-msm, linux-sound,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <ajNud7QkwF369lBY@google.com>
Hi Tzung-Bi,
> Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Thanks for reviewing the patch.
Best regards,
Phuc
^ permalink raw reply
* Re: [PATCH 15/78] ASoC: codecs: cs42l43: Use guard() for mutex locks
From: Bui Duc Phuc @ 2026-06-19 8:20 UTC (permalink / raw)
To: David Laight
Cc: Charles Keepax, Mark Brown, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, Cheng-Yi Chiang, Tzung-Bi Shih, Guenter Roeck,
Benson Leung, David Rhodes, Richard Fitzgerald, povik+lin,
Support Opensource, Nick Li, Herve Codina, Srinivas Kandagatla,
Matthias Brugger, AngeloGioacchino Del Regno, Shenghao Ding,
Kevin Lu, Baojun Xu, Sen Wang, Oder Chiou, Lars-Peter Clausen,
nuno.sa, Steven Eckhoff, patches, chrome-platform, asahi,
linux-arm-msm, linux-sound, linux-kernel, linux-arm-kernel,
linux-mediatek
In-Reply-To: <20260617140209.3f89706c@pumpkin>
Hi Charles, David,
Thanks for the review.
> >
> > I believe you have to use scoped_guard here, as there is a return
> > from the function above, if memory serves it attempts to release
> > the mutex on that path despite it being above the guard.
>
> Indeed.
> I believe clang will complain.
> That makes these mechanical conversions of existing code dangerous churn.
>
> While using guard() (etc) can make it easier to ensure the lock is released
> when functions have multiple error exits, I'm not convinced it makes the
> code any easier to read (other people may disagree).
>
I built the code with both GCC and Clang and didn't see any warnings.
My understanding was that the early return exits the function before
the guard is instantiated, so it should not affect the guard's cleanup
handling.
Could you explain what issue you are referring to? I may be missing
something.
Best regards,
Phuc
^ permalink raw reply
* [PATCH net v2] net: airoha: Fix TX scheduler queue mask loop upper bound
From: Wayen Yan @ 2026-06-19 7:52 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
In airoha_qdma_set_chan_tx_sched(), the loop clearing queue mask was
using AIROHA_NUM_TX_RING (32) instead of AIROHA_NUM_QOS_QUEUES (8).
Each channel has 8 queues, and TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)
computes BIT(i + (channel * 8)). With i ranging 0..31, this causes:
- channel 0: clears bit 0..31 (all 4 channels) instead of 0..7
- channel 1: clears bit 8..31 (channels 1-3) instead of 8..15
- channel 2: clears bit 16..31 (channels 2-3) instead of 16..23
- channel 3: clears bit 24..31 (channel 3 only) - correct by accident
While BIT(32+) on arm64 produces 64-bit values truncated to 0 in u32
mask parameter, the loop still incorrectly clears queues within the
same channel beyond queue 7.
Even though this is functionally harmless (the register resets to 0
and is only ever cleared, never set — so clearing extra bits is a
no-op), the loop bound is semantically wrong and should be fixed for
correctness and clarity.
Fix by using AIROHA_NUM_QOS_QUEUES (8) as the loop upper bound.
Fixes: ef1ca9271313 ("net: airoha: Add sched HTB offload support")
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Wayen Yan <win847@gmail.com>
---
Changes in v2:
- Add Lorenzo's Acked-by tag.
- Clarify in commit message that this is semantically wrong but
functionally harmless (register resets to 0, only cleared), as
Lorenzo pointed out in review.
- Rebase on current net tree.
Link: https://lore.kernel.org/netdev/ajJIWMs4dVbfkHZ5@lore-desk/
Link: https://lore.kernel.org/netdev/CAL_ptrs6J3Ryw_4mVTq5VgzkB4RreF5S0huHyLvd9YwWr1m6jAA@mail.gmail.com/
drivers/net/ethernet/airoha/airoha_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index d0c0c0ec8a..ca77747b44 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -2212,7 +2212,7 @@ static int airoha_qdma_set_chan_tx_sched(struct net_device *dev,
struct airoha_gdm_port *port = netdev_priv(dev);
int i;
- for (i = 0; i < AIROHA_NUM_TX_RING; i++)
+ for (i = 0; i < AIROHA_NUM_QOS_QUEUES; i++)
airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel),
TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i));
--
2.51.0
^ permalink raw reply related
* [PATCH net v4] net: airoha: Fix skb->priority underflow in airoha_dev_select_queue()
From: Wayen Yan @ 2026-06-19 7:50 UTC (permalink / raw)
To: netdev
Cc: lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
In airoha_dev_select_queue(), the expression:
queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES;
implicitly converts to unsigned arithmetic: when skb->priority is 0
(the default for unclassified traffic), (0u - 1u) wraps to UINT_MAX,
and UINT_MAX % 8 = 7, routing default best-effort packets to the
highest-priority QoS queue. This causes QoS inversion where the
majority of traffic on a PON gateway starves actual high-priority
flows (VoIP, gaming, etc.).
The "- 1" offset was a leftover from the ETS offload implementation
that has since been removed. The correct mapping is a direct modulo:
queue = skb->priority % AIROHA_NUM_QOS_QUEUES;
This maps priority 0 → queue 0 (lowest), priority 7 → queue 7
(highest), with higher priorities wrapping around. This is the
standard Linux sk_prio → HW queue mapping used by other drivers.
Fixes: 2b288b81560b ("net: airoha: Introduce ndo_select_queue callback")
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: Joe Damato <joe@dama.to>
Signed-off-by: Wayen Yan <win847@gmail.com>
---
Changes in v4:
- Remove the "- 1" offset entirely as suggested by Lorenzo and Jakub.
The offset was an ETS offload leftover; the correct mapping is a
direct modulo of skb->priority to AIROHA_NUM_QOS_QUEUES, matching
the standard Linux sk_prio → HW queue convention. (v3 used a
ternary guard which addressed the underflow but kept the unneeded
offset.)
Link: https://lore.kernel.org/netdev/20260617164448.31e189bc@kernel.org/
Link: https://lore.kernel.org/netdev/ajPCgH7E_ke6Fdur@lore-desk/
drivers/net/ethernet/airoha/airoha_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index d0c0c0ec8a..9ec3f22754 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1928,7 +1928,7 @@ static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb,
*/
channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id;
channel = channel % AIROHA_NUM_QOS_CHANNELS;
- queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */
+ queue = skb->priority % AIROHA_NUM_QOS_QUEUES;
queue = channel * AIROHA_NUM_QOS_QUEUES + queue;
return queue < dev->num_tx_queues ? queue : 0;
--
2.51.0
^ permalink raw reply related
* Re: [PATCH wireless-next] wifi: mt76: fix of_get_mac_address error handling
From: Rosen Penev @ 2026-06-19 1:50 UTC (permalink / raw)
To: Klara Modin, Rosen Penev
Cc: linux-wireless, Felix Fietkau, Lorenzo Bianconi, Ryder Lee,
Shayne Chen, Sean Wang, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <ajSDtsJCmYnMNJSD@parmesan.int.kasm.eu>
On Thu Jun 18, 2026 at 4:51 PM PDT, Klara Modin wrote:
> On 2026-06-18 16:01:45 -0700, Rosen Penev wrote:
>> On Thu, Jun 18, 2026 at 2:47 PM Klara Modin <klarasmodin@gmail.com> wrote:
>> >
>> > Hi,
>> >
>> > On 2026-04-26 22:17:46 -0700, Rosen Penev wrote:
>> > > Check return value instead of is_valid_ether_addr. The latter is handled
>> > > by the former.
>> > >
>> > > Signed-off-by: Rosen Penev <rosenp@gmail.com>
>> > > ---
>> > > drivers/net/wireless/mediatek/mt76/eeprom.c | 2 +-
>> > > 1 file changed, 1 insertion(+), 1 deletion(-)
>> > >
>> > > diff --git a/drivers/net/wireless/mediatek/mt76/eeprom.c b/drivers/net/wireless/mediatek/mt76/eeprom.c
>> > > index 93d91264687f..0f6ccf6ed53d 100644
>> > > --- a/drivers/net/wireless/mediatek/mt76/eeprom.c
>> > > +++ b/drivers/net/wireless/mediatek/mt76/eeprom.c
>> > > @@ -93,7 +93,7 @@ mt76_eeprom_override(struct mt76_phy *phy)
>> > > if (err == -EPROBE_DEFER)
>> > > return err;
>> > >
>> > > - if (!is_valid_ether_addr(phy->macaddr)) {
>> > > + if (err) {
>> > > eth_random_addr(phy->macaddr);
>> > > dev_info(dev->dev,
>> > > "Invalid MAC address, using random address %pM\n",
>> > > --
>> > > 2.54.0
>> > >
>> >
>> > Recently I have started to see randomized MAC-addresses on my x86 laptop
>> > with a MT7922 and the above message printed in the kernel log. I have
>> > CONFIG_OF turned on, but since this is an ACPI system the device is not
>> > described by any device tree and the earlier of_get_mac_address() likely
>> > fails with -ENODEV. Looking at the !CONFIG_OF stub for
>> > of_get_mac_address it always returns -ENODEV, meaning this will always
>> > randomize the mac in that case too.
>
>> IIRC, the normal device_get_mac_address supports nvmem now. Does that
>> fix your use case?
>
> I tried this:
>
> diff --git a/drivers/net/wireless/mediatek/mt76/eeprom.c b/drivers/net/wireless/mediatek/mt76/eeprom.c
> index b99d7452800f..243a8f2c7bda 100644
> --- a/drivers/net/wireless/mediatek/mt76/eeprom.c
> +++ b/drivers/net/wireless/mediatek/mt76/eeprom.c
> @@ -174,10 +174,9 @@ int
> mt76_eeprom_override(struct mt76_phy *phy)
> {
> struct mt76_dev *dev = phy->dev;
> - struct device_node *np = dev->dev->of_node;
> int err;
>
> - err = of_get_mac_address(np, phy->macaddr);
> + err = device_get_mac_address(dev->dev, phy->macaddr);
> if (err == -EPROBE_DEFER)
> return err;
>
>
> but I still get a random MAC.
Then the original patch should be reverted. Unfortunate that it doesn't
workq
>
>> >
>> > Reverting this patch fixes the issue and the correct MAC address is
>> > used. I'm not sure if there is any case where of_get_mac_addres() could
>> > fail in a way that results in a valid MAC address but it seems unlikely
>> > to me.
>> >
>> > Regards,
>> > Klara Modin
^ permalink raw reply
* Re: [PATCH v2] [net] net: airoha: fix foe_check_time allocation size
From: patchwork-bot+netdevbpf @ 2026-06-19 1:10 UTC (permalink / raw)
To: Wayen Yan
Cc: netdev, lorenzo, horms, pabeni, kuba, edumazet, andrew+netdev,
angelogioacchino.delregno, matthias.bgg, linux-arm-kernel,
linux-mediatek
In-Reply-To: <178161119471.2163752.14373384830691569758@gmail.com>
Hello:
This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 16 Jun 2026 19:52:36 +0800 you wrote:
> foe_check_time is declared as u16 pointer but was allocated with
> only ppe_num_entries bytes instead of ppe_num_entries * sizeof(u16).
>
> When airoha_ppe_foe_verify_entry() is called with hash >= ppe_num_entries/2,
> it writes beyond the allocated buffer, causing heap buffer overflow and
> potential kernel crash.
>
> [...]
Here is the summary with links:
- [v2,net] net: airoha: fix foe_check_time allocation size
https://git.kernel.org/netdev/net/c/5c121ee63568
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH wireless-next] wifi: mt76: fix of_get_mac_address error handling
From: Klara Modin @ 2026-06-18 23:51 UTC (permalink / raw)
To: Rosen Penev
Cc: linux-wireless, Felix Fietkau, Lorenzo Bianconi, Ryder Lee,
Shayne Chen, Sean Wang, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <CAKxU2N-gfH8Tq29-j2MArogLZuO7JEqtN5LNPVygJzrAERa3cg@mail.gmail.com>
On 2026-06-18 16:01:45 -0700, Rosen Penev wrote:
> On Thu, Jun 18, 2026 at 2:47 PM Klara Modin <klarasmodin@gmail.com> wrote:
> >
> > Hi,
> >
> > On 2026-04-26 22:17:46 -0700, Rosen Penev wrote:
> > > Check return value instead of is_valid_ether_addr. The latter is handled
> > > by the former.
> > >
> > > Signed-off-by: Rosen Penev <rosenp@gmail.com>
> > > ---
> > > drivers/net/wireless/mediatek/mt76/eeprom.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/net/wireless/mediatek/mt76/eeprom.c b/drivers/net/wireless/mediatek/mt76/eeprom.c
> > > index 93d91264687f..0f6ccf6ed53d 100644
> > > --- a/drivers/net/wireless/mediatek/mt76/eeprom.c
> > > +++ b/drivers/net/wireless/mediatek/mt76/eeprom.c
> > > @@ -93,7 +93,7 @@ mt76_eeprom_override(struct mt76_phy *phy)
> > > if (err == -EPROBE_DEFER)
> > > return err;
> > >
> > > - if (!is_valid_ether_addr(phy->macaddr)) {
> > > + if (err) {
> > > eth_random_addr(phy->macaddr);
> > > dev_info(dev->dev,
> > > "Invalid MAC address, using random address %pM\n",
> > > --
> > > 2.54.0
> > >
> >
> > Recently I have started to see randomized MAC-addresses on my x86 laptop
> > with a MT7922 and the above message printed in the kernel log. I have
> > CONFIG_OF turned on, but since this is an ACPI system the device is not
> > described by any device tree and the earlier of_get_mac_address() likely
> > fails with -ENODEV. Looking at the !CONFIG_OF stub for
> > of_get_mac_address it always returns -ENODEV, meaning this will always
> > randomize the mac in that case too.
> IIRC, the normal device_get_mac_address supports nvmem now. Does that
> fix your use case?
I tried this:
diff --git a/drivers/net/wireless/mediatek/mt76/eeprom.c b/drivers/net/wireless/mediatek/mt76/eeprom.c
index b99d7452800f..243a8f2c7bda 100644
--- a/drivers/net/wireless/mediatek/mt76/eeprom.c
+++ b/drivers/net/wireless/mediatek/mt76/eeprom.c
@@ -174,10 +174,9 @@ int
mt76_eeprom_override(struct mt76_phy *phy)
{
struct mt76_dev *dev = phy->dev;
- struct device_node *np = dev->dev->of_node;
int err;
- err = of_get_mac_address(np, phy->macaddr);
+ err = device_get_mac_address(dev->dev, phy->macaddr);
if (err == -EPROBE_DEFER)
return err;
but I still get a random MAC.
> >
> > Reverting this patch fixes the issue and the correct MAC address is
> > used. I'm not sure if there is any case where of_get_mac_addres() could
> > fail in a way that results in a valid MAC address but it seems unlikely
> > to me.
> >
> > Regards,
> > Klara Modin
^ permalink raw reply related
* Re: [PATCH wireless-next] wifi: mt76: fix of_get_mac_address error handling
From: Rosen Penev @ 2026-06-18 23:01 UTC (permalink / raw)
To: Klara Modin
Cc: linux-wireless, Felix Fietkau, Lorenzo Bianconi, Ryder Lee,
Shayne Chen, Sean Wang, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <ajRmlyx_AEGybykL@soda.int.kasm.eu>
On Thu, Jun 18, 2026 at 2:47 PM Klara Modin <klarasmodin@gmail.com> wrote:
>
> Hi,
>
> On 2026-04-26 22:17:46 -0700, Rosen Penev wrote:
> > Check return value instead of is_valid_ether_addr. The latter is handled
> > by the former.
> >
> > Signed-off-by: Rosen Penev <rosenp@gmail.com>
> > ---
> > drivers/net/wireless/mediatek/mt76/eeprom.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/wireless/mediatek/mt76/eeprom.c b/drivers/net/wireless/mediatek/mt76/eeprom.c
> > index 93d91264687f..0f6ccf6ed53d 100644
> > --- a/drivers/net/wireless/mediatek/mt76/eeprom.c
> > +++ b/drivers/net/wireless/mediatek/mt76/eeprom.c
> > @@ -93,7 +93,7 @@ mt76_eeprom_override(struct mt76_phy *phy)
> > if (err == -EPROBE_DEFER)
> > return err;
> >
> > - if (!is_valid_ether_addr(phy->macaddr)) {
> > + if (err) {
> > eth_random_addr(phy->macaddr);
> > dev_info(dev->dev,
> > "Invalid MAC address, using random address %pM\n",
> > --
> > 2.54.0
> >
>
> Recently I have started to see randomized MAC-addresses on my x86 laptop
> with a MT7922 and the above message printed in the kernel log. I have
> CONFIG_OF turned on, but since this is an ACPI system the device is not
> described by any device tree and the earlier of_get_mac_address() likely
> fails with -ENODEV. Looking at the !CONFIG_OF stub for
> of_get_mac_address it always returns -ENODEV, meaning this will always
> randomize the mac in that case too.
IIRC, the normal device_get_mac_address supports nvmem now. Does that
fix your use case?
>
> Reverting this patch fixes the issue and the correct MAC address is
> used. I'm not sure if there is any case where of_get_mac_addres() could
> fail in a way that results in a valid MAC address but it seems unlikely
> to me.
>
> Regards,
> Klara Modin
^ permalink raw reply
* Re: [PATCH wireless-next] wifi: mt76: fix of_get_mac_address error handling
From: Klara Modin @ 2026-06-18 21:47 UTC (permalink / raw)
To: Rosen Penev
Cc: linux-wireless, Felix Fietkau, Lorenzo Bianconi, Ryder Lee,
Shayne Chen, Sean Wang, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
In-Reply-To: <20260427051746.954704-1-rosenp@gmail.com>
Hi,
On 2026-04-26 22:17:46 -0700, Rosen Penev wrote:
> Check return value instead of is_valid_ether_addr. The latter is handled
> by the former.
>
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
> drivers/net/wireless/mediatek/mt76/eeprom.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/eeprom.c b/drivers/net/wireless/mediatek/mt76/eeprom.c
> index 93d91264687f..0f6ccf6ed53d 100644
> --- a/drivers/net/wireless/mediatek/mt76/eeprom.c
> +++ b/drivers/net/wireless/mediatek/mt76/eeprom.c
> @@ -93,7 +93,7 @@ mt76_eeprom_override(struct mt76_phy *phy)
> if (err == -EPROBE_DEFER)
> return err;
>
> - if (!is_valid_ether_addr(phy->macaddr)) {
> + if (err) {
> eth_random_addr(phy->macaddr);
> dev_info(dev->dev,
> "Invalid MAC address, using random address %pM\n",
> --
> 2.54.0
>
Recently I have started to see randomized MAC-addresses on my x86 laptop
with a MT7922 and the above message printed in the kernel log. I have
CONFIG_OF turned on, but since this is an ACPI system the device is not
described by any device tree and the earlier of_get_mac_address() likely
fails with -ENODEV. Looking at the !CONFIG_OF stub for
of_get_mac_address it always returns -ENODEV, meaning this will always
randomize the mac in that case too.
Reverting this patch fixes the issue and the correct MAC address is
used. I'm not sure if there is any case where of_get_mac_addres() could
fail in a way that results in a valid MAC address but it seems unlikely
to me.
Regards,
Klara Modin
^ permalink raw reply
* Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable
From: Adam Thiede @ 2026-06-18 21:06 UTC (permalink / raw)
To: Gary Bisson, Chun-Kuang Hu, Philipp Zabel, David Airlie,
Simona Vetter, Matthias Brugger, AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, linux-kernel, linux-arm-kernel
In-Reply-To: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com>
On 1/20/26 05:36, Gary Bisson wrote:
> Some bridges, such as the TI SN65DSI83, require the HS clock to be
> running in order to lock its PLL during its own pre-enable function.
>
> Without this change, the bridge gives the following error:
> sn65dsi83 14-002c: failed to lock PLL, ret=-110
> sn65dsi83 14-002c: Unexpected link status 0x01
> sn65dsi83 14-002c: reset the pipe
>
> Move the necessary functions from enable to pre-enable.
>
> Signed-off-by: Gary Bisson <bisson.gary@gmail.com>
> ---
> Tested on Tungsten510 module with sn65dsi83 + tm070jdhg30 panel.
>
> Left mtk_dsi_set_mode() as part of the enable function to mimic what is
> done in the Samsung DSIM driver which is known to be working the TI
> bridge.
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 35 +++++++++++++++++------------------
> 1 file changed, 17 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 0e2bcd5f67b7..b560245d1be9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -672,6 +672,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
> }
> }
>
> +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
> +{
> + if (!dsi->lanes_ready) {
> + dsi->lanes_ready = true;
> + mtk_dsi_rxtx_control(dsi);
> + usleep_range(30, 100);
> + mtk_dsi_reset_dphy(dsi);
> + mtk_dsi_clk_ulp_mode_leave(dsi);
> + mtk_dsi_lane0_ulp_mode_leave(dsi);
> + mtk_dsi_clk_hs_mode(dsi, 0);
> + usleep_range(1000, 3000);
> + /* The reaction time after pulling up the mipi signal for dsi_rx */
> + }
> +}
> +
> static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> {
> struct device *dev = dsi->host.dev;
> @@ -724,6 +739,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> mtk_dsi_set_vm_cmd(dsi);
> mtk_dsi_config_vdo_timing(dsi);
> mtk_dsi_set_interrupt_enable(dsi);
> + mtk_dsi_lane_ready(dsi);
> + mtk_dsi_clk_hs_mode(dsi, 1);
>
> return 0;
> err_disable_engine_clk:
> @@ -769,30 +786,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
> dsi->lanes_ready = false;
> }
>
> -static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
> -{
> - if (!dsi->lanes_ready) {
> - dsi->lanes_ready = true;
> - mtk_dsi_rxtx_control(dsi);
> - usleep_range(30, 100);
> - mtk_dsi_reset_dphy(dsi);
> - mtk_dsi_clk_ulp_mode_leave(dsi);
> - mtk_dsi_lane0_ulp_mode_leave(dsi);
> - mtk_dsi_clk_hs_mode(dsi, 0);
> - usleep_range(1000, 3000);
> - /* The reaction time after pulling up the mipi signal for dsi_rx */
> - }
> -}
> -
> static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
> {
> if (dsi->enabled)
> return;
>
> - mtk_dsi_lane_ready(dsi);
> mtk_dsi_set_mode(dsi);
> - mtk_dsi_clk_hs_mode(dsi, 1);
> -
> mtk_dsi_start(dsi);
>
> dsi->enabled = true;
>
> ---
> base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
> change-id: 20260120-mtkdsi-29e4c84e7b38
>
> Best regards,
Hello,
This commit was part of 7.1 and caused a problem for me.
I'm running postmarketOS (basically Alpine Linux) on a Lenovo C330
chromebook with a Mediatek MT8173 processor.
The problem: when the display on my laptop powers off (via suspend or
idle, like xset dpms off) the picture does not come back when the
display powers back on (from resume). The display backlight comes on and
brightness is adjustable but there is no picture. The only fix is to reboot.
Reverting this commit and applying it as a patch on top of 7.1 addresses
the issue for me.
You can view the config I'm using here:
https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/8819
Is there any sort of testing or other debugging info I can provide to
help address this issue?
Thanks,
- Adam Thiede
^ permalink raw reply
* Re: [PATCH net] net: airoha: fix BQL underflow and UAF in shared QDMA TX ring
From: Lorenzo Bianconi @ 2026-06-18 15:42 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni
Cc: Wayen Yan, linux-arm-kernel, linux-mediatek, netdev
In-Reply-To: <20260618-airoha-bql-fixes-v1-1-ffd2c2089518@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 7943 bytes --]
> When multiple netdevs share a QDMA TX ring and one device is stopped,
> netdev_tx_reset_subqueue() zeroes that device's BQL counters while its
> pending skbs remain in the shared HW TX ring. When NAPI later completes
> those skbs via netdev_tx_completed_queue(), the already-zeroed
> dql->num_queued counter underflows.
> Moreover, in the airoha_remove() path, netdevs are unregistered
> sequentially while skbs from previously unregistered netdevs may still
> reference freed net_device memory via skb->dev, causing a use-after-free
> during BQL accounting.
> Fix both issues:
> - Remove netdev_tx_reset_subqueue() from airoha_dev_stop() so pending
> skbs are completed naturally by NAPI with proper BQL accounting.
> - Add netdev_tx_completed_queue() in airoha_qdma_cleanup_tx_queue()
> to properly account for skbs freed during queue teardown.
> - Introduce airoha_qdma_tx_disable() to stop TX on all registered
> netdevs for a given QDMA instance under RTNL lock.
> - Move DMA engine start/stop into probe/remove and
> airoha_qdma_cleanup(), ensuring TX queues are cleaned up while all
> netdevs are still registered and skb->dev is valid.
>
> Fixes: 6df0488dc9dd ("net: airoha: fix BQL accounting in airoha_qdma_cleanup_tx_queue()")
This Fixes tag is wrong, the proper one is the one below:
Fixes: a9c2ca61fec7 ("net: airoha: Support multiple net_devices for a single FE GDM port")
Regards,
Lorenzo
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> drivers/net/ethernet/airoha/airoha_eth.c | 95 ++++++++++++++++++++++++--------
> 1 file changed, 72 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 64dde6464f3f..4d6a061cd779 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -1004,6 +1004,7 @@ static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget)
>
> e = &q->entry[index];
> skb = e->skb;
> + e->skb = NULL;
>
> dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
> DMA_TO_DEVICE);
> @@ -1147,6 +1148,42 @@ static int airoha_qdma_init_tx(struct airoha_qdma *qdma)
> return 0;
> }
>
> +static void airoha_qdma_tx_disable(struct airoha_qdma *qdma)
> +{
> + struct airoha_eth *eth = qdma->eth;
> + int i;
> +
> + /* Protect netdev->reg_state and netif_tx_disable() calls. */
> + rtnl_lock();
> +
> + for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> + struct airoha_gdm_port *port = eth->ports[i];
> + int j;
> +
> + if (!port)
> + continue;
> +
> + for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
> + struct airoha_gdm_dev *dev = port->devs[j];
> + struct net_device *netdev;
> +
> + if (!dev)
> + continue;
> +
> + if (dev->qdma != qdma)
> + continue;
> +
> + netdev = netdev_from_priv(dev);
> + if (netdev->reg_state != NETREG_REGISTERED)
> + continue;
> +
> + netif_tx_disable(netdev);
> + }
> + }
> +
> + rtnl_unlock();
> +}
> +
> static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
> {
> struct airoha_qdma *qdma = q->qdma;
> @@ -1158,13 +1195,20 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
> for (i = 0; i < q->ndesc; i++) {
> struct airoha_queue_entry *e = &q->entry[i];
> struct airoha_qdma_desc *desc = &q->desc[i];
> + struct sk_buff *skb = e->skb;
>
> if (!e->dma_addr)
> continue;
>
> dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
> DMA_TO_DEVICE);
> - dev_kfree_skb_any(e->skb);
> + if (skb) {
> + struct netdev_queue *txq;
> +
> + txq = skb_get_tx_queue(skb->dev, skb);
> + netdev_tx_completed_queue(txq, 1, skb->len);
> + dev_kfree_skb_any(skb);
> + }
> e->dma_addr = 0;
> e->skb = NULL;
> list_add_tail(&e->list, &q->tx_list);
> @@ -1527,6 +1571,23 @@ static void airoha_qdma_cleanup(struct airoha_qdma *qdma)
> {
> int i;
>
> + if (test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) {
> + u32 status;
> +
> + airoha_qdma_tx_disable(qdma);
> +
> + airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
> + GLOBAL_CFG_TX_DMA_EN_MASK |
> + GLOBAL_CFG_RX_DMA_EN_MASK);
> + if (read_poll_timeout(airoha_qdma_rr, status,
> + !(status & (GLOBAL_CFG_TX_DMA_BUSY_MASK |
> + GLOBAL_CFG_RX_DMA_BUSY_MASK)),
> + USEC_PER_MSEC, 50 * USEC_PER_MSEC, true,
> + qdma, REG_QDMA_GLOBAL_CFG))
> + dev_warn(qdma->eth->dev,
> + "QDMA DMA engine busy timeout\n");
> + }
> +
> for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
> if (!qdma->q_rx[i].ndesc)
> continue;
> @@ -1837,9 +1898,6 @@ static int airoha_dev_open(struct net_device *netdev)
> }
> port->users++;
>
> - airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
> - GLOBAL_CFG_TX_DMA_EN_MASK |
> - GLOBAL_CFG_RX_DMA_EN_MASK);
> qdma->users++;
>
> if (!airoha_is_lan_gdm_dev(dev) &&
> @@ -1880,12 +1938,9 @@ static int airoha_dev_stop(struct net_device *netdev)
> struct airoha_gdm_dev *dev = netdev_priv(netdev);
> struct airoha_gdm_port *port = dev->port;
> struct airoha_qdma *qdma = dev->qdma;
> - int i;
>
> netif_tx_disable(netdev);
> airoha_set_vip_for_gdm_port(dev, false);
> - for (i = 0; i < netdev->num_tx_queues; i++)
> - netdev_tx_reset_subqueue(netdev, i);
>
> if (--port->users)
> airoha_set_port_mtu(dev->eth, port);
> @@ -1893,19 +1948,7 @@ static int airoha_dev_stop(struct net_device *netdev)
> airoha_set_gdm_port_fwd_cfg(qdma->eth,
> REG_GDM_FWD_CFG(port->id),
> FE_PSE_PORT_DROP);
> -
> - if (!--qdma->users) {
> - airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
> - GLOBAL_CFG_TX_DMA_EN_MASK |
> - GLOBAL_CFG_RX_DMA_EN_MASK);
> -
> - for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
> - if (!qdma->q_tx[i].ndesc)
> - continue;
> -
> - airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
> - }
> - }
> + qdma->users--;
>
> return 0;
> }
> @@ -3413,8 +3456,12 @@ static int airoha_probe(struct platform_device *pdev)
> if (err)
> goto error_netdev_free;
>
> - for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
> + for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
> airoha_qdma_start_napi(ð->qdma[i]);
> + airoha_qdma_set(ð->qdma[i], REG_QDMA_GLOBAL_CFG,
> + GLOBAL_CFG_TX_DMA_EN_MASK |
> + GLOBAL_CFG_RX_DMA_EN_MASK);
> + }
>
> for_each_child_of_node(pdev->dev.of_node, np) {
> if (!of_device_is_compatible(np, "airoha,eth-mac"))
> @@ -3440,6 +3487,8 @@ static int airoha_probe(struct platform_device *pdev)
> for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
> airoha_qdma_stop_napi(ð->qdma[i]);
>
> + airoha_hw_cleanup(eth);
> +
> for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> struct airoha_gdm_port *port = eth->ports[i];
> int j;
> @@ -3461,7 +3510,6 @@ static int airoha_probe(struct platform_device *pdev)
> }
> airoha_metadata_dst_free(port);
> }
> - airoha_hw_cleanup(eth);
> error_netdev_free:
> free_netdev(eth->napi_dev);
> platform_set_drvdata(pdev, NULL);
> @@ -3477,6 +3525,8 @@ static void airoha_remove(struct platform_device *pdev)
> for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
> airoha_qdma_stop_napi(ð->qdma[i]);
>
> + airoha_hw_cleanup(eth);
> +
> for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> struct airoha_gdm_port *port = eth->ports[i];
> int j;
> @@ -3497,7 +3547,6 @@ static void airoha_remove(struct platform_device *pdev)
> }
> airoha_metadata_dst_free(port);
> }
> - airoha_hw_cleanup(eth);
>
> free_netdev(eth->napi_dev);
> platform_set_drvdata(pdev, NULL);
>
> ---
> base-commit: 7d8297e26b4e20b5d1c3c3fe51fe81a1c7fbc823
> change-id: 20260618-airoha-bql-fixes-f57b2d108573
>
> Best regards,
> --
> Lorenzo Bianconi <lorenzo@kernel.org>
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [RFC v3 net-next] net: airoha: add HW GRO offload support
From: Lorenzo Bianconi @ 2026-06-18 14:42 UTC (permalink / raw)
To: andrew+netdev, davem, edumazet, kuba, pabeni
Cc: lorenzo, aleksander.lobakin, linux-arm-kernel, linux-mediatek,
netdev
Add hardware GRO offload support to the airoha_eth driver, leveraging
the EN7581/AN7583 SoC's 8 dedicated LRO hardware queues mapped to RX
queues 24-31. HW GRO offloading does not support Scatter-Gather (SG) so
it is required to increase the page_pool allocation order to 2 for RX
queues 24-31 (LRO queues).
Since HW GRO is configured per-QDMA and shared across all devices using
it, HW GRO is mutually exclusive with multiple active devices on the
same QDMA block. Call netdev_update_features() on sibling devices in
ndo_open/ndo_stop so that NETIF_F_GRO_HW availability is re-evaluated
when the QDMA user count changes.
Set CHECKSUM_PARTIAL with pseudo-header checksum on aggregated packets
so that L3-forwarded traffic is correctly handled by the GSO/TSO path
on the egress device.
Performance comparison between GRO and HW GRO has been carried out using
a 10Gbps NIC:
GRO: ~2.7 Gbps
HW GRO: ~8.1 Gbps
Tested-by: Madhur Agrawal <madhur.agrawal@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
Changes in RFC v3:
- Add missing TCP header length check.
- Fix TCP checkum calculation.
- Disable LRO running ndo_stop callback.
- Implement packet header split in order to support HW-GRO
- Link to v2: https://lore.kernel.org/r/20260610-airoha-eth-lro-v2-1-54be99b9a2d5@kernel.org
Changes in v2:
- Rebase on top of net-next main branch.
- Link to v1: https://lore.kernel.org/r/20260606-airoha-eth-lro-v1-1-0ebceb0eafc3@kernel.org
Changes in v1:
- Please note this patch depends on the following patch not applied yet
to net-next
https://lore.kernel.org/netdev/20260606-airoha_qdma_users-no-atomic-v1-1-86e2d6a1bfaf@kernel.org/T/#u
- Restrict LRO to single user QDMA.
- Introduce some more sanity checks.
- Disable scatter-gather for LRO queues.
- Run netif_receive_skb() for LRO packets.
- Link to v3: https://lore.kernel.org/r/20260528-airoha-eth-lro-v3-1-dd09c1fb000e@kernel.org
Changes in RFC v3:
- Fix double-free of the page_pool of airoha_qdma_lro_rx_process()
fails.
- Set AIROHA_LRO_PAGE_ORDER according to PAGE_SIZE.
- Add missig gso metadata for the LRO packet.
- Link to v2: https://lore.kernel.org/r/20260526-airoha-eth-lro-v2-1-24e2a9e7a397@kernel.org
Changes in RFC v2:
- Improve performances fixing buf_size computation.
- Fix possible overflow in REG_CDM_LRO_LIMIT() register configuration.
- Require the device to be not running before configuring LRO.
- Fix configuration order in airoha_fe_lro_is_enabled().
- Check skb header length in airoha_qdma_lro_rx_process().
- Do not check net_device feature in airoha_qdma_rx_process() before
executing airoha_qdma_lro_rx_process() but rely on
airoha_qdma_lro_rx_process() logic.
- Fix possible double recycle in airoha_qdma_rx_process() for LRO
packets.
- Always use AIROHA_RXQ_LRO_MAX_AGG_COUNT macro for max LRO aggregated
fragments in airoha_fe_lro_init_rx_queue().
- Link to v1: https://lore.kernel.org/r/20260520-airoha-eth-lro-v1-1-129cc33766e9@kernel.org
---
drivers/net/ethernet/airoha/airoha_eth.c | 364 ++++++++++++++++++++--
drivers/net/ethernet/airoha/airoha_eth.h | 24 ++
drivers/net/ethernet/airoha/airoha_regs.h | 22 +-
3 files changed, 386 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 64dde6464f3f..2aa6915d424e 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -10,8 +10,10 @@
#include <linux/tcp.h>
#include <linux/u64_stats_sync.h>
#include <net/dst_metadata.h>
+#include <net/ip6_checksum.h>
#include <net/page_pool/helpers.h>
#include <net/pkt_cls.h>
+#include <net/tcp.h>
#include <uapi/linux/ppp_defs.h>
#include "airoha_regs.h"
@@ -486,6 +488,73 @@ static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth)
CDM_CRSN_QSEL_Q1));
}
+static void airoha_fe_lro_rxq_enable(struct airoha_eth *eth, int qdma_id,
+ int lro_queue_index, int qid,
+ int buf_size)
+{
+ int id = qdma_id + 1;
+
+ airoha_fe_rmw(eth, REG_CDM_LRO_LIMIT(id),
+ CDM_LRO_AGG_NUM_MASK | CDM_LRO_AGG_SIZE_MASK,
+ FIELD_PREP(CDM_LRO_AGG_SIZE_MASK, buf_size) |
+ FIELD_PREP(CDM_LRO_AGG_NUM_MASK,
+ AIROHA_RXQ_LRO_MAX_AGG_COUNT));
+ airoha_fe_rmw(eth, REG_CDM_LRO_AGE_TIME(id),
+ CDM_LRO_AGE_TIME_MASK | CDM_LRO_AGG_TIME_MASK,
+ FIELD_PREP(CDM_LRO_AGE_TIME_MASK,
+ AIROHA_RXQ_LRO_MAX_AGE_TIME) |
+ FIELD_PREP(CDM_LRO_AGG_TIME_MASK,
+ AIROHA_RXQ_LRO_MAX_AGG_TIME));
+ airoha_fe_rmw(eth, REG_CDM_LRO_RXQ(id, lro_queue_index),
+ LRO_RXQ_MASK(lro_queue_index),
+ __field_prep(LRO_RXQ_MASK(lro_queue_index), qid));
+ airoha_fe_set(eth, REG_CDM_LRO_EN(id), BIT(lro_queue_index));
+}
+
+static void airoha_fe_lro_disable(struct airoha_eth *eth, int qdma_id)
+{
+ int i, id = qdma_id + 1;
+
+ airoha_fe_clear(eth, REG_CDM_LRO_EN(id), LRO_RXQ_EN_MASK);
+ airoha_fe_clear(eth, REG_CDM_LRO_LIMIT(id),
+ CDM_LRO_AGG_NUM_MASK | CDM_LRO_AGG_SIZE_MASK);
+ airoha_fe_clear(eth, REG_CDM_LRO_AGE_TIME(id),
+ CDM_LRO_AGE_TIME_MASK | CDM_LRO_AGG_TIME_MASK);
+ for (i = 0; i < AIROHA_MAX_NUM_LRO_QUEUES; i++)
+ airoha_fe_clear(eth, REG_CDM_LRO_RXQ(id, i), LRO_RXQ_MASK(i));
+}
+
+static bool airoha_fe_lro_is_enabled(struct airoha_eth *eth, int qdma_id)
+{
+ return airoha_fe_get(eth, REG_CDM_LRO_EN(qdma_id + 1),
+ LRO_RXQ_EN_MASK);
+}
+
+static void airoha_dev_lro_enable(struct airoha_gdm_dev *dev)
+{
+ struct airoha_qdma *qdma = dev->qdma;
+ struct airoha_eth *eth = qdma->eth;
+ int qdma_id = qdma - ð->qdma[0];
+ int i, lro_queue_index = 0;
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
+ struct airoha_queue *q = &qdma->q_rx[i];
+ u32 size;
+
+ if (!q->ndesc)
+ continue;
+
+ if (!airoha_qdma_is_lro_queue(q))
+ continue;
+
+ size = SKB_WITH_OVERHEAD(AIROHA_RX_LEN(q->buf_size));
+ size = min_t(u32, size, CDM_LRO_AGG_SIZE_MASK);
+ airoha_fe_lro_rxq_enable(eth, qdma_id, lro_queue_index, i,
+ size);
+ lro_queue_index++;
+ }
+}
+
static int airoha_fe_init(struct airoha_eth *eth)
{
airoha_fe_maccr_init(eth);
@@ -611,6 +680,7 @@ static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)
e->dma_addr = page_pool_get_dma_addr(page) + offset;
e->dma_len = SKB_WITH_OVERHEAD(AIROHA_RX_LEN(q->buf_size));
+ WRITE_ONCE(desc->tcp_ts_reply, 0);
val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len);
WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr));
@@ -652,12 +722,173 @@ airoha_qdma_get_gdm_dev(struct airoha_eth *eth, struct airoha_qdma_desc *desc)
return port->devs[d] ? port->devs[d] : ERR_PTR(-ENODEV);
}
+static struct sk_buff *airoha_qdma_lro_rx_skb(struct airoha_queue *q,
+ struct airoha_qdma_desc *desc,
+ struct airoha_queue_entry *e)
+{
+ u32 len, th_off, tcp_ack_seq, agg_count, data_off, data_len;
+ u32 desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
+ u32 msg1 = le32_to_cpu(READ_ONCE(desc->msg1));
+ u32 msg2 = le32_to_cpu(READ_ONCE(desc->msg2));
+ u32 msg3 = le32_to_cpu(READ_ONCE(desc->msg3));
+ struct skb_shared_info *shinfo;
+ u16 tcp_win, l2_len;
+ struct sk_buff *skb;
+ struct tcphdr *th;
+ struct page *page;
+ bool ipv4, ipv6;
+
+ ipv4 = FIELD_GET(QDMA_ETH_RXMSG_IP4_MASK, msg1);
+ ipv6 = FIELD_GET(QDMA_ETH_RXMSG_IP6_MASK, msg1);
+ if (!ipv4 && !ipv6)
+ return NULL;
+
+ l2_len = FIELD_GET(QDMA_ETH_RXMSG_L2_LEN_MASK, msg2);
+ len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
+
+ if (ipv4) {
+ struct iphdr *iph;
+
+ if (len < l2_len + sizeof(*iph))
+ return NULL;
+
+ iph = (struct iphdr *)(e->buf + l2_len);
+ if (iph->protocol != IPPROTO_TCP)
+ return NULL;
+
+ if (iph->ihl < 5)
+ return NULL;
+
+ th_off = l2_len + (iph->ihl << 2);
+ if (len < th_off)
+ return NULL;
+
+ iph->tot_len = cpu_to_be16(len - l2_len);
+ iph->check = 0;
+ iph->check = ip_fast_csum((void *)iph, iph->ihl);
+ } else {
+ struct ipv6hdr *ip6h;
+
+ th_off = l2_len + sizeof(*ip6h);
+ if (len < th_off)
+ return NULL;
+
+ ip6h = (struct ipv6hdr *)(e->buf + l2_len);
+ if (ip6h->nexthdr != NEXTHDR_TCP)
+ return NULL;
+
+ ip6h->payload_len = cpu_to_be16(len - th_off);
+ }
+
+ if (len < th_off + sizeof(*th))
+ return NULL;
+
+ th = (struct tcphdr *)(e->buf + th_off);
+ if (th->doff < 5)
+ return NULL;
+
+ data_off = th_off + (th->doff << 2);
+ if (len < data_off)
+ return NULL;
+
+ tcp_win = FIELD_GET(QDMA_ETH_RXMSG_TCP_WIN_MASK, msg3);
+ tcp_ack_seq = le32_to_cpu(READ_ONCE(desc->data));
+ th->ack_seq = cpu_to_be32(tcp_ack_seq);
+ th->window = cpu_to_be16(tcp_win);
+
+ /* Check tcp timestamp option */
+ if (th->doff == (sizeof(*th) + TCPOLEN_TSTAMP_ALIGNED) / 4) {
+ u32 topt = get_unaligned_be32(th + 1);
+
+ if (topt == ((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
+ u8 *ptr = (u8 *)th + sizeof(*th) + 2 * sizeof(__be32);
+ __le32 tcp_ts_reply = READ_ONCE(desc->tcp_ts_reply);
+
+ put_unaligned_be32(le32_to_cpu(tcp_ts_reply), ptr);
+ }
+ }
+
+ if (ipv4) {
+ struct iphdr *iph = (struct iphdr *)(e->buf + l2_len);
+
+ th->check = ~tcp_v4_check(len - th_off, iph->saddr,
+ iph->daddr, 0);
+ } else {
+ struct ipv6hdr *ip6h = (struct ipv6hdr *)(e->buf + l2_len);
+
+ th->check = ~tcp_v6_check(len - th_off, &ip6h->saddr,
+ &ip6h->daddr, 0);
+ }
+
+ /* Split network headers and payload to rely on GRO.
+ * We need to do it in the driver since the NIC does
+ * not support it.
+ */
+ skb = napi_alloc_skb(&q->napi, data_off);
+ if (!skb)
+ return NULL;
+
+ __skb_put(skb, data_off);
+ memcpy(skb->data, e->buf, data_off);
+
+ page = virt_to_head_page(e->buf);
+ data_len = len - data_off;
+ shinfo = skb_shinfo(skb);
+ skb_add_rx_frag(skb, shinfo->nr_frags, page,
+ e->buf + data_off - page_address(page), data_len,
+ q->buf_size);
+
+ shinfo->gso_type = ipv4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
+ agg_count = FIELD_GET(QDMA_ETH_RXMSG_AGG_COUNT_MASK, msg2);
+ shinfo->gso_size = DIV_ROUND_UP(data_len, agg_count);
+ shinfo->gso_segs = agg_count;
+
+ skb->csum_start = skb_headroom(skb) + th_off;
+ skb->csum_offset = offsetof(struct tcphdr, check);
+ skb->ip_summed = CHECKSUM_PARTIAL;
+
+ return skb;
+}
+
+static struct sk_buff *airoha_qdma_build_rx_skb(struct airoha_queue *q,
+ struct airoha_qdma_desc *desc,
+ struct airoha_queue_entry *e,
+ struct net_device *dev)
+{
+ u32 msg2 = le32_to_cpu(READ_ONCE(desc->msg2));
+ int qid = q - &q->qdma->q_rx[0];
+ struct sk_buff *skb;
+
+ if (FIELD_GET(QDMA_ETH_RXMSG_AGG_COUNT_MASK, msg2) > 1) { /* LRO */
+ skb = airoha_qdma_lro_rx_skb(q, desc, e);
+ if (!skb)
+ return NULL;
+ } else {
+ u32 desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
+ u32 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
+
+ skb = napi_build_skb(e->buf - AIROHA_RX_HEADROOM, q->buf_size);
+ if (!skb)
+ return NULL;
+
+ skb_reserve(skb, AIROHA_RX_HEADROOM);
+ __skb_put(skb, len);
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ }
+
+ skb_mark_for_recycle(skb);
+ skb->dev = dev;
+ skb_record_rx_queue(skb, qid);
+ skb->protocol = eth_type_trans(skb, dev);
+
+ return skb;
+}
+
static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
{
enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool);
- struct airoha_qdma *qdma = q->qdma;
- struct airoha_eth *eth = qdma->eth;
- int qid = q - &qdma->q_rx[0];
+ struct airoha_eth *eth = q->qdma->eth;
int done = 0;
while (done < budget) {
@@ -693,18 +924,9 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
netdev = netdev_from_priv(dev);
if (!q->skb) { /* first buffer */
- q->skb = napi_build_skb(e->buf - AIROHA_RX_HEADROOM,
- q->buf_size);
+ q->skb = airoha_qdma_build_rx_skb(q, desc, e, netdev);
if (!q->skb)
goto free_frag;
-
- skb_reserve(q->skb, AIROHA_RX_HEADROOM);
- __skb_put(q->skb, len);
- skb_mark_for_recycle(q->skb);
- q->skb->dev = netdev;
- q->skb->protocol = eth_type_trans(q->skb, netdev);
- q->skb->ip_summed = CHECKSUM_UNNECESSARY;
- skb_record_rx_queue(q->skb, qid);
} else { /* scattered frame */
struct skb_shared_info *shinfo = skb_shinfo(q->skb);
int nr_frags = shinfo->nr_frags;
@@ -795,12 +1017,10 @@ static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)
static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
struct airoha_qdma *qdma, int ndesc)
{
- const struct page_pool_params pp_params = {
- .order = 0,
+ struct page_pool_params pp_params = {
.pool_size = 256,
.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
.dma_dir = DMA_FROM_DEVICE,
- .max_len = PAGE_SIZE,
.nid = NUMA_NO_NODE,
.dev = qdma->eth->dev,
.napi = &q->napi,
@@ -808,9 +1028,10 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
struct airoha_eth *eth = qdma->eth;
int qid = q - &qdma->q_rx[0], thr;
dma_addr_t dma_addr;
+ bool lro_q;
- q->buf_size = PAGE_SIZE / 2;
q->qdma = qdma;
+ lro_q = airoha_qdma_is_lro_queue(q);
q->entry = devm_kzalloc(eth->dev, ndesc * sizeof(*q->entry),
GFP_KERNEL);
@@ -822,6 +1043,9 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
if (!q->desc)
return -ENOMEM;
+ pp_params.order = lro_q ? AIROHA_LRO_PAGE_ORDER : 0;
+ pp_params.max_len = PAGE_SIZE << pp_params.order;
+
q->page_pool = page_pool_create(&pp_params);
if (IS_ERR(q->page_pool)) {
int err = PTR_ERR(q->page_pool);
@@ -830,6 +1054,7 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
return err;
}
+ q->buf_size = lro_q ? pp_params.max_len : pp_params.max_len / 2;
q->ndesc = ndesc;
netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll);
@@ -843,7 +1068,12 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
FIELD_PREP(RX_RING_THR_MASK, thr));
airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head));
- airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK);
+ if (lro_q)
+ airoha_qdma_clear(qdma, REG_RX_SCATTER_CFG(qid),
+ RX_RING_SG_EN_MASK);
+ else
+ airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid),
+ RX_RING_SG_EN_MASK);
airoha_qdma_fill_rx_queue(q);
@@ -865,6 +1095,7 @@ static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q)
page_pool_get_dma_dir(q->page_pool));
page_pool_put_full_page(q->page_pool, page, false);
/* Reset DMA descriptor */
+ WRITE_ONCE(desc->tcp_ts_reply, 0);
WRITE_ONCE(desc->ctrl, 0);
WRITE_ONCE(desc->addr, 0);
WRITE_ONCE(desc->data, 0);
@@ -1802,6 +2033,37 @@ static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
spin_unlock(&port->stats_lock);
}
+static void airoha_update_netdev_features(struct airoha_gdm_dev *dev)
+{
+ struct airoha_eth *eth = dev->eth;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
+ struct airoha_gdm_port *port = eth->ports[i];
+ int j;
+
+ if (!port)
+ continue;
+
+ for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
+ struct airoha_gdm_dev *iter_dev = port->devs[j];
+ struct net_device *netdev;
+
+ if (!iter_dev || iter_dev == dev)
+ continue;
+
+ if (iter_dev->qdma != dev->qdma)
+ continue;
+
+ netdev = netdev_from_priv(iter_dev);
+ if (netdev->reg_state != NETREG_REGISTERED)
+ continue;
+
+ netdev_update_features(netdev);
+ }
+ }
+}
+
static int airoha_dev_open(struct net_device *netdev)
{
int err, len = ETH_HLEN + netdev->mtu + ETH_FCS_LEN;
@@ -1809,6 +2071,17 @@ static int airoha_dev_open(struct net_device *netdev)
struct airoha_gdm_port *port = dev->port;
u32 cur_len, pse_port = FE_PSE_PORT_PPE1;
struct airoha_qdma *qdma = dev->qdma;
+ int qdma_id = qdma - &qdma->eth->qdma[0];
+
+ /* HW GRO is configured on the QDMA and it is shared between
+ * all the devices using it. Refuse to open a second device on
+ * the same QDMA if HW GRO is enabled on any device sharing it.
+ */
+ if (qdma->users && airoha_fe_lro_is_enabled(qdma->eth, qdma_id)) {
+ netdev_warn(netdev, "required to disable HW GRO on QDMA%d\n",
+ qdma_id);
+ return -EBUSY;
+ }
netif_tx_start_all_queues(netdev);
err = airoha_set_vip_for_gdm_port(dev, true);
@@ -1848,6 +2121,11 @@ static int airoha_dev_open(struct net_device *netdev)
airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id),
pse_port);
+ if (netdev->features & NETIF_F_GRO_HW)
+ airoha_dev_lro_enable(dev);
+
+ airoha_update_netdev_features(dev);
+
return 0;
}
@@ -1895,6 +2173,9 @@ static int airoha_dev_stop(struct net_device *netdev)
FE_PSE_PORT_DROP);
if (!--qdma->users) {
+ int qdma_id = qdma - &qdma->eth->qdma[0];
+
+ airoha_fe_lro_disable(qdma->eth, qdma_id);
airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
GLOBAL_CFG_TX_DMA_EN_MASK |
GLOBAL_CFG_RX_DMA_EN_MASK);
@@ -1907,6 +2188,8 @@ static int airoha_dev_stop(struct net_device *netdev)
}
}
+ airoha_update_netdev_features(dev);
+
return 0;
}
@@ -2176,6 +2459,41 @@ int airoha_get_fe_port(struct airoha_gdm_dev *dev)
}
}
+static netdev_features_t airoha_dev_fix_features(struct net_device *netdev,
+ netdev_features_t features)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+ struct airoha_qdma *qdma = dev->qdma;
+
+ if (qdma->users > 1)
+ features &= ~NETIF_F_GRO_HW;
+
+ return features;
+}
+
+static int airoha_dev_set_features(struct net_device *netdev,
+ netdev_features_t features)
+{
+ netdev_features_t diff = netdev->features ^ features;
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ if (!(diff & NETIF_F_GRO_HW))
+ return 0;
+
+ if (!netif_running(netdev))
+ return 0;
+
+ if (features & NETIF_F_GRO_HW) {
+ airoha_dev_lro_enable(dev);
+ } else {
+ int qdma_id = dev->qdma - &dev->eth->qdma[0];
+
+ airoha_fe_lro_disable(dev->eth, qdma_id);
+ }
+
+ return 0;
+}
+
static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
struct net_device *netdev)
{
@@ -3102,6 +3420,8 @@ static const struct net_device_ops airoha_netdev_ops = {
.ndo_stop = airoha_dev_stop,
.ndo_change_mtu = airoha_dev_change_mtu,
.ndo_select_queue = airoha_dev_select_queue,
+ .ndo_fix_features = airoha_dev_fix_features,
+ .ndo_set_features = airoha_dev_set_features,
.ndo_start_xmit = airoha_dev_xmit,
.ndo_get_stats64 = airoha_dev_get_stats64,
.ndo_set_mac_address = airoha_dev_set_macaddr,
@@ -3189,11 +3509,9 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
netdev->ethtool_ops = &airoha_ethtool_ops;
netdev->max_mtu = AIROHA_MAX_MTU;
netdev->watchdog_timeo = 5 * HZ;
- netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | NETIF_F_TSO6 |
- NETIF_F_IPV6_CSUM | NETIF_F_SG | NETIF_F_TSO |
- NETIF_F_HW_TC;
- netdev->features |= netdev->hw_features;
- netdev->vlan_features = netdev->hw_features;
+ netdev->hw_features = AIROHA_HW_FEATURES | NETIF_F_GRO_HW;
+ netdev->features |= AIROHA_HW_FEATURES;
+ netdev->vlan_features = AIROHA_HW_FEATURES;
SET_NETDEV_DEV(netdev, eth->dev);
/* reserve hw queues for HTB offloading */
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 41d2e7a1f9fb..c13757a88aba 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -44,6 +44,18 @@
(_n) == 15 ? 128 : \
(_n) == 0 ? 1024 : 16)
+#define AIROHA_LRO_PAGE_ORDER order_base_2(SZ_16K / PAGE_SIZE)
+#define AIROHA_MAX_NUM_LRO_QUEUES 8
+#define AIROHA_RXQ_LRO_EN_MASK GENMASK(31, 24)
+#define AIROHA_RXQ_LRO_MAX_AGG_COUNT 64
+#define AIROHA_RXQ_LRO_MAX_AGG_TIME 100
+#define AIROHA_RXQ_LRO_MAX_AGE_TIME 2000
+
+#define AIROHA_HW_FEATURES \
+ (NETIF_F_IP_CSUM | NETIF_F_RXCSUM | \
+ NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | \
+ NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_TC)
+
#define PSE_RSV_PAGES 128
#define PSE_QUEUE_RSV_PAGES 64
@@ -673,6 +685,18 @@ static inline bool airoha_is_7583(struct airoha_eth *eth)
return eth->soc->version == 0x7583;
}
+static inline bool airoha_qdma_is_lro_queue(struct airoha_queue *q)
+{
+ struct airoha_qdma *qdma = q->qdma;
+ int qid = q - &qdma->q_rx[0];
+
+ /* EN7581 SoC supports at most 8 LRO rx queues */
+ BUILD_BUG_ON(hweight32(AIROHA_RXQ_LRO_EN_MASK) >
+ AIROHA_MAX_NUM_LRO_QUEUES);
+
+ return !!(AIROHA_RXQ_LRO_EN_MASK & BIT(qid));
+}
+
int airoha_get_fe_port(struct airoha_gdm_dev *dev);
bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
struct airoha_gdm_dev *dev);
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index 436f3c8779c1..dfc786583774 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -122,6 +122,20 @@
#define CDM_CRSN_QSEL_REASON_MASK(_n) \
GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3))
+#define REG_CDM_LRO_RXQ(_n, _m) (CDM_BASE(_n) + 0x78 + ((_m) & 0x4))
+#define LRO_RXQ_MASK(_n) GENMASK(4 + (((_n) & 0x3) << 3), ((_n) & 0x3) << 3)
+
+#define REG_CDM_LRO_EN(_n) (CDM_BASE(_n) + 0x80)
+#define LRO_RXQ_EN_MASK GENMASK(7, 0)
+
+#define REG_CDM_LRO_LIMIT(_n) (CDM_BASE(_n) + 0x84)
+#define CDM_LRO_AGG_NUM_MASK GENMASK(23, 16)
+#define CDM_LRO_AGG_SIZE_MASK GENMASK(15, 0)
+
+#define REG_CDM_LRO_AGE_TIME(_n) (CDM_BASE(_n) + 0x88)
+#define CDM_LRO_AGE_TIME_MASK GENMASK(31, 16)
+#define CDM_LRO_AGG_TIME_MASK GENMASK(15, 0)
+
#define REG_GDM_FWD_CFG(_n) GDM_BASE(_n)
#define GDM_PAD_EN_MASK BIT(28)
#define GDM_DROP_CRC_ERR_MASK BIT(23)
@@ -883,9 +897,15 @@
#define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21)
#define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16)
#define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0)
+/* RX MSG2 */
+#define QDMA_ETH_RXMSG_AGG_COUNT_MASK GENMASK(31, 24)
+#define QDMA_ETH_RXMSG_L2_LEN_MASK GENMASK(6, 0)
+/* RX MSG3 */
+#define QDMA_ETH_RXMSG_AGG_LEN_MASK GENMASK(31, 16)
+#define QDMA_ETH_RXMSG_TCP_WIN_MASK GENMASK(15, 0)
struct airoha_qdma_desc {
- __le32 rsv;
+ __le32 tcp_ts_reply;
__le32 ctrl;
__le32 addr;
__le32 data;
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v2 00/78] drm/bridge: Convert all reset users to create_state
From: Luca Ceresoli @ 2026-06-18 13:38 UTC (permalink / raw)
To: Maxime Ripard, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
Maarten Lankhorst, Thomas Zimmermann, David Airlie, Simona Vetter
Cc: Dmitry Baryshkov, dri-devel, Laurent Pinchart, Jagan Teki,
Liu Ying, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, imx, linux-arm-kernel, Andy Yan, Phong LE,
Douglas Anderson, Inki Dae, Marek Szyprowski, Philipp Zabel,
Paul Cercueil, linux-mips, Chun-Kuang Hu, Matthias Brugger,
AngeloGioacchino Del Regno, linux-mediatek, linux-kernel,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-amlogic,
Tomi Valkeinen, Geert Uytterhoeven, Magnus Damm, Kieran Bingham,
linux-renesas-soc, Biju Das, Heiko Stuebner, Sandy Huang,
linux-rockchip, Yannick Fertre, Raphael Gallais-Pou,
Philippe Cornu, Maxime Coquelin, Alexandre Torgue, linux-stm32,
Jyri Sarha, Tomi Valkeinen, Dave Stevenson, Maíra Canal,
Raspberry Pi Kernel Maintenance, Icenowy Zheng, Michal Simek
In-Reply-To: <20260618-terrestrial-abiding-tamarin-01befc@houat>
Hi Maxime,
On Thu Jun 18, 2026 at 1:20 PM CEST, Maxime Ripard wrote:
> Hi,
>
> On Mon, Jun 08, 2026 at 04:35:42PM +0200, Maxime Ripard wrote:
>> Hi,
>>
>> All the bridges use reset to create a blank state only and don't use it
>> to reset the hardware at all. This is what the new atomic_create_state
>> is exactly supposed to be doing, so we can convert all existing bridge
>> users to it, and remove the reset hook and helpers.
>>
>> Let me know what you think,
>> Maxime
>>
>> Signed-off-by: Maxime Ripard <mripard@kernel.org>
>
> FTR, Thomas on IRC yesterday[1] added
> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
>
> Unless another review shows up, I intend to merge this tomorrow
Did you have a look at my questions for patches 7 and 8?
I was planning to review the following patches but that would be based on
what I asked there.
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [RFC PATCH net-next v8 11/12] net: pcs: airoha: add PCS driver for Airoha AN7581 SoC
From: Benjamin Larsson @ 2026-06-18 13:30 UTC (permalink / raw)
To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Simon Horman, Jonathan Corbet, Shuah Khan,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-12-ansuelsmth@gmail.com>
Hi.
On 18/06/2026 14:57, Christian Marangi wrote:
> Add PCS driver for Airoha AN7581 SoC for Ethernet/PON/PCIe/USB SERDES
> and permit usage of external PHY or connected SFP cage. Supported modes
> are USXGMII, 10G-BASER, 2500BASE-X, 1000BASE-X and SGMII.
>
> The driver probe and register the various needed registers and register as
> a PCS provider for fwnode usage.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> drivers/net/pcs/Kconfig | 2 +
> drivers/net/pcs/Makefile | 2 +
> drivers/net/pcs/airoha/Kconfig | 12 +
> drivers/net/pcs/airoha/Makefile | 7 +
> drivers/net/pcs/airoha/pcs-airoha-common.c | 1324 +++++++++++++
> drivers/net/pcs/airoha/pcs-airoha.h | 1311 ++++++++++++
> drivers/net/pcs/airoha/pcs-an7581.c | 2093 ++++++++++++++++++++
> 7 files changed, 4751 insertions(+)
> create mode 100644 drivers/net/pcs/airoha/Kconfig
> create mode 100644 drivers/net/pcs/airoha/Makefile
> create mode 100644 drivers/net/pcs/airoha/pcs-airoha-common.c
> create mode 100644 drivers/net/pcs/airoha/pcs-airoha.h
> create mode 100644 drivers/net/pcs/airoha/pcs-an7581.c
My comment that the files should be renamed now instead of later when
support for other airoha platforms are added still stands. The common
code is not common among other platforms (EN7523 as example).
MvH
Benjamin Larsson
^ permalink raw reply
* Re: [RFC PATCH net-next v8 12/12] net: airoha: add phylink support
From: Lorenzo Bianconi @ 2026-06-18 13:15 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Heiner Kallweit,
Russell King, Saravana Kannan, Philipp Zabel, Nathan Chancellor,
Nick Desaulniers, Bill Wendling, Justin Stitt, netdev, devicetree,
linux-kernel, linux-doc, linux-arm-kernel, linux-mediatek, llvm,
Maxime Chevallier
In-Reply-To: <20260618125752.1223-13-ansuelsmth@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 8113 bytes --]
[...]
> +static void airoha_mac_config(struct phylink_config *config, unsigned int mode,
> + const struct phylink_link_state *state)
> +{
> +}
> +
> +static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
> + unsigned int mode, phy_interface_t interface,
> + int speed, int duplex, bool tx_pause, bool rx_pause)
> +{
> + struct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,
> + phylink_config);
> + struct airoha_gdm_port *port = dev->port;
> + struct airoha_eth *eth = dev->eth;
> + u32 frag_size_tx, frag_size_rx;
> + u32 mask, val;
> +
> + /* TX/RX frag is configured only for GDM4 */
> + if (port->id != AIROHA_GDM4_IDX)
> + return;
> +
> + switch (speed) {
> + case SPEED_10000:
> + case SPEED_5000:
> + frag_size_tx = 8;
> + frag_size_rx = 8;
> + break;
> + case SPEED_2500:
> + frag_size_tx = 2;
> + frag_size_rx = 1;
> + break;
> + default:
> + frag_size_tx = 1;
> + frag_size_rx = 0;
> + }
> +
> + spin_lock(&port->lock);
Using a spin_lock seems overkill here to me since airoha_mac_link_up()
run in the process context and the spin_lock you are acquiring here
was just used for stats. Since mac_link_up is running in some cases
acquiring RTNL, I guess you can even do something like:
bool rtnl = rtnl_is_locked();
if (!rtnl)
rtnl_lock();
...
if (!rtnl)
rtnl_unlock();
Regards,
Lorenzo
> +
> + /* Configure TX/RX frag based on speed */
> + if (dev->nbq == 1) {
> + mask = GDM4_SGMII1_TX_FRAG_SIZE_MASK;
> + val = FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK,
> + frag_size_tx);
> + } else {
> + mask = GDM4_SGMII0_TX_FRAG_SIZE_MASK;
> + val = FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK,
> + frag_size_tx);
> + }
> + airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, mask, val);
> +
> + if (dev->nbq == 1) {
> + mask = GDM4_SGMII1_RX_FRAG_SIZE_MASK;
> + val = FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK,
> + frag_size_rx);
> + } else {
> + mask = GDM4_SGMII0_RX_FRAG_SIZE_MASK;
> + val = FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK,
> + frag_size_rx);
> + }
> + airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, mask, val);
> +
> + spin_unlock(&port->lock);
> +}
> +
> +/* Nothing to do in MAC, everything is handled in PCS */
> +static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode,
> + phy_interface_t interface)
> +{
> +}
> +
> +static const struct phylink_mac_ops airoha_phylink_ops = {
> + .mac_config = airoha_mac_config,
> + .mac_link_up = airoha_mac_link_up,
> + .mac_link_down = airoha_mac_link_down,
> +};
> +
> +static int airoha_fill_available_pcs(struct phylink_config *config,
> + struct phylink_pcs **available_pcs,
> + unsigned int num_possible_pcs)
> +{
> + struct device *dev = config->dev;
> +
> + return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
> + num_possible_pcs);
> +}
> +
> +static int airoha_setup_phylink(struct net_device *netdev)
> +{
> + struct airoha_gdm_dev *dev = netdev_priv(netdev);
> + struct device_node *np = netdev->dev.of_node;
> + struct airoha_gdm_port *port = dev->port;
> + struct phylink_config *config;
> + phy_interface_t phy_mode;
> + struct phylink *phylink;
> + int err;
> +
> + err = of_get_phy_mode(np, &phy_mode);
> + if (err) {
> + dev_err(&netdev->dev, "incorrect phy-mode\n");
> + return err;
> + }
> +
> + config = &dev->phylink_config;
> + config->dev = &netdev->dev;
> + config->type = PHYLINK_NETDEV;
> +
> + /*
> + * GDM1 only supports internal for Embedded Switch
> + * and doesn't require a PCS.
> + */
> + if (port->id == AIROHA_GDM1_IDX) {
> + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> + MAC_10000FD;
> +
> + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
> + config->supported_interfaces);
> + } else {
> + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> + MAC_10 | MAC_100 | MAC_1000 |
> + MAC_2500FD | MAC_5000FD | MAC_10000FD;
> +
> + config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config->dev));
> + config->fill_available_pcs = airoha_fill_available_pcs;
> +
> + __set_bit(PHY_INTERFACE_MODE_SGMII,
> + config->supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_1000BASEX,
> + config->supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_2500BASEX,
> + config->supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_10GBASER,
> + config->supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_USXGMII,
> + config->supported_interfaces);
> +
> + phy_interface_copy(config->pcs_interfaces,
> + config->supported_interfaces);
> + }
> +
> + phylink = phylink_create(config, of_fwnode_handle(np),
> + phy_mode, &airoha_phylink_ops);
> + if (IS_ERR(phylink))
> + return PTR_ERR(phylink);
> +
> + dev->phylink = phylink;
> +
> + return 0;
> +}
> +
> static int airoha_alloc_gdm_device(struct airoha_eth *eth,
> struct airoha_gdm_port *port,
> int nbq, struct device_node *np)
> @@ -3231,7 +3411,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
> dev->nbq = nbq;
> port->devs[index] = dev;
>
> - return 0;
> + return airoha_setup_phylink(netdev);
> }
>
> static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> @@ -3266,7 +3446,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> return -ENOMEM;
>
> port->id = id;
> - spin_lock_init(&port->stats_lock);
> + spin_lock_init(&port->lock);
> eth->ports[p] = port;
>
> err = airoha_metadata_dst_alloc(port);
> @@ -3457,6 +3637,8 @@ static int airoha_probe(struct platform_device *pdev)
> netdev = netdev_from_priv(dev);
> if (netdev->reg_state == NETREG_REGISTERED)
> unregister_netdev(netdev);
> + if (dev->phylink)
> + phylink_destroy(dev->phylink);
> of_node_put(netdev->dev.of_node);
> }
> airoha_metadata_dst_free(port);
> @@ -3493,6 +3675,7 @@ static void airoha_remove(struct platform_device *pdev)
>
> netdev = netdev_from_priv(dev);
> unregister_netdev(netdev);
> + phylink_destroy(dev->phylink);
> of_node_put(netdev->dev.of_node);
> }
> airoha_metadata_dst_free(port);
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 46b1c31939de..a6fef1777c7b 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -554,6 +554,9 @@ struct airoha_gdm_dev {
> int nbq;
>
> struct airoha_hw_stats stats;
> +
> + struct phylink *phylink;
> + struct phylink_config phylink_config;
> };
>
> struct airoha_gdm_port {
> @@ -561,8 +564,8 @@ struct airoha_gdm_port {
> int id;
> int users;
>
> - /* protect concurrent hw_stats accesses */
> - spinlock_t stats_lock;
> + /* protect concurrent hw_stats and frag register accesses */
> + spinlock_t lock;
>
> struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
> };
> diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
> index 436f3c8779c1..6ad91ca6dcd3 100644
> --- a/drivers/net/ethernet/airoha/airoha_regs.h
> +++ b/drivers/net/ethernet/airoha/airoha_regs.h
> @@ -358,6 +358,18 @@
> #define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)
> #define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)
>
> +#define REG_FE_GDM4_TMBI_FRAG 0x2028
> +#define GDM4_SGMII1_TX_WEIGHT_MASK GENMASK(31, 26)
> +#define GDM4_SGMII1_TX_FRAG_SIZE_MASK GENMASK(25, 16)
> +#define GDM4_SGMII0_TX_WEIGHT_MASK GENMASK(15, 10)
> +#define GDM4_SGMII0_TX_FRAG_SIZE_MASK GENMASK(9, 0)
> +
> +#define REG_FE_GDM4_RMBI_FRAG 0x202c
> +#define GDM4_SGMII1_RX_WEIGHT_MASK GENMASK(31, 26)
> +#define GDM4_SGMII1_RX_FRAG_SIZE_MASK GENMASK(25, 16)
> +#define GDM4_SGMII0_RX_WEIGHT_MASK GENMASK(15, 10)
> +#define GDM4_SGMII0_RX_FRAG_SIZE_MASK GENMASK(9, 0)
> +
> #define REG_MC_VLAN_EN 0x2100
> #define MC_VLAN_EN_MASK BIT(0)
>
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [RFC PATCH net-next v8 11/12] net: pcs: airoha: add PCS driver for Airoha AN7581 SoC
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Add PCS driver for Airoha AN7581 SoC for Ethernet/PON/PCIe/USB SERDES
and permit usage of external PHY or connected SFP cage. Supported modes
are USXGMII, 10G-BASER, 2500BASE-X, 1000BASE-X and SGMII.
The driver probe and register the various needed registers and register as
a PCS provider for fwnode usage.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/Kconfig | 2 +
drivers/net/pcs/Makefile | 2 +
drivers/net/pcs/airoha/Kconfig | 12 +
drivers/net/pcs/airoha/Makefile | 7 +
drivers/net/pcs/airoha/pcs-airoha-common.c | 1324 +++++++++++++
drivers/net/pcs/airoha/pcs-airoha.h | 1311 ++++++++++++
drivers/net/pcs/airoha/pcs-an7581.c | 2093 ++++++++++++++++++++
7 files changed, 4751 insertions(+)
create mode 100644 drivers/net/pcs/airoha/Kconfig
create mode 100644 drivers/net/pcs/airoha/Makefile
create mode 100644 drivers/net/pcs/airoha/pcs-airoha-common.c
create mode 100644 drivers/net/pcs/airoha/pcs-airoha.h
create mode 100644 drivers/net/pcs/airoha/pcs-an7581.c
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 2ce89d4bff6b..10ac9af04594 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -41,4 +41,6 @@ config PCS_RZN1_MIIC
Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to
RMII/RGMII, or can be set in pass-through mode for MII.
+source "drivers/net/pcs/airoha/Kconfig"
+
endmenu
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 3005cdd89ab7..91593aa8d926 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -9,3 +9,5 @@ obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o
obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
+
+obj-$(CONFIG_PCS_AIROHA) += airoha/
diff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig
new file mode 100644
index 000000000000..4ddd527b365f
--- /dev/null
+++ b/drivers/net/pcs/airoha/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PCS_AIROHA
+ tristate
+ select FWNODE_PCS
+
+config PCS_AIROHA_AN7581
+ tristate "Airoha AN7581 PCS driver"
+ select PCS_AIROHA
+ help
+ This module provides helper to phylink for managing the Airoha
+ AN7581 PCS for SoC Ethernet and PON SERDES.
diff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makefile
new file mode 100644
index 000000000000..c5201d5cc356
--- /dev/null
+++ b/drivers/net/pcs/airoha/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PCS_AIROHA) := pcs-airoha.o
+pcs-airoha-objs := pcs-airoha-common.o
+ifdef CONFIG_PCS_AIROHA_AN7581
+pcs-airoha-objs += pcs-an7581.o
+endif
diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c
new file mode 100644
index 000000000000..781f89adf3ab
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
@@ -0,0 +1,1324 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
+
+#include "pcs-airoha.h"
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+ AIROHA_SCU_ETH_XSI_SEL,
+ xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel, wan_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PON_XSI_SEL,
+ xsi_sel);
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+ AIROHA_SCU_WAN_SEL,
+ wan_sel);
+}
+
+static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ if (index == 0) {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI0_SEL,
+ xsi_sel);
+ } else {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI1_SEL,
+ xsi_sel);
+ }
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ int ret;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ airoha_pcs_setup_scu_eth(priv, interface);
+ break;
+ case AIROHA_PCS_PON:
+ airoha_pcs_setup_scu_pon(priv, interface);
+ break;
+ case AIROHA_PCS_PCIE:
+ airoha_pcs_setup_scu_pcie(priv, index, interface);
+ break;
+ case AIROHA_PCS_USB:
+ break;
+ }
+
+ /* TODO better handle reset from MAC */
+ ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_set_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ /* Disable Hibernation */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+ AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+ /* FIXME: wait Airoha */
+ /* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+ regmap_write(maps->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE,
+ priv->phy ? 0 : AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_init_sgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_init_hsgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_init_usxgmii(priv, index);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every interrupt */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+ /* Clear interrupt */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every Interrupt */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+ AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+ AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+ AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+ /* Clear any pending interrupt */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+ /* Interrupt saddly seems to be not weel supported for Link Down.
+ * PCS Poll is a must to correctly read and react on Cable Deatch
+ * as only cable attach interrupt are fired and Link Down interrupt
+ * are fired only in special case like AN restart.
+ */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return airoha_pcs_interrupt_init_sgmii(priv, index);
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ return airoha_pcs_interrupt_init_usxgmii(priv, index);
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+ unsigned int neg_mode, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr, lpa;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+ &lpa);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+ lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+ phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+
+ state->link = !!(bmsr & BMSR_LSTATUS);
+ state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
+ state->speed = SPEED_2500;
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 an_done, lpa;
+
+ /* Trigger HW workaround if needed. If an error is reported,
+ * consider link down and test again later.
+ */
+ if (data->rxlock_workaround && data->rxlock_workaround(priv, index)) {
+ state->link = false;
+ return;
+ }
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_2, &an_done);
+
+ state->link = !!(lpa & MDIO_USXGMII_LINK);
+ state->an_complete = !!(an_done & AIROHA_PCS_USXGMII_PCS_AN_COMPLETE);
+
+ phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state_10gbaser(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 status, curr_mode;
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1,
+ &status);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &curr_mode);
+
+ state->link = !!(status & AIROHA_PCS_USXGMII_RX_LINK_STUS);
+
+ switch (curr_mode & AIROHA_PCS_USXGMII_CUR_USXGMII_MODE) {
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G:
+ state->speed = SPEED_10000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G:
+ state->speed = SPEED_5000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G:
+ state->speed = SPEED_2500;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_get_state_sgmii(priv, neg_mode, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_get_state_hsgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ airoha_pcs_get_state_usxgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_get_state_10gbaser(priv, port->index, state);
+ break;
+ default:
+ return;
+ }
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+ int index = port->index;
+ u32 rate_adapt;
+ int ret;
+
+ maps = &priv->maps[port->index];
+ port->interface = interface;
+ data = priv->data;
+
+ /* Apply Analog and Digital configuration for PCS */
+ if (data->bringup) {
+ ret = data->bringup(priv, index, interface);
+ if (ret)
+ return ret;
+ }
+
+ /* Set final configuration for various modes */
+ airoha_pcs_init(priv, index, interface);
+
+ /* Configure Interrupt for various modes */
+ airoha_pcs_interrupt_init(priv, index, interface);
+
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ rate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS;
+
+ /* AN Auto Settings (Rate Adaptation) */
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+ else
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ } else {
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ }
+ }
+
+ /* Clear any force bit that my be set by bootloader */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0 |
+ AIROHA_PCS_FORCE_LINKDOWN_P0 |
+ AIROHA_PCS_FORCE_LINKUP_P0);
+ }
+
+ /* Toggle Rate Adaption for SGMII/HSGMII mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_clear_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ else
+ regmap_set_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ }
+
+ /* Setup AN Link Timer */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 an_timer;
+
+ an_timer = phylink_get_link_timer_ns(interface);
+
+ /* Value needs to be shifted by 4, seems value is internally * 16 */
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ an_timer >> 4));
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+ AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ an_timer >> 4));
+ }
+
+ /* Setup SGMII AN and advertisement in DEV_ABILITY */
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (advertise < 0)
+ return advertise;
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+ AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ advertise));
+
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ } else {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ }
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+ /* Toggle SGMII or 1000base-x mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN;
+
+ if (neg_mode & PHYLINK_PCS_NEG_INBAND)
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+ else
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Clear force speed bits and MAC mode */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ } else {
+ /* Enable compatibility with MAC PCS Layer */
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+ /* AN off force rate adaption, speed is set later in Link Up */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ }
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+ AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+ AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY);
+ }
+
+ /* Configure Flow Control on XFI */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+ permit_pause_to_mac ?
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+ 0);
+
+ return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ switch (port->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface, int speed, int duplex)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+ data = priv->data;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+ udelay(1);
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+ }
+ } else {
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ u32 mode;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_10000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+ mode = AIROHA_PCS_USXGMII_MODE_10000;
+ break;
+ case SPEED_5000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+ mode = AIROHA_PCS_USXGMII_MODE_5000;
+ break;
+ case SPEED_2500:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+ mode = AIROHA_PCS_USXGMII_MODE_2500;
+ break;
+ case SPEED_1000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+ mode = AIROHA_PCS_USXGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+ mode = AIROHA_PCS_USXGMII_MODE_100;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ /* Force USXGMII to selected speed */
+ regmap_update_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_MODE, mode);
+
+ if (interface == PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 force_speed;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_1000:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+ break;
+ case SPEED_100:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+ break;
+ case SPEED_10:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+ force_speed | rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ u32 ck_gen_mode;
+ u32 speed_reg;
+ u32 if_mode;
+
+ switch (speed) {
+ case SPEED_2500:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+ break;
+ case SPEED_1000:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+ break;
+ case SPEED_10:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+ break;
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+ if_mode);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+ ck_gen_mode |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+ }
+
+ regmap_update_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0,
+ speed_reg |
+ AIROHA_PCS_FORCE_SPD_MODE_P0);
+ }
+ }
+
+ if (data->link_up)
+ data->link_up(priv, port->index);
+
+ /* BPI BMI enable */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_link_down(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Select HSGMII or USXGMII in SCU regs */
+ airoha_pcs_setup_scu(priv, port->index, interface);
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+
+ /* Write 1 to trigger reset and clear */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+
+ usleep_range(1000, 2000);
+
+ /* Clear XFI MAC counter */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,
+ AIROHA_PCS_XFI_GLB_CNT_CLR);
+}
+
+static int airoha_pcs_post_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Frag disable */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31));
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31));
+
+ /* IPG NUM */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_IPG_NUM,
+ FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10));
+
+ /* Enable TX/RX flow control */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN);
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RX_FC_EN);
+
+ return 0;
+}
+
+static unsigned int airoha_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+ .pcs_inband_caps = airoha_pcs_inband_caps,
+ .pcs_pre_config = airoha_pcs_pre_config,
+ .pcs_post_config = airoha_pcs_post_config,
+ .pcs_get_state = airoha_pcs_get_state,
+ .pcs_config = airoha_pcs_config,
+ .pcs_an_restart = airoha_pcs_an_restart,
+ .pcs_link_up = airoha_pcs_link_up,
+ .pcs_link_down = airoha_pcs_link_down,
+};
+
+static int airoha_pcs_init_named_regmap(struct platform_device *pdev,
+ const char *name, struct regmap **regmap)
+{
+ struct regmap_config config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ };
+ void *base;
+
+ base = devm_platform_ioremap_resource_byname(pdev, name);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ config.name = name;
+ *regmap = devm_regmap_init_mmio(&pdev->dev, base, &config);
+
+ return PTR_ERR_OR_ZERO(*regmap);
+}
+
+static int airoha_pcs_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii", &maps->usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = priv->maps;
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac0", &maps[0].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an0", &maps[0].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs0", &maps[0].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp0", &maps[0].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii0", &maps[0].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii0", &maps[0].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac1", &maps[1].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an1", &maps[1].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs1", &maps[1].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp1", &maps[1].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii1", &maps[1].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii1", &maps[1].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma0", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma1", &priv->pcs_pma[1]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static struct phylink_pcs *airoha_pcs_get(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ struct airoha_pcs_priv *priv = data;
+ struct device *dev = priv->dev;
+ u64 index = 0;
+
+ switch (priv->data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_USB:
+ if (pcsspec->nargs) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ case AIROHA_PCS_PCIE:
+ if (pcsspec->nargs != 1) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ }
+
+ if (pcsspec->nargs)
+ index = pcsspec->args[0];
+
+ if (index >= priv->data->num_port) {
+ dev_err(dev, "invalid index cell in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &priv->ports[index].pcs;
+}
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+ const struct airoha_pcs_match_data *data;
+ struct device *dev = &pdev->dev;
+ struct airoha_pcs_priv *priv;
+ int index, ret;
+
+ data = of_device_get_match_data(dev);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->ports = devm_kcalloc(dev, data->num_port,
+ sizeof(*priv->ports), GFP_KERNEL);
+ if (!priv->ports)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->data = data;
+
+ if (data->port_type == AIROHA_PCS_USB) {
+ struct phy *phy;
+
+ phy = devm_phy_get(dev, NULL);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy), "failed to get phy\n");
+
+ priv->phy = phy;
+ }
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ ret = airoha_pcs_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_PCIE:
+ ret = airoha_pcs_pcie_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_USB:
+ ret = airoha_pcs_usb_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ }
+
+ if (data->alloc_regmap_fields) {
+ ret = data->alloc_regmap_fields(priv);
+ if (ret)
+ return ret;
+ }
+
+ /* SCU is used to toggle XFI or HSGMII in global SoC registers */
+ if (!priv->phy) {
+ priv->scu = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu");
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+ }
+
+ priv->rsts[0].id = "mac";
+ priv->rsts[1].id = "phy";
+ ret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+ /* For Ethernet PCS, read the AN7581 SoC revision to check if
+ * manual rx calibration is needed. This is only limited to
+ * any SoC revision before E2.
+ */
+ if (device_is_compatible(dev, "airoha,an7581-pcs-eth")) {
+ u32 val;
+
+ ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val);
+ if (ret)
+ return ret;
+
+ if (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) < 0x2)
+ priv->manual_rx_calib = true;
+ }
+
+ for (index = 0; index < data->num_port; index++) {
+ struct airoha_pcs_port *port = &priv->ports[index];
+
+ port->priv = priv;
+ port->index = index;
+ port->pcs.poll = true;
+ port->pcs.ops = &airoha_pcs_ops;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_PCIE:
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ port->pcs.supported_interfaces);
+ fallthrough;
+ case AIROHA_PCS_USB:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ port->pcs.supported_interfaces);
+ break;
+ }
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ return fwnode_pcs_add_provider(dev_fwnode(dev), airoha_pcs_get, priv);
+}
+
+static void airoha_pcs_remove(struct platform_device *pdev)
+{
+ struct airoha_pcs_priv *priv = platform_get_drvdata(pdev);
+ const struct airoha_pcs_match_data *data = priv->data;
+ int i;
+
+ fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+ rtnl_lock();
+
+ for (i = 0; i < data->num_port; i++) {
+ struct airoha_pcs_port *port = &priv->ports[i];
+
+ phylink_release_pcs(&port->pcs);
+ }
+
+ rtnl_unlock();
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_ETH,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+ .rxlock_workaround = an7581_pcs_rxlock_workaround,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_PON,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pcie = {
+ .num_port = 2,
+ .port_type = AIROHA_PCS_PCIE,
+ .alloc_regmap_fields = an7581_pcs_pcie_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_usb = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_USB,
+ .bringup = an7581_pcs_usb_bringup,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+ { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+ { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+ { .compatible = "airoha,an7581-pcs-pcie", .data = &an7581_pcs_pcie },
+ { .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+ .driver = {
+ .name = "airoha-pcs",
+ .of_match_table = airoha_pcs_of_table,
+ },
+ .probe = airoha_pcs_probe,
+ .remove = airoha_pcs_remove,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h
new file mode 100644
index 000000000000..8a76d51b5d2c
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha.h
@@ -0,0 +1,1311 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* SCU*/
+#define AIROHA_SCU_PDIDR 0x5c
+#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0)
+#define AIROHA_SCU_WAN_CONF 0x70
+#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
+#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3 0x94
+#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13)
+#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR 0x9c
+#define AIROHA_SCU_PCIE_XSI0_SEL GENMASK(14, 13)
+#define AIROHA_SCU_PCIE_XSI0_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI0_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x2)
+#define AIROHA_SCU_PCIE_XSI1_SEL GENMASK(12, 11)
+#define AIROHA_SCU_PCIE_XSI1_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI1_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x2)
+#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9)
+#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0
+#define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22)
+#define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17)
+#define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10)
+#define AIROHA_PCS_XFI_TX_FC_EN BIT(5)
+#define AIROHA_PCS_XFI_RX_FC_EN BIT(4)
+#define AIROHA_PCS_XFI_RXMPI_STOP BIT(3)
+#define AIROHA_PCS_XFI_RXMBI_STOP BIT(2)
+#define AIROHA_PCS_XFI_TXMPI_STOP BIT(1)
+#define AIROHA_PCS_XFI_TXMBI_STOP BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10
+#define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60
+#define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64
+#define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100
+#define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0
+#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY BIT(15)
+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */
+#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10
+#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */
+#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1)
+#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_TBI_10B_MODE BIT(30)
+#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24)
+#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8
+#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8)
+#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104
+#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5)
+#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c
+#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0)
+
+/* HSGMII_ANA */
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6 0x18
+#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC BIT(20)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8 0x20
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11 0x2c
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE GENMASK(1, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18 0x48
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV GENMASK(28, 27)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19 0x4c
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK(2, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x5)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x7)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24 0x60
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26 0x68
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14
+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4)
+#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2)
+#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1)
+#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c
+#define AIROHA_PCS_HSGMII_PCS_INT BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c
+#define AIROHA_PCS_LINK_STS_P0 BIT(3)
+#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0)
+#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448
+#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2)
+#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1)
+#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x4
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x1)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_DOWN \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x0)
+#define AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1 0x30
+#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12)
+#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0
+#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4
+#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8
+#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8)
+#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318
+#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
+#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
+#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
+#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
+#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0
+#define AIROHA_PCS_ANA_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17)
+#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8)
+#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38
+#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16)
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48
+#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO BIT(5)
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
+#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54
+#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
+#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68
+#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74
+#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c
+#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84
+#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94
+#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4
+#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
+#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
+#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
+#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4
+#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8
+#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
+#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
+#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
+#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2)
+#define AIROHA_PCS_ANA_CDR_PR_MONPI_EN BIT(1)
+#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
+#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
+#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8)
+#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c
+#define AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c
+#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148
+#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYA 2L */
+#define AIROHA_PCS_ANA_PXP_2L_CMN_EN 0x0
+#define AIROHA_PCS_ANA_2L_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_2L_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN 0x38
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1 0x3c
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD 0x40
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN 0x4c
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF 0x50
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN 0x54
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IBIAS GENMASK(29, 24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST 0x58
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BP GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IOFST GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR 0x5c
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_CODE GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_OPTION BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV 0x60
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KF GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KFC GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_DIV GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN 0x64
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_POSTDIV_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN 0x68
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_INTERNAL BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV 0x6c
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_PLL_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_RST_DLY GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS 0x70
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_IFM BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT 0x74
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_HREN BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_OUT BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF 0x78
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW 0x7c
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_HALFLSB_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_CFIX GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR 0x80
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_TCLVAR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_SCAPWR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN 0x84
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1 0x88
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD 0x8c
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF 0x9c
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN 0xcc
+#define AIROHA_PCS_ANA_2L_TX0_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX0_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN 0xe8
+#define AIROHA_PCS_ANA_2L_TX1_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX1_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL 0xf4
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX0_REV_0 0xfc
+#define AIROHA_PCS_ANA_2L_RX0_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV 0x100
+#define AIROHA_PCS_ANA_2L_RX0_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV 0x104
+#define AIROHA_PCS_ANA_2L_CDR0_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO 0x110
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE 0x11c
+#define AIROHA_PCS_ANA_2L_CDR0_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC 0x120
+#define AIROHA_PCS_ANA_2L_CDR0_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL 0x124
+#define AIROHA_PCS_ANA_2L_CDR0_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN 0x130
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN 0x134
+#define AIROHA_PCS_ANA_2L_CDR0_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR 0x138
+#define AIROHA_PCS_ANA_2L_CDR0_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON 0x13c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_MON GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN 0x140
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_PEAK GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_LPF_CTRL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL 0x144
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ1_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_FE_EQ_HZEN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_VTH_SEL GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN 0x148
+#define AIROHA_PCS_ANA_2L_RX0_FE_VCM_GEN_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ3_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ2_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE 0x150
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE 0x170
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ 0x17c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E1_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E0_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D1_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D0_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ 0x180
+#define AIROHA_PCS_ANA_2L_RX0_DAC_EYE_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB 0x234
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL 0x1ac
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX1_REV_0 0x1b4
+#define AIROHA_PCS_ANA_2L_RX1_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV 0x1b8
+#define AIROHA_PCS_ANA_2L_RX1_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV 0x1bc
+#define AIROHA_PCS_ANA_2L_CDR1_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO 0x1c8
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE 0x1d4
+#define AIROHA_PCS_ANA_2L_CDR1_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC 0x1d8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL 0x1dc
+#define AIROHA_PCS_ANA_2L_CDR1_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN 0x1e8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN 0x1ec
+#define AIROHA_PCS_ANA_2L_CDR1_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR 0x1f0
+#define AIROHA_PCS_ANA_2L_RX1_DAC_MON GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE 0x1f4
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH 0x1f8
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL 0x1fc
+#define AIROHA_PCS_ANA_2L_RX1_FE_EQ_HZEN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN 0x200
+#define AIROHA_PCS_ANA_2L_RX1_FE_VCM_GEN_PWDB BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ3_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ2_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ1_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW 0x208
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE GENMASK(25, 16)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE 0x228
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE GENMASK(27, 16)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ 0x238
+#define AIROHA_PCS_ANA_2L_RX1_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
+#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
+#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
+#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
+#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c
+#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90
+#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94
+#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98
+#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c
+#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100
+#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
+#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120
+#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8)
+#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
+#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150
+#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158
+#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12)
+#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c
+#define AIROHA_PCS_PMA_SIGDET_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1 0x174
+#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2 0x178
+#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16)
+#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5 0x184
+#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16)
+#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B 0x19c
+#define AIROHA_PCS_PMA_LOAD_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1 0x208
+#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B 0x260
+#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320
+#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330
+#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c
+#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
+#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24)
+#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
+#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8)
+#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350
+#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360
+#define AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN GENMASK(17, 16)
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374
+#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2 0x380
+#define AIROHA_PCS_RX_SIGDET BIT(8)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390
+#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
+#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414
+#define AIROHA_PCS_PMA_XFI_RX_MODE GENMASK(11, 9)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x5)
+#define AIROHA_PCS_PMA_R2T_MODE BIT(8)
+#define AIROHA_PCS_PMA_XFI_TX_MODE GENMASK(5, 3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x5)
+#define AIROHA_PCS_PMA_SW_RST_SET 0x460
+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
+#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8)
+#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7)
+#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6)
+#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5)
+#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4)
+#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3)
+#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
+#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
+#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474
+#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c
+#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
+#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET 0x530
+#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580
+#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_29 0x910
+#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL GENMASK(5, 4)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY 50
+#define AIROHA_PCS_MAX_RX_SIGDET_TRY 6
+#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT 4
+#define AIROHA_PCS_MAX_NUM_RSTS 2
+
+enum xfi_port_type {
+ AIROHA_PCS_ETH,
+ AIROHA_PCS_PON,
+ AIROHA_PCS_USB,
+ AIROHA_PCS_PCIE,
+};
+
+struct airoha_pcs_maps {
+ struct regmap *pcs_mac;
+ struct regmap *hsgmii_an;
+ struct regmap *hsgmii_pcs;
+ struct regmap *hsgmii_rate_adp;
+ struct regmap *multi_sgmii;
+ struct regmap *usxgmii_pcs;
+};
+
+struct airoha_pcs_priv {
+ struct device *dev;
+ const struct airoha_pcs_match_data *data;
+
+ struct airoha_pcs_port *ports;
+
+ struct regmap *scu;
+
+ struct airoha_pcs_maps maps[2];
+
+ struct regmap *pcs_pma[2];
+ struct regmap *pcs_ana;
+ struct regmap_field **pcs_ana_fields[2];
+
+ struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+ struct phy *phy;
+
+ bool manual_rx_calib;
+};
+
+struct airoha_pcs_port {
+ struct airoha_pcs_priv *priv;
+ phy_interface_t interface;
+ int index;
+
+ struct phylink_pcs pcs;
+};
+
+struct airoha_pcs_match_data {
+ int num_port;
+ enum xfi_port_type port_type;
+
+ int (*alloc_regmap_fields)(struct airoha_pcs_priv *priv);
+ int (*bringup)(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+ void (*link_up)(struct airoha_pcs_priv *priv, int index);
+ int (*rxlock_workaround)(struct airoha_pcs_priv *priv, int index);
+};
+
+#define to_airoha_pcs_port(n) container_of(n, struct airoha_pcs_port, pcs)
+
+#if IS_ENABLED(CONFIG_PCS_AIROHA_AN7581)
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index);
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index);
+#else
+static inline int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv,
+ int index)
+{
+}
+
+static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv,
+ int index)
+{
+ return 0;
+}
+#endif
diff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/pcs-an7581.c
new file mode 100644
index 000000000000..3517d7a78f32
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-an7581.c
@@ -0,0 +1,2093 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/math.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/regmap.h>
+
+#include "pcs-airoha.h"
+
+#include <linux/of.h>
+
+enum {
+ AN7581_PCS_CMN_EN,
+
+ AN7581_PCS_JCPLL_SPARE_L,
+ AN7581_PCS_JCPLL_RST_DLY,
+ AN7581_PCS_JCPLL_PLL_RSTB,
+ AN7581_PCS_JCPLL_SDM_DI_LS,
+ AN7581_PCS_JCPLL_SDM_DI_EN,
+
+ AN7581_PCS_JCPLL_SDM_OUT,
+ AN7581_PCS_JCPLL_SDM_ORD,
+ AN7581_PCS_JCPLL_SDM_MODE,
+ AN7581_PCS_JCPLL_SDM_IFM,
+ AN7581_PCS_JCPLL_SDM_HREN,
+
+ AN7581_PCS_JCPLL_CHP_IOFST,
+ AN7581_PCS_JCPLL_CHP_IBIAS,
+ AN7581_PCS_JCPLL_LPF_SHCK_EN,
+
+ AN7581_PCS_JCPLL_LPF_BWR,
+ AN7581_PCS_JCPLL_LPF_BP,
+ AN7581_PCS_JCPLL_LPF_BC,
+ AN7581_PCS_JCPLL_LPF_BR,
+ AN7581_PCS_JCPLL_LPF_BWC,
+
+ AN7581_PCS_JCPLL_VCO_SCAPWR,
+ AN7581_PCS_JCPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_JCPLL_VCO_CFIX,
+ AN7581_PCS_JCPLL_VCODIV,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_JCPLL_VCO_TCLVAR,
+
+ AN7581_PCS_JCPLL_POSTDIV_D5,
+ AN7581_PCS_JCPLL_MMD_PREDIV_MODE,
+
+ AN7581_PCS_JCPLL_KBAND_KS,
+ AN7581_PCS_JCPLL_KBAND_KF,
+ AN7581_PCS_JCPLL_KBAND_KFC,
+ AN7581_PCS_JCPLL_KBAND_DIV,
+ AN7581_PCS_JCPLL_KBAND_CODE,
+ AN7581_PCS_JCPLL_KBAND_OPTION,
+
+ AN7581_PCS_JCPLL_TCL_AMP_VREF,
+ AN7581_PCS_JCPLL_TCL_AMP_GAIN,
+ AN7581_PCS_JCPLL_TCL_AMP_EN,
+
+ AN7581_PCS_JCPLL_TCL_LPF_BW,
+ AN7581_PCS_JCPLL_TCL_LPF_EN,
+
+ AN7581_PCS_JCPLL_SSC_DELTA,
+ AN7581_PCS_JCPLL_SSC_DELTA1,
+ AN7581_PCS_JCPLL_SSC_PERIOD,
+ AN7581_PCS_JCPLL_SSC_TRI_EN,
+ AN7581_PCS_JCPLL_SSC_EN,
+ AN7581_PCS_JCPLL_SSC_PHASE_INI,
+ AN7581_PCS_JCPLL_TCL_KBAND_VREF,
+
+ AN7581_PCS_TXPLL_LDO_VCO_OUT,
+ AN7581_PCS_TXPLL_LDO_OUT,
+ AN7581_PCS_TXPLL_PLL_RSTB,
+ AN7581_PCS_TXPLL_RST_DLY,
+ AN7581_PCS_TXPLL_REFIN_DIV,
+ AN7581_PCS_TXPLL_REFIN_INTERNAL,
+ AN7581_PCS_TXPLL_SDM_MODE,
+ AN7581_PCS_TXPLL_SDM_IFM,
+ AN7581_PCS_TXPLL_SDM_DI_LS,
+ AN7581_PCS_TXPLL_SDM_DI_EN,
+ AN7581_PCS_TXPLL_SDM_HREN,
+ AN7581_PCS_TXPLL_SDM_ORD,
+ AN7581_PCS_TXPLL_SDM_OUT,
+ AN7581_PCS_TXPLL_SSC_DELTA1,
+ AN7581_PCS_TXPLL_SSC_DELTA,
+ AN7581_PCS_TXPLL_SSC_TRI_EN,
+ AN7581_PCS_TXPLL_SSC_PHASE_INI,
+ AN7581_PCS_TXPLL_SSC_EN,
+ AN7581_PCS_TXPLL_SSC_PERIOD,
+ AN7581_PCS_TXPLL_LPF_BC,
+ AN7581_PCS_TXPLL_LPF_BR,
+ AN7581_PCS_TXPLL_LPF_BP,
+ AN7581_PCS_TXPLL_LPF_BWC,
+ AN7581_PCS_TXPLL_LPF_BWR,
+ AN7581_PCS_TXPLL_CHP_IOFST,
+ AN7581_PCS_TXPLL_CHP_IBIAS,
+ AN7581_PCS_TXPLL_VCO_CFIX,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_TXPLL_VCO_TCLVAR,
+ AN7581_PCS_TXPLL_VCO_SCAPWR,
+ AN7581_PCS_TXPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_TXPLL_KBAND_CODE,
+ AN7581_PCS_TXPLL_KBAND_OPTION,
+ AN7581_PCS_TXPLL_KBAND_KS,
+ AN7581_PCS_TXPLL_KBAND_KF,
+ AN7581_PCS_TXPLL_KBAND_KFC,
+ AN7581_PCS_TXPLL_KBAND_DIV,
+ AN7581_PCS_TXPLL_MMD_PREDIV_MODE,
+ AN7581_PCS_TXPLL_POSTDIV_EN,
+ AN7581_PCS_TXPLL_VCODIV,
+ AN7581_PCS_TXPLL_TCL_KBAND_VREF,
+ AN7581_PCS_TXPLL_TCL_AMP_GAIN,
+ AN7581_PCS_TXPLL_TCL_AMP_VREF,
+ AN7581_PCS_TXPLL_TCL_LPF_BW,
+ AN7581_PCS_TXPLL_TCL_LPF_EN,
+ AN7581_PCS_TXPLL_TCL_AMP_EN,
+
+ AN7581_PCS_TX_DMEDGEGEN_EN,
+ AN7581_PCS_TX_CKLDO_EN,
+
+ AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E0_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D0_BYPASS_AEQ,
+ AN7581_PCS_RX_FE_VCM_GEN_PWDB,
+ AN7581_PCS_RX_OSCAL_FORCE,
+ AN7581_PCS_RX_DAC_MON,
+ AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_SIGDET_ILEAK,
+ AN7581_PCS_RX_FE_VB_EQ3_EN,
+ AN7581_PCS_RX_FE_VB_EQ2_EN,
+ AN7581_PCS_RX_FE_VB_EQ1_EN,
+ AN7581_PCS_RX_FE_EQ_HZEN,
+ AN7581_PCS_RX_SIGDET_VTH_SEL,
+ AN7581_PCS_RX_SIGDET_PEAK,
+ AN7581_PCS_RX_SIGDET_LPF_CTRL,
+ AN7581_PCS_RX_TDC_CK_SEL,
+ AN7581_PCS_RX_PHYCK_RSTB,
+ AN7581_PCS_RX_PHYCK_SEL,
+ AN7581_PCS_RX_PHYCK_DIV,
+ AN7581_PCS_RX_PHY_CK_SEL_FORCE,
+ AN7581_PCS_RX_PHY_CK_SEL,
+
+ AN7581_PCS_AEQ_OFORCE,
+
+ AN7581_PCS_CDR_PD_EDGE_DIS,
+ AN7581_PCS_CDR_PD_PICAL_CKD8_INV,
+
+ AN7581_PCS_CDR_PR_XFICK_EN,
+ AN7581_PCS_CDR_PR_MONPI_EN,
+ AN7581_PCS_CDR_PR_MONPR_EN,
+ AN7581_PCS_CDR_PR_KBAND_DIV,
+ AN7581_PCS_CDR_PR_BETA_SEL,
+ AN7581_PCS_CDR_PR_VCOADC_OS,
+ AN7581_PCS_CDR_PR_BETA_DAC,
+ AN7581_PCS_CDR_PR_FBKSEL,
+ AN7581_PCS_CDR_PR_DAC_BAND,
+ AN7581_PCS_CDR_PR_VREG_CKBUF_VAL,
+ AN7581_PCS_CDR_PR_VREG_IBAND_VAL,
+ AN7581_PCS_CDR_PR_CAP_EN,
+ AN7581_PCS_CDR_PR_INJ_FORCE_OFF,
+
+ AN7581_PCS_CDR_BUF_IN_SR,
+
+ AN7581_PCS_CDR_LPF_TOP_LIM,
+ AN7581_PCS_CDR_LPF_RATIO,
+
+ AN7581_PCS_FIELDS_MAX,
+};
+
+static const struct reg_field an7581_pcs_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 8, 15),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 8, 23),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 0, 0),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 17, 17),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 16, 16),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 16, 20),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 3, 5),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 24, 24),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 16, 18),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 8, 9),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 24, 25),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 8, 9),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 0, 1),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 24, 28),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 16, 20),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 8, 13),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 0, 5),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 0, 4),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 24, 25),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 27, 29),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 0, 0),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 0, 7),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 0, 1),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 8, 10),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 16, 17),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 8, 8),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 16, 17),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 8, 12),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 8, 10),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, 0, 0),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_AEQ_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 24, 28),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 2, 2),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 1, 1),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 0, 0),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 24, 24),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 8, 8),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 0, 0),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 19, 19),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 16, 18),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie0_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 16, 16),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON, 0, 4),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 0, 0),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 24, 24),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 0, 4),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 24, 25),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 8, 9),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie1_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 24, 24),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE, 16, 27),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW, 16, 25),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 16, 20),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 0, 0),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL, 24, 24),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE, 24, 24),
+};
+
+static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma;
+ u32 kband_vref;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ kband_vref = 0x10;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ kband_vref = 0xf;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for JCPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup LDO */
+ usleep_range(200, 300);
+
+ regmap_field_set_bits(pcs_ana_fields[AN7581_PCS_JCPLL_SPARE_L],
+ AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_RST_DLY],
+ AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_PLL_RSTB], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_EN], 0x0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_ORD],
+ AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_HREN], 0x0);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA1], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PERIOD], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_TRI_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PHASE_INI], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IBIAS], 0x18);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_SHCK_EN], 0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BP], 0x10);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BR], BIT(3) | BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWC], 0x0);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_SCAPWR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_HALFLSB_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_CFIX], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x3);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_POSTDIV_D5], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCODIV],
+ AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_DIV], 0x2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_OPTION], 0x0);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_KBAND_VREF],
+ kband_vref);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_VREF], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_EN], 0x1);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+ struct regmap *pcs_pma;
+ u32 tcl_amp_vref;
+ bool sdm_hren;
+ u32 vco_cfix;
+ bool vcodiv;
+ u32 pcw;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(1) | BIT(0);
+ pcw = BIT(27);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ lpf_chp_ibias = 0xa;
+ lpf_bp = BIT(2) | BIT(0);
+ lpf_bwr = 0;
+ lpf_bwc = 0;
+ vco_cfix = 0;
+ pcw = BIT(27) | BIT(25);
+ tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+ vcodiv = true;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(0);
+ pcw = BIT(27) | BIT(22);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = true;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for TXPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup VCO LDO Output */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_VCO_OUT], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_OUT], 0x1);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_PLL_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_RST_DLY], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_DIV],
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_INTERNAL], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_HREN], sdm_hren);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_ORD],
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA1], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_TRI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PHASE_INI], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PERIOD], 0x0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IBIAS],
+ lpf_chp_ibias);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BR], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWC], lpf_bwc);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWR], lpf_bwr);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BP], lpf_bp);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_CFIX], vco_cfix);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_TCLVAR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_SCAPWR], 0x7);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_HALFLSB_EN], 0x1);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_OPTION], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KS], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_DIV], 0x4);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_POSTDIV_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCODIV],
+ vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+ AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_KBAND_VREF], 0xf);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_VREF],
+ tcl_amp_vref);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 fir_cn1, fir_c0b, fir_c1;
+ u32 tx_rate_ctrl;
+ u32 ckin_divisor;
+ u32 xfi_tx_mode;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ ckin_divisor = BIT(1);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 12;
+ fir_c1 = 0;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ ckin_divisor = BIT(2);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 11;
+ fir_c1 = 1;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ ckin_divisor = BIT(2) | BIT(0);
+ tx_rate_ctrl = BIT(1);
+ fir_cn1 = 1;
+ fir_c0b = 1;
+ fir_c1 = 11;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set TX rate ctrl */
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_TX_MODE,
+ xfi_tx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX Config */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_DMEDGEGEN_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_CKLDO_EN], 0x1);
+
+ udelay(1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+ /* FIXME: Ask Airoha TX term is OK to reset? */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+ ckin_divisor));
+
+ if (priv->data->port_type != AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX FIR Load Parameters (Reference 660mV) */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+ /* Reset TX Bar */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,
+ AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 phyck_div, phyck_sel;
+ u32 pr_cdr_beta_dac;
+ u32 cdr_pr_buf_in_sr;
+ bool cdr_pr_cap_en;
+ u32 sigdet_vth_sel;
+ u32 rx_rate_ctrl;
+ u32 xfi_rx_mode;
+ u32 osr;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ osr = BIT(1) | BIT(0); /* 1.25G */
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = false;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(5) | BIT(3) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ osr = BIT(0); /* 2.5G */
+ pr_cdr_beta_dac = BIT(2) | BIT(1);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = true;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(3) | BIT(1) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ osr = 0; /* 10G */
+ cdr_pr_cap_en = false;
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = BIT(1);
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(1);
+ phyck_div = BIT(6) | BIT(1);
+ phyck_sel = BIT(1);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set RX rate ctrl */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2,
+ AIROHA_PCS_PMA_CK_RATE,
+ AIROHA_PCS_PMA_CK_RATE_10);
+
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ rx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_RX_MODE,
+ xfi_rx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+ AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ rx_rate_ctrl));
+ }
+
+ /* Setup RX Path */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5,
+ AIROHA_PCS_PMA_FLL_IDAC_MIN |
+ AIROHA_PCS_PMA_FLL_IDAC_MAX,
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VCM_GEN_PWDB], 0x1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+ AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_AEQ_OFORCE],
+ AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_OSCAL_FORCE],
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+ AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+ AIROHA_PCS_PMA_DISB_LEQ);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_PICAL_CKD8_INV], 0x0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+ AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_MON], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_XFICK_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPR_EN], 0x0);
+
+ /* Setup FE Gain and FE Peacking */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));
+
+ /* Setup FE VOS */
+ if (interface != PHY_INTERFACE_MODE_USXGMII &&
+ interface != PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+ /* Setup FLL PR FMeter (no bypass mode)*/
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+ AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+ AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+ /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+ /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+ /* Setup REV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_SIGDET_ILEAK], 0x0);
+
+ /* Setup Rdy Timeout */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+ AIROHA_PCS_PMA_RX_RDY |
+ AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+ /* Setup CaBoundry Init */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+ AIROHA_PCS_PMA_RX_OS_START |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+ AIROHA_PCS_PMA_RX_OS_END,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+ AIROHA_PCS_PMA_RX_PICAL_END |
+ AIROHA_PCS_PMA_RX_PICAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+ AIROHA_PCS_PMA_RX_SDCAL_END |
+ AIROHA_PCS_PMA_RX_SDCAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+ AIROHA_PCS_PMA_RX_PDOS_END |
+ AIROHA_PCS_PMA_RX_PDOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+ AIROHA_PCS_PMA_RX_FEOS_END |
+ AIROHA_PCS_PMA_RX_FEOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+ /* Setup By Serdes*/
+ /* Setup RX OSR */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], !!osr);
+
+ /* Setup CDR LPF Ratio */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_TOP_LIM], 0x20000);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_RATIO], osr);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_KBAND_DIV], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_SEL], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VCOADC_OS], 0x8);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_DAC],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_FBKSEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_DAC_BAND],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL], 0x6);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_IBAND_VAL], 0x6);
+
+ /* Setup Eye Mon */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,
+ AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+ AIROHA_PCS_PMA_FOM_NUM_ORDER |
+ AIROHA_PCS_PMA_A_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+ FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_DATA_SHIFT |
+ AIROHA_PCS_PMA_EYECNT_FAST,
+ AIROHA_PCS_PMA_EYECNT_FAST);
+
+ /* Calibration Start */
+
+ /* Enable SYS */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+ AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+ AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+ usleep_range(500, 600);
+
+ /* Setup FLL PR FMeter (bypass mode)*/
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+ /* Enable CMLEQ */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_EQ_HZEN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ3_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ2_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ1_EN], 0x1);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_CAP_EN],
+ cdr_pr_cap_en);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_BUF_IN_SR],
+ cdr_pr_buf_in_sr);
+
+ /* Setup CDR xxx Pwdb, set force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* FIXME: Ask Airoha WHY it's cleared? */
+ /* regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+ */
+
+ /* Setup SigDet */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_VTH_SEL],
+ sigdet_vth_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_PEAK],
+ BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_LPF_CTRL],
+ BIT(1) | BIT(0));
+
+ /* Disable SigDet Pwdb */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+ /* Setup PHYCK */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_TDC_CK_SEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_SEL],
+ phyck_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_DIV],
+ phyck_div);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL_FORCE], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL], 0x0);
+
+ usleep_range(100, 200);
+
+ /* Enable CDR xxx Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* Enable SigDet Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+ int index, u32 cdr_pr_idac)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 val;
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ cdr_pr_idac));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+ usleep_range(5000, 7000);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+ return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv,
+ int index, u32 target_fl_out)
+{
+ unsigned int fl_out_diff = UINT_MAX;
+ unsigned int prcal_search;
+ u32 cdr_pr_idac = 0;
+
+ for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+ unsigned int fl_out_diff_new;
+ unsigned int fl_out;
+ u32 cdr_pr_idac_tmp;
+
+ /* try to find the upper value by setting the last 3 bit */
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ prcal_search);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, int index,
+ u32 target_fl_out, u32 cdr_pr_idac_major)
+{
+ unsigned int remaining_prcal_search_bits = 0;
+ u32 cdr_pr_idac = cdr_pr_idac_major;
+ unsigned int fl_out, fl_out_diff;
+ int best_prcal_search_bit = -1;
+ int prcal_search_bit;
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+
+ /* Deadline search part.
+ * We start from top bits to bottom as we progressively decrease the
+ * signal.
+ */
+ for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ best_prcal_search_bit = prcal_search_bit;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ /* Set the idac with the best value we found and
+ * reset the search bit to start from bottom to top.
+ */
+ if (best_prcal_search_bit >= 0) {
+ cdr_pr_idac |= BIT(best_prcal_search_bit);
+ remaining_prcal_search_bits = best_prcal_search_bit;
+ prcal_search_bit = 0;
+ }
+
+ /* Fine tune part.
+ * Test remaining bits to find an even closer signal level to target
+ * by increasing the signal.
+ */
+ while (remaining_prcal_search_bits) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ /* Assume we found the deadline when the new absolue signal difference
+ * from target is greater than the previous and the difference is at
+ * least 10% greater between the old and new value.
+ * This is to account for signal detection level tollerance making
+ * sure we are actually over a deadline (AKA we are getting farther
+ * from target)
+ */
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff && fl_out_diff_new > fl_out_diff &&
+ (abs_diff(fl_out_diff_new, fl_out_diff) * 100) / fl_out_diff > 10) {
+ /* Exit early if we are already at the deadline */
+ if (prcal_search_bit == 0)
+ break;
+
+ /* We found the deadline, set the value to the previous
+ * bit, and reset the loop to fine tune with the
+ * remaining values.
+ */
+ cdr_pr_idac |= BIT(prcal_search_bit - 1);
+ remaining_prcal_search_bits = prcal_search_bit - 1;
+ prcal_search_bit = 0;
+ } else {
+ /* Update the signal level diff and try the next bit */
+ fl_out_diff = fl_out_diff_new;
+
+ /* If we didn't found the deadline, set the last bit
+ * and reset the loop to fine tune with the remainig
+ * values.
+ */
+ if (prcal_search_bit == remaining_prcal_search_bits - 1) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ remaining_prcal_search_bits = prcal_search_bit;
+ prcal_search_bit = 0;
+ } else {
+ prcal_search_bit++;
+ }
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 cdr_pr_idac_major, cdr_pr_idac;
+ unsigned int fl_out, fl_out_diff;
+
+ u32 target_fl_out;
+ u32 cyclecnt;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */
+ case PHY_INTERFACE_MODE_1000BASEX:
+ target_fl_out = 0xa3d6;
+ cyclecnt = 32767;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */
+ target_fl_out = 0xa000;
+ cyclecnt = 20000;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */
+ case PHY_INTERFACE_MODE_10GBASER:
+ target_fl_out = 0x9edf;
+ cyclecnt = 32767;
+ break;
+ default:
+ return;
+ }
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+ AIROHA_PCS_PMA_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+ AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+ AIROHA_PCS_PMA_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+ AIROHA_PCS_PMA_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+ AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+ AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ /* Calibration logic:
+ * First check the major value by looping with every
+ * value in the last 3 bit of CDR_PR_IDAC.
+ * Get the signal level and save the value that is closer to
+ * the target.
+ *
+ * Then check each remaining 7 bits in search of the deadline
+ * where the signal gets farther than signal target.
+ *
+ * Finally fine tune for the remaining bits to find the one that
+ * produce the closest signal level.
+ */
+ cdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, index, target_fl_out);
+
+ cdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out, cdr_pr_idac_major);
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+ if (fl_out_diff > 100) {
+ u32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ cdr_pr_idac_major);
+ unsigned int fl_out_tmp, fl_out_diff_tmp;
+ u32 cdr_pr_idac_tmp;
+
+ if (pr_idac_major > 0) {
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ pr_idac_major - 1);
+
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\n",
+ fl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp);
+
+ cdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out,
+ cdr_pr_idac_tmp);
+
+ fl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, index,
+ cdr_pr_idac_tmp);
+ fl_out_diff_tmp = abs_diff(fl_out_tmp, target_fl_out);
+ if (fl_out_diff_tmp < fl_out_diff) {
+ fl_out = fl_out_tmp;
+ fl_out_diff = fl_out_diff_tmp;
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ }
+ }
+ }
+ dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+ if (fl_out_diff > 100)
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n",
+ fl_out_diff, target_fl_out);
+
+ /* Setup Load Band */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x0);
+
+ /* Disable force of LPF C previously enabled */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_B,
+ AIROHA_PCS_PMA_LOAD_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1,
+ AIROHA_PCS_PMA_LPATH_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface, bool calibrate)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Setup LPF L2D force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ /* Calibrate IDAC and setup Load Band */
+ if (calibrate)
+ an7581_pcs_rx_prcal(priv, index, interface);
+
+ /* Setup LPF RSTB force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ usleep_range(700, 1000);
+
+ /* Force Enable LPF RSTB */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ usleep_range(100, 200);
+
+ /* Force Enable LPF L2D */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ /* Disable LPF RSTB force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ /* Disable LPF L2D force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ int calibration_try = 0;
+ u32 val;
+
+ an7581_pcs_tx_bringup(priv, index, interface);
+ an7581_pcs_rx_bringup(priv, index, interface);
+
+ usleep_range(100, 200);
+
+retry_calibration:
+ an7581_pcs_cdr_reset(priv, index, interface, priv->manual_rx_calib);
+
+ /* Global reset clear */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ /* Global reset */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+ usleep_range(5000, 7000);
+
+ an7581_pcs_cdr_reset(priv, index, interface, false);
+
+ /* Manual RX calibration is required only for SoC before E2
+ * revision. E2+ SoC autocalibrate RX and only CDR reset is needed.
+ */
+ if (!priv->manual_rx_calib)
+ return 0;
+
+ /* It was discovered that after a global reset and auto mode gets
+ * actually enabled, the fl_out from calibration might change and
+ * might deviates a lot from the expected value it was calibrated for.
+ * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+ * (frequency level output) or no signal can correctly be transmitted.
+ * This is detected by checking the FreqDet module Lock bit.
+ *
+ * If it's detected that the FreqDet module is not locked, retry
+ * calibration. From observation on real hardware with a 10g SFP module,
+ * it required a maximum of an additional calibration to actually make
+ * the FreqDet module to lock. Try 10 times before failing to handle
+ * really strange case.
+ */
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+ if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+ if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+ dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+ AIROHA_PCS_MAX_CALIBRATION_TRY);
+ return -EIO;
+ }
+
+ calibration_try++;
+
+ dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+ goto retry_calibration;
+ }
+
+ return 0;
+}
+
+static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ an7581_pcs_jcpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+
+ an7581_pcs_txpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+}
+
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+
+ /* Enable Analog Common Lane */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CMN_EN], 0x1);
+
+ /* Setup PLL */
+ an7581_pcs_pll_bringup(priv, index, interface);
+
+ msleep(100);
+
+ /* Setup PHYA */
+ return an7581_pcs_phya_bringup(priv, index, interface);
+}
+
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ int ret;
+
+ ret = phy_set_mode_ext(priv->phy, PHY_MODE_ETHERNET, interface);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3));
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ } else {
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ }
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32);
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK)));
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII);
+ else
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII);
+
+ return 0;
+}
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Reset TXPCS on link up */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+}
+
+static int __an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv, int index,
+ const struct reg_field *fields)
+{
+ struct device *dev = priv->dev;
+ int i;
+
+ priv->pcs_ana_fields[index] = devm_kcalloc(dev, AN7581_PCS_FIELDS_MAX,
+ sizeof(*priv->pcs_ana_fields[index]),
+ GFP_KERNEL);
+ if (!priv->pcs_ana_fields[index])
+ return -ENOMEM;
+
+ for (i = 0; i < AN7581_PCS_FIELDS_MAX; i++) {
+ struct regmap_field *field;
+
+ field = devm_regmap_field_alloc(dev, priv->pcs_ana,
+ fields[i]);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ priv->pcs_ana_fields[index][i] = field;
+ }
+
+ return 0;
+}
+
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_fields);
+}
+
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ int ret;
+
+ ret = __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_pcie0_fields);
+ if (ret)
+ return ret;
+
+ return __an7581_pcs_alloc_regmap_fields(priv, 1, an7581_pcs_pcie1_fields);
+}
+
+static bool an7581_pcs_have_rx_signal(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ unsigned int count = 0;
+ u32 val;
+ int i;
+
+ regmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0,
+ AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN);
+
+ /* Scan 6 times for RX sigdet module to detect RX signal */
+ for (i = 0; i < AIROHA_PCS_MAX_RX_SIGDET_TRY; i++) {
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_DIG_RO_RESERVE_2,
+ &val);
+ if (val & AIROHA_PCS_RX_SIGDET)
+ count++;
+ }
+
+ /* Consider signal presence if we detect signal at least 4 times */
+ return count >= AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT;
+}
+
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 val;
+
+ /* Check if PCS is UP or Down */
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_STUS_1, &val);
+ if (val & AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP)
+ return 0;
+
+ /* Validate if this is consistent with RX SigDet module */
+ if (!an7581_pcs_have_rx_signal(priv, index))
+ return 0;
+
+ /* If PCS is down but RX SigDet module detected signal,
+ * trigger CDR reset.
+ */
+ an7581_pcs_cdr_reset(priv, index, PHY_INTERFACE_MODE_NA, false);
+
+ /* Report there is an error with Link Detection and we
+ * should test again later.
+ */
+ return -EINVAL;
+}
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 12/12] net: airoha: add phylink support
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Add phylink support for each GDM port. For GDM1 add the internal interface
mode as the only supported mode. For GDM2/3/4 add the required
configuration of the PCS to make the external PHY or attached SFP cage
work.
These needs to be defined in the GDM port node using the pcs-handle
property.
Update and provide a .get/set_link_ksettings function that use phylink
for ethtool OPs now that we fully support phylink.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/ethernet/airoha/Kconfig | 1 +
drivers/net/ethernet/airoha/airoha_eth.c | 193 +++++++++++++++++++++-
drivers/net/ethernet/airoha/airoha_eth.h | 7 +-
drivers/net/ethernet/airoha/airoha_regs.h | 12 ++
4 files changed, 206 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig
index ad3ce501e7a5..38dcc76e5998 100644
--- a/drivers/net/ethernet/airoha/Kconfig
+++ b/drivers/net/ethernet/airoha/Kconfig
@@ -20,6 +20,7 @@ config NET_AIROHA
depends on NET_DSA || !NET_DSA
select NET_AIROHA_NPU
select PAGE_POOL
+ select PHYLINK
help
This driver supports the gigabit ethernet MACs in the
Airoha SoC family.
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 5f1a118875fb..195e4ead6db3 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -8,6 +8,7 @@
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/tcp.h>
+#include <linux/pcs/pcs.h>
#include <linux/u64_stats_sync.h>
#include <net/dst_metadata.h>
#include <net/page_pool/helpers.h>
@@ -1788,7 +1789,7 @@ static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
struct airoha_gdm_port *port = dev->port;
int i;
- spin_lock(&port->stats_lock);
+ spin_lock(&port->lock);
for (i = 0; i < ARRAY_SIZE(port->devs); i++) {
if (port->devs[i])
@@ -1799,7 +1800,7 @@ static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
airoha_fe_set(dev->eth, REG_FE_GDM_MIB_CLEAR(port->id),
FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK);
- spin_unlock(&port->stats_lock);
+ spin_unlock(&port->lock);
}
static int airoha_dev_open(struct net_device *netdev)
@@ -1810,6 +1811,14 @@ static int airoha_dev_open(struct net_device *netdev)
u32 cur_len, pse_port = FE_PSE_PORT_PPE1;
struct airoha_qdma *qdma = dev->qdma;
+ err = phylink_of_phy_connect(dev->phylink, netdev->dev.of_node, 0);
+ if (err) {
+ netdev_err(netdev, "could not attach PHY: %d\n", err);
+ return err;
+ }
+
+ phylink_start(dev->phylink);
+
netif_tx_start_all_queues(netdev);
err = airoha_set_vip_for_gdm_port(dev, true);
if (err)
@@ -1907,6 +1916,9 @@ static int airoha_dev_stop(struct net_device *netdev)
}
}
+ phylink_stop(dev->phylink);
+ phylink_disconnect_phy(dev->phylink);
+
return 0;
}
@@ -2388,6 +2400,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,
} while (u64_stats_fetch_retry(&dev->stats.syncp, start));
}
+static int
+airoha_ethtool_get_link_ksettings(struct net_device *netdev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_get(dev->phylink, cmd);
+}
+
+static int
+airoha_ethtool_set_link_ksettings(struct net_device *netdev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_set(dev->phylink, cmd);
+}
+
static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,
int channel, enum tx_sched_mode mode,
const u16 *weights, u8 n_weights)
@@ -3112,7 +3142,8 @@ static const struct ethtool_ops airoha_ethtool_ops = {
.get_drvinfo = airoha_ethtool_get_drvinfo,
.get_eth_mac_stats = airoha_ethtool_get_mac_stats,
.get_rmon_stats = airoha_ethtool_get_rmon_stats,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .get_link_ksettings = airoha_ethtool_get_link_ksettings,
+ .set_link_ksettings = airoha_ethtool_set_link_ksettings,
.get_link = ethtool_op_get_link,
};
@@ -3168,6 +3199,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
return false;
}
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+}
+
+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+ struct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,
+ phylink_config);
+ struct airoha_gdm_port *port = dev->port;
+ struct airoha_eth *eth = dev->eth;
+ u32 frag_size_tx, frag_size_rx;
+ u32 mask, val;
+
+ /* TX/RX frag is configured only for GDM4 */
+ if (port->id != AIROHA_GDM4_IDX)
+ return;
+
+ switch (speed) {
+ case SPEED_10000:
+ case SPEED_5000:
+ frag_size_tx = 8;
+ frag_size_rx = 8;
+ break;
+ case SPEED_2500:
+ frag_size_tx = 2;
+ frag_size_rx = 1;
+ break;
+ default:
+ frag_size_tx = 1;
+ frag_size_rx = 0;
+ }
+
+ spin_lock(&port->lock);
+
+ /* Configure TX/RX frag based on speed */
+ if (dev->nbq == 1) {
+ mask = GDM4_SGMII1_TX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK,
+ frag_size_tx);
+ } else {
+ mask = GDM4_SGMII0_TX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK,
+ frag_size_tx);
+ }
+ airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, mask, val);
+
+ if (dev->nbq == 1) {
+ mask = GDM4_SGMII1_RX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK,
+ frag_size_rx);
+ } else {
+ mask = GDM4_SGMII0_RX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK,
+ frag_size_rx);
+ }
+ airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, mask, val);
+
+ spin_unlock(&port->lock);
+}
+
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+}
+
+static const struct phylink_mac_ops airoha_phylink_ops = {
+ .mac_config = airoha_mac_config,
+ .mac_link_up = airoha_mac_link_up,
+ .mac_link_down = airoha_mac_link_down,
+};
+
+static int airoha_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+{
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+}
+
+static int airoha_setup_phylink(struct net_device *netdev)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+ struct device_node *np = netdev->dev.of_node;
+ struct airoha_gdm_port *port = dev->port;
+ struct phylink_config *config;
+ phy_interface_t phy_mode;
+ struct phylink *phylink;
+ int err;
+
+ err = of_get_phy_mode(np, &phy_mode);
+ if (err) {
+ dev_err(&netdev->dev, "incorrect phy-mode\n");
+ return err;
+ }
+
+ config = &dev->phylink_config;
+ config->dev = &netdev->dev;
+ config->type = PHYLINK_NETDEV;
+
+ /*
+ * GDM1 only supports internal for Embedded Switch
+ * and doesn't require a PCS.
+ */
+ if (port->id == AIROHA_GDM1_IDX) {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10000FD;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ } else {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000 |
+ MAC_2500FD | MAC_5000FD | MAC_10000FD;
+
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config->dev));
+ config->fill_available_pcs = airoha_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ config->supported_interfaces);
+
+ phy_interface_copy(config->pcs_interfaces,
+ config->supported_interfaces);
+ }
+
+ phylink = phylink_create(config, of_fwnode_handle(np),
+ phy_mode, &airoha_phylink_ops);
+ if (IS_ERR(phylink))
+ return PTR_ERR(phylink);
+
+ dev->phylink = phylink;
+
+ return 0;
+}
+
static int airoha_alloc_gdm_device(struct airoha_eth *eth,
struct airoha_gdm_port *port,
int nbq, struct device_node *np)
@@ -3231,7 +3411,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
dev->nbq = nbq;
port->devs[index] = dev;
- return 0;
+ return airoha_setup_phylink(netdev);
}
static int airoha_alloc_gdm_port(struct airoha_eth *eth,
@@ -3266,7 +3446,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
return -ENOMEM;
port->id = id;
- spin_lock_init(&port->stats_lock);
+ spin_lock_init(&port->lock);
eth->ports[p] = port;
err = airoha_metadata_dst_alloc(port);
@@ -3457,6 +3637,8 @@ static int airoha_probe(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
if (netdev->reg_state == NETREG_REGISTERED)
unregister_netdev(netdev);
+ if (dev->phylink)
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
@@ -3493,6 +3675,7 @@ static void airoha_remove(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
unregister_netdev(netdev);
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 46b1c31939de..a6fef1777c7b 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -554,6 +554,9 @@ struct airoha_gdm_dev {
int nbq;
struct airoha_hw_stats stats;
+
+ struct phylink *phylink;
+ struct phylink_config phylink_config;
};
struct airoha_gdm_port {
@@ -561,8 +564,8 @@ struct airoha_gdm_port {
int id;
int users;
- /* protect concurrent hw_stats accesses */
- spinlock_t stats_lock;
+ /* protect concurrent hw_stats and frag register accesses */
+ spinlock_t lock;
struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
};
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index 436f3c8779c1..6ad91ca6dcd3 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -358,6 +358,18 @@
#define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)
#define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)
+#define REG_FE_GDM4_TMBI_FRAG 0x2028
+#define GDM4_SGMII1_TX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_TX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_TX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_TX_FRAG_SIZE_MASK GENMASK(9, 0)
+
+#define REG_FE_GDM4_RMBI_FRAG 0x202c
+#define GDM4_SGMII1_RX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_RX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_RX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_RX_FRAG_SIZE_MASK GENMASK(9, 0)
+
#define REG_MC_VLAN_EN 0x2100
#define MC_VLAN_EN_MASK BIT(0)
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 10/12] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Document support for Airoha Ethernet PCS for AN7581 SoC.
Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
the various Serdes port supporting different Media Independent Interface
(10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
This follow the new PCS provider with the use of #pcs-cells property.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../bindings/net/pcs/airoha,pcs.yaml | 261 ++++++++++++++++++
1 file changed, 261 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 000000000000..9c1d116c1b01
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,261 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+ the various Serdes port supporting different Media Independent Interface
+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+ compatible:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+ - airoha,an7581-pcs-pcie
+ - airoha,an7581-pcs-usb
+
+ reg:
+ minItems: 6
+ maxItems: 15
+
+ reg-names:
+ minItems: 6
+ maxItems: 15
+
+ airoha,scu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the SCU node required to configure
+ the serdes line to the correct interface mode.
+
+ phys:
+ maxItems: 1
+
+ "#pcs-cells": true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#pcs-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: USXGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: usxgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+ - const: pcs_pma
+
+ phys: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-pcie
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC 0 reg
+ - description: HSGMII AN 0 reg
+ - description: HSGMII PCS 0 reg
+ - description: MULTI SGMII 0 reg
+ - description: USXGMII 0 reg
+ - description: HSGMII rate adaption 0 reg
+ - description: PCS MAC 1 reg
+ - description: HSGMII AN 1 reg
+ - description: HSGMII PCS 1 reg
+ - description: MULTI SGMII 1 reg
+ - description: USXGMII 1 reg
+ - description: HSGMII rate adaption 1 reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) 0 register
+ - description: PCS PMA (Physical Medium Attachment) 1 register
+
+ reg-names:
+ items:
+ - const: pcs_mac0
+ - const: hsgmii_an0
+ - const: hsgmii_pcs0
+ - const: multi_sgmii0
+ - const: usxgmii0
+ - const: hsgmii_rate_adp0
+ - const: pcs_mac1
+ - const: hsgmii_an1
+ - const: hsgmii_pcs1
+ - const: multi_sgmii1
+ - const: usxgmii1
+ - const: hsgmii_rate_adp1
+ - const: pcs_ana
+ - const: pcs_pma0
+ - const: pcs_pma1
+
+ phys: false
+
+ "#pcs-cells":
+ const: 1
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-usb
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+
+ airoha,scu: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - phys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ pcs@1fa08000 {
+ compatible = "airoha,an7581-pcs-pon";
+ reg = <0x1fa08000 0x1000>,
+ <0x1fa80000 0x60>,
+ <0x1fa80a00 0x164>,
+ <0x1fa84000 0x450>,
+ <0x1fa85900 0x338>,
+ <0x1fa86000 0x300>,
+ <0x1fa8a000 0x1000>,
+ <0x1fa8b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa09000 {
+ compatible = "airoha,an7581-pcs-eth";
+ reg = <0x1fa09000 0x1000>,
+ <0x1fa70000 0x60>,
+ <0x1fa70a00 0x164>,
+ <0x1fa74000 0x450>,
+ <0x1fa75900 0x338>,
+ <0x1fa76000 0x300>,
+ <0x1fa7a000 0x1000>,
+ <0x1fa7b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa04000 {
+ compatible = "airoha,an7581-pcs-pcie";
+ reg = <0x1fa04000 0x1000>,
+ <0x1fa50000 0x60>,
+ <0x1fa50a00 0x164>,
+ <0x1fa54000 0x450>,
+ <0x1fa55900 0x338>,
+ <0x1fa56000 0x300>,
+ <0x1fa05000 0x1000>,
+ <0x1fa60000 0x60>,
+ <0x1fa60a00 0x164>,
+ <0x1fa64000 0x450>,
+ <0x1fa65900 0x338>,
+ <0x1fa66000 0x300>,
+ <0x1fa5a000 0x1000>,
+ <0x1fa5b000 0x1000>,
+ <0x1fa5c000 0x1000>;
+ reg-names = "pcs_mac0", "hsgmii_an0", "hsgmii_pcs0",
+ "multi_sgmii0", "usxgmii0",
+ "hsgmii_rate_adp0",
+ "pcs_mac1", "hsgmii_an1", "hsgmii_pcs1",
+ "multi_sgmii1", "usxgmii1",
+ "hsgmii_rate_adp1",
+ "pcs_ana", "pcs_pma0", "pcs_pma1";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <1>;
+ };
+
+ pcs@1fa07000 {
+ compatible = "airoha,an7581-pcs-usb";
+ reg = <0x1fa07000 0x1000>,
+ <0x1fa90000 0x60>,
+ <0x1fa90a00 0x164>,
+ <0x1fa94000 0x450>,
+ <0x1fa96000 0x300>,
+ <0x1fa9a000 0x600>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "hsgmii_rate_adp","pcs_ana";
+
+ phys = <&usb0_phy PHY_TYPE_USB3>;
+
+ #pcs-cells = <0>;
+ };
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 09/12] net: phylink: add .pcs_link_down PCS OP
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Permit for PCS driver to define specific operation to tear down the link
between the MAC and the PCS.
This might be needed for some PCS that reset counter or require special
reset to correctly work if the link needs to be restored later.
On phylink_link_down() call, the additional phylink_pcs_link_down() will
be called after .mac_link_down to tear down the link.
PCS driver will need to define .pcs_link_down to make use of this.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 9 +++++++++
include/linux/phylink.h | 12 ++++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index b9a212bd1206..b2b1d57dacd2 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -1038,6 +1038,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
}
+static void phylink_pcs_link_down(struct phylink_pcs *pcs)
+{
+ if (pcs && pcs->ops->pcs_link_down)
+ pcs->ops->pcs_link_down(pcs);
+}
+
static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
{
if (pcs && pcs->ops->pcs_disable_eee)
@@ -1739,6 +1745,9 @@ static void phylink_link_down(struct phylink *pl)
pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
pl->cur_interface);
+
+ phylink_pcs_link_down(pl->pcs);
+
phylink_info(pl, "Link is Down\n");
}
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 15e6b1a39dfe..ecf4c384fd31 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -528,6 +528,7 @@ struct phylink_pcs {
* @pcs_an_restart: restart 802.3z BaseX autonegotiation.
* @pcs_link_up: program the PCS for the resolved link configuration
* (where necessary).
+ * @pcs_link_down: tear down link between MAC and PCS.
* @pcs_disable_eee: optional notification to PCS that EEE has been disabled
* at the MAC.
* @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
@@ -555,6 +556,7 @@ struct phylink_pcs_ops {
void (*pcs_an_restart)(struct phylink_pcs *pcs);
void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+ void (*pcs_link_down)(struct phylink_pcs *pcs);
void (*pcs_disable_eee)(struct phylink_pcs *pcs);
void (*pcs_enable_eee)(struct phylink_pcs *pcs);
int (*pcs_pre_init)(struct phylink_pcs *pcs);
@@ -690,6 +692,16 @@ void pcs_an_restart(struct phylink_pcs *pcs);
void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+/**
+ * pcs_link_up() - tear down link between MAC and PCS
+ * @pcs: a pointer to a &struct phylink_pcs.
+ *
+ * This call will be made just after mac_link_down() to inform the PCS the
+ * link has gone down. PCS should be configured to stop processing packets
+ * for transmission and reception.
+ */
+void pcs_link_down(struct phylink_pcs *pcs);
+
/**
* pcs_disable_eee() - Disable EEE at the PCS
* @pcs: a pointer to a &struct phylink_pcs
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 07/12] MAINTAINERS: add myself as PCS subsystem maintainer
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
List all the files of the Ethernet PCS subsystem and add myself as
maintainer.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cc1dde0c9067..ef3ef5096d08 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9593,6 +9593,15 @@ F: include/uapi/linux/if_bridge.h
F: include/linux/netfilter_bridge/
F: net/bridge/
+ETHERNET PCS SUBSYSTEM
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/networking/pcs.rst
+F: drivers/net/pcs/pcs.c
+F: include/linux/pcs/pcs-provider.h
+F: include/linux/pcs/pcs.h
+
ETHERNET PHY LIBRARY
M: Andrew Lunn <andrew@lunn.ch>
M: Heiner Kallweit <hkallweit1@gmail.com>
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 08/12] of: property: fw_devlink: Add support for "pcs-handle"
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Add support for parsing PCS binding so that fw_devlink can
enforce the dependency with Ethernet port.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/of/property.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/of/property.c b/drivers/of/property.c
index 136946f8b746..e6584a2f705d 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -1392,6 +1392,7 @@ DEFINE_SIMPLE_PROP(access_controllers, "access-controllers", "#access-controller
DEFINE_SIMPLE_PROP(pses, "pses", "#pse-cells")
DEFINE_SIMPLE_PROP(power_supplies, "power-supplies", NULL)
DEFINE_SIMPLE_PROP(mmc_pwrseq, "mmc-pwrseq", NULL)
+DEFINE_SIMPLE_PROP(pcs_handle, "pcs-handle", "#pcs-cells")
DEFINE_SUFFIX_PROP(regulators, "-supply", NULL)
DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells")
@@ -1548,6 +1549,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_interrupts, },
{ .parse_prop = parse_interrupt_map, },
{ .parse_prop = parse_access_controllers, },
+ { .parse_prop = parse_pcs_handle, },
{ .parse_prop = parse_regulators, },
{ .parse_prop = parse_gpio, },
{ .parse_prop = parse_gpios, },
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 06/12] net: Document PCS subsystem
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Add extensive documentation of the new PCS subsystem and the fwnode
implementation with producer/consumer API.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Documentation/networking/index.rst | 1 +
Documentation/networking/pcs.rst | 229 +++++++++++++++++++++++++++++
2 files changed, 230 insertions(+)
create mode 100644 Documentation/networking/pcs.rst
diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst
index 44a422ad3b05..3fce8f6ac089 100644
--- a/Documentation/networking/index.rst
+++ b/Documentation/networking/index.rst
@@ -28,6 +28,7 @@ Contents:
net_failover
page_pool
phy
+ pcs
sfp-phylink
alias
bridge
diff --git a/Documentation/networking/pcs.rst b/Documentation/networking/pcs.rst
new file mode 100644
index 000000000000..98592cdee3ef
--- /dev/null
+++ b/Documentation/networking/pcs.rst
@@ -0,0 +1,229 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=============
+PCS Subsystem
+=============
+
+The PCS (Physical Coding Sublayer) subsystem handles the registration and lookup
+of PCS devices. These devices contain the upper sublayers of the Ethernet
+physical layer, generally handling framing, scrambling, and encoding tasks. PCS
+devices may also include PMA (Physical Medium Attachment) components. PCS
+devices transfer data between the Link-layer MAC device, and the rest of the
+physical layer, typically via a serdes. The output of the serdes may be
+connected more-or-less directly to the medium when using fiber-optic or
+backplane connections (1000BASE-SX, 1000BASE-KX, etc). It may also communicate
+with a separate PHY (such as over SGMII) which handles the connection to the
+medium (such as 1000BASE-T).
+
+Remark on usage of .mac_select_pcs and fw_node PCS
+--------------------------------------------------
+
+There are generally two ways to look up a PCS device.
+
+1. MAC OP struct .mac_select_pcs (considered legacy)
+2. firmware node (fwnode) PCS entirely handled by phylink
+
+Implementation 1 leaves the entire handling of the PCS to the MAC
+driver with the selection of the PCS driven by .mac_select_pcs.
+Custom implementations are required if the PCS is external to the MAC
+and needs to be handled by a separate driver.
+
+This implementation is considered legacy and it's suggested to
+switch to the new fwnode PCS.
+
+Looking up PCS Devices (fwnode implementation)
+-----------------------------------------------
+
+The lookup of a PCS device follows the common producer/consumer implementation
+used by similar subsystems with a ``#pcs-cells`` on the producer and a
+``pcs-handle`` property on the consumer::
+
+ pcs: pcs {
+ // ...
+ #pcs-cells = <0>;
+ };
+
+ ethernet-controller {
+ // ...
+ pcs-handle = <&pcs>;
+ };
+
+On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` to compose the list of available PCS that can be
+used for the phylink instance.
+
+Phylink will then internally handle the selection of the correct PCS for
+the requested interface mode based on the interface modes configured in
+``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+A PCS is considered eligible when the requested interface mode is present
+in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+``supported_interfaces`` describes all interface modes supported by the MAC,
+whereas ``pcs_interfaces`` identifies the subset that require PCS selection.
+
+For the special implementation where the PCS is internal or part of the MAC
+and a dedicated driver is not needed, it's possible to leave the implementation
+of the PCS to the MAC driver and just implement the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` referencing the local :c:struct:`phylink_pcs`
+struct allocated from the MAC driver.
+
+Using PCS Devices
+-----------------
+
+It's mandatory to either implement the ``mac_select_pcs`` callback
+of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_available_pcs``
+of :c:struct:`phylink_config` to use a PCS for a MAC.
+
+The fwnode implementation exposes simple helpers to parse the PCS from
+the fwnode :c:func:`fwnode_phylink_pcs_count` and
+:c:func:`fwnode_phylink_pcs_parse`. The :c:func:`fwnode_phylink_pcs_count` helper
+takes the fwnode where the ``pcs-handle`` should be parsed and return the
+number of PCS entries described in the fwnode.
+The :c:func:`fwnode_phylink_pcs_parse` helper takes three arguments,
+the fwnode where the ``pcs-handle`` should be parsed, an allocated array
+of :c:struct:`phylink_pcs` pointer where to put the parsed PCS from the fwnode
+and the maximum number of PCS to parse.
+Contrary to :c:func:`fwnode_phylink_pcs_count`, :c:func:`fwnode_phylink_pcs_parse`
+helper fills the allocated array with ONLY the available PCS and return the
+number of available PCS found. PCS that returns -ENODEV will be skipped and
+won't be inserted in the allocated array.
+
+A phylink instance may use multiple PCS devices. The maximum number is reported
+through ``num_possible_pcs``.
+
+It's mandatory to specify for what interface a PCS is needed. This can be done
+by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct.
+If the requested interface mode is not present in this bitmask, phylink does
+not search for a PCS for that specific mode. (example MAC doesn't need a PCS
+for SGMII but require one for USXGMII)
+
+With the use of the :c:func:`fwnode_phylink_pcs_parse` a common implementation
+is the following::
+
+ static int mac_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+ {
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+ }
+
+ static int mac_setup_phylink(struct net_device *netdev)
+ {
+ struct phylink_config *config;
+
+ // ...
+
+ config->dev = &netdev->dev;
+
+ // ...
+
+ // Parse possible PCS and fill num_possible_pcs.
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(&netdev->dev));
+ config->fill_available_pcs = mac_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces);
+
+ // PCS required only for USXGMII
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->pcs_interfaces);
+
+ phylink = phylink_create(config, //...
+
+It's worth to mention that it's phylink code that takes care of allocating
+the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs``
+callback based on the value set in ``num_possible_pcs`` for
+:c:struct:`phylink_config` struct.
+
+The ``fill_available_pcs`` callback must not write more than
+``num_possible_pcs`` entries. The third argument may be used to validate
+that there is enough space to fill all the available PCS in the passed array
+of :c:struct:`phylink_pcs` pointer.
+
+The ``fill_available_pcs`` callback is called only on :c:func:`phylink_create`
+and is used only to compose the initial available PCS list. Ownership of PCS
+is held by phylink and :c:func:`phylink_release_pcs` should be used to release
+them.
+
+Writing PCS Drivers
+-------------------
+
+To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then,
+register your PCS in your probe function using :c:func:`fwnode_pcs_add_provider`.
+The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode where
+the PCS provider should be registered to, a get function to return the requested
+PCS based on ``#pcs-cells`` and a pointer to reference private data for the get
+function.
+
+The PCS will then be registered to a global list of PCS provider that the
+PCS fwnode implementation will use to parse it.
+
+For the simple case where the PCS driver expose a single PCS,
+:c:func:`fwnode_pcs_simple_get` can be used as the get function.
+
+You must call :c:func:`fwnode_pcs_del_provider` from your remove function and
+release the PCS from any phylink instance under RTNL lock with
+:c:func:`phylink_release_pcs`::
+
+ fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+ rtnl_lock();
+
+ for (i = 0; i < data->num_port; i++) {
+ struct pcs_port *port = &priv->ports[i];
+
+ phylink_release_pcs(&port->pcs);
+ }
+
+ rtnl_unlock();
+
+Late PCS registration handling
+------------------------------
+
+It's possible that a PCS becomes available after the MAC finished probing.
+Contrary to the usual producer/consumer implementation, when a PCS is not
+registered and can't be found, the fwnode parser helper returns ``-ENODEV``
+instead of ``-EPROBE_DEFER``.
+
+This is to prevent race condition with particular devices that register
+MAC and PCS with USB or PCIe and require the MAC to be registered before
+the PCS.
+
+The phylink logic correctly handle this special case and keep the phylink
+instance in a fail condition.
+
+The PCS fwnode implementation provides a notifier to which each phylink
+instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config`
+registers. When a new PCS provider is registered, the notifier is called
+triggering the :c:func:`pcs_provider_notify` function.
+
+Function :c:func:`pcs_provider_notify` will check if the just added PCS
+should be used by the phylink instance. If it should be used then,
+it's added to the internal list of available PCS and a phylink major
+config is forced.
+
+If a phylink instance was in a failure state, with the just added PCS
+now part of the available PCS internal phylink list, provided all other
+conditions are satisfied, the configuration is retried and the failure
+condition is cleared.
+
+API Reference
+-------------
+
+.. kernel-doc:: include/linux/phylink.h
+ :identifiers: phylink_pcs
+
+.. kernel-doc:: include/linux/pcs/pcs.h
+ :internal:
+
+.. kernel-doc:: include/linux/pcs/pcs-provider.h
+ :internal:
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 05/12] net: phylink: support late PCS provider attach
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Add support for late PCS provider attachment to a phylink instance.
This works by creating a global notifier for the PCS provider and
making each phylink instance that makes use of fwnode subscribe to
this notifier.
The PCS notifier will emit the event FWNODE_PCS_PROVIDER_ADD every time
a new PCS provider is added.
phylink will then react to this event and will call the new function
fwnode_phylink_pcs_get_from_fwnode() that will check if the PCS fwnode
provided by the event is present in the pcs-handle property of the
phylink instance.
If a related PCS is found, then such PCS is added to the phylink
instance PCS list.
Then we link the PCS to the phylink instance and we refresh the supported
interfaces of the phylink instance.
Finally we check if we are in a major_config_failed scenario and trigger
an interface reconfiguration in the next phylink resolve.
In the example scenario where the link was previously torn down due to
removal of PCS, the link will be established again as the PCS came back
and is now available to phylink.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/pcs.c | 49 +++++++++++++++++++++++++++++
drivers/net/phy/phylink.c | 60 +++++++++++++++++++++++++++++++++++-
include/linux/pcs/pcs.h | 65 +++++++++++++++++++++++++++++++++++++++
3 files changed, 173 insertions(+), 1 deletion(-)
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
index 0cc4daf7beea..7a9d91b2a34d 100644
--- a/drivers/net/pcs/pcs.c
+++ b/drivers/net/pcs/pcs.c
@@ -22,6 +22,19 @@ struct fwnode_pcs_provider {
static LIST_HEAD(fwnode_pcs_providers);
static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
+
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);
struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
void *data)
@@ -55,6 +68,10 @@ int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
fwnode_dev_initialized(fwnode, true);
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_ADD,
+ fwnode);
+
return 0;
}
EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
@@ -150,6 +167,38 @@ struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, unsigned int in
}
EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ struct fwnode_reference_args pcsspec;
+ int index = 0;
+ int ret;
+
+ /* Loop until we find a matching PCS node or
+ * fwnode_parse_pcsspec() returns error
+ * if we don't have any other PCS reference to check.
+ */
+ while (true) {
+ ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ /* Exit loop if we found the matching PCS node */
+ if (pcsspec.fwnode == pcs_fwnode) {
+ fwnode_handle_put(pcsspec.fwnode);
+ break;
+ }
+
+ /* Check the next PCS reference */
+ fwnode_handle_put(pcsspec.fwnode);
+ index++;
+ }
+
+ return fwnode_pcs_get(fwnode, index);
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);
+
unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
{
struct fwnode_reference_args out_args;
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 064d6f5a06da..b9a212bd1206 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/phylink.h>
@@ -62,6 +63,7 @@ struct phylink {
/* List of available PCS */
struct list_head pcs_list;
+ struct notifier_block fwnode_pcs_nb;
/* What interface are supported by the current link.
* Can change on removal or addition of new PCS.
@@ -2000,6 +2002,53 @@ static int phylink_fill_available_pcs(struct phylink *pl,
return ret;
}
+static int pcs_provider_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+ struct fwnode_handle *pcs_fwnode = data;
+ struct phylink_pcs *pcs;
+
+ rtnl_lock();
+
+ /* Check if the just added PCS provider is
+ * in the phylink instance pcs-handle property.
+ */
+ pcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl->config->dev),
+ pcs_fwnode);
+ if (IS_ERR(pcs)) {
+ rtnl_unlock();
+ return NOTIFY_DONE;
+ }
+
+ /* Add the PCS */
+ mutex_lock(&pl->state_mutex);
+
+ /* Link PCS with phylink */
+ list_add(&pcs->list, &pl->pcs_list);
+ pcs->phylink = pl;
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ /* Force an interface reconfig if major config fail */
+ if (pl->major_config_failed)
+ pl->force_major_config = true;
+
+ mutex_unlock(&pl->state_mutex);
+
+ rtnl_unlock();
+
+ phylink_run_resolve(pl);
+
+ return NOTIFY_OK;
+}
+
/**
* phylink_create() - create a phylink instance
* @config: a pointer to the target &struct phylink_config
@@ -2124,6 +2173,12 @@ struct phylink *phylink_create(struct phylink_config *config,
if (ret < 0)
goto unlink_pcs_list;
+ /* Register notifier for late PCS attach */
+ if (!phy_interface_empty(config->pcs_interfaces)) {
+ pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+ register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+ }
+
return pl;
unlink_pcs_list:
@@ -2152,10 +2207,13 @@ void phylink_destroy(struct phylink *pl)
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+ /* Unregister notifier for late PCS attach */
+ if (pl->fwnode_pcs_nb.notifier_call)
+ unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+
cancel_work_sync(&pl->resolve);
/* Drop link between PCS and phylink */
- /* Remove every PCS from phylink PCS list */
list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
pcs->phylink = NULL;
list_del(&pcs->list);
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
index b7cfdd680b2a..45e8f96662db 100644
--- a/include/linux/pcs/pcs.h
+++ b/include/linux/pcs/pcs.h
@@ -4,7 +4,36 @@
#include <linux/phylink.h>
+enum fwnode_pcs_notify_event {
+ FWNODE_PCS_PROVIDER_ADD,
+};
+
#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns: 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Unregisters a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain.
+ *
+ * Returns: 0 or a negative error.
+ */
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb);
+
/**
* fwnode_pcs_get - Retrieves a PCS from a firmware node
* @fwnode: firmware node
@@ -20,6 +49,25 @@
struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
unsigned int index);
+/**
+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
+ * by the firmware node from a
+ * firmware node
+ * @fwnode: firmware node
+ * @pcs_fwnode: PCS firmware node
+ *
+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
+ * 'pcs_fwnode' firmware node.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode);
+
/**
* fwnode_phylink_pcs_count - count PCS entries described in firmware node
* @fwnode: firmware node
@@ -53,12 +101,29 @@ int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
struct phylink_pcs **available_pcs,
unsigned int num_pcs);
#else
+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
unsigned int index)
{
return ERR_PTR(-ENOENT);
}
+static inline struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ return ERR_PTR(-ENOENT);
+}
+
static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
{
return 0;
--
2.53.0
^ permalink raw reply related
* [RFC PATCH net-next v8 04/12] net: pcs: implement Firmware node support for PCS driver
From: Christian Marangi @ 2026-06-18 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm, Maxime Chevallier
Cc: Daniel Golle
In-Reply-To: <20260618125752.1223-1-ansuelsmth@gmail.com>
Implement the foundation of Firmware node support for PCS driver.
To support this, implement a simple Provider API where a PCS driver can
expose multiple PCS with an xlate .get function.
PCS driver will have to call fwnode_pcs_add_provider() and pass the
firmware node pointer and a xlate function to return the correct PCS for
the passed #pcs-cells.
This will register the PCS in a global list of providers so that
consumer can access it.
The consumer will then use fwnode_pcs_get() to get the actual PCS by
passing the firmware node pointer and the index for #pcs-cells.
For a simple implementation where #pcs-cells is 0 and the PCS driver
expose a single PCS, the xlate function fwnode_pcs_simple_get() is
provided.
For an advanced implementation a custom xlate function is required.
On removal the PCS driver should first delete itself from the provider
list using fwnode_pcs_del_provider() and then call phylink_release_pcs()
on every PCS the driver provides.
Generic functions fwnode_phylink_pcs_count() and fwnode_phylink_pcs_parse()
are provided for MAC driver that will declare PCS in DT (or ACPI).
Function fwnode_phylink_pcs_count() will parse "pcs-handle" property and
will return the number of PCS entries described in the passed firmware
node.
Function fwnode_phylink_pcs_parse() will parse "pcs-handle" property and
fill the passed available_pcs array with the available PCS found up to passed
num_pcs value. It's worth to mention that this function will ignore PCS
that still needs to be probed (returning -ENODEV) and such PCS won't be
added to the available_pcs array.
Co-developed-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/Kconfig | 6 +
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs.c | 212 +++++++++++++++++++++++++++++++
include/linux/pcs/pcs-provider.h | 41 ++++++
include/linux/pcs/pcs.h | 75 +++++++++++
5 files changed, 335 insertions(+)
create mode 100644 drivers/net/pcs/pcs.c
create mode 100644 include/linux/pcs/pcs-provider.h
create mode 100644 include/linux/pcs/pcs.h
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index e417fd66f660..2ce89d4bff6b 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,12 @@
menu "PCS device drivers"
+config FWNODE_PCS
+ bool "PCS Firmware Node"
+ depends on (ACPI || OF)
+ help
+ Firmware node PCS accessors
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b90..3005cdd89ab7 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Linux PCS drivers
+obj-$(CONFIG_FWNODE_PCS) += pcs.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 000000000000..0cc4daf7beea
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+ struct list_head link;
+
+ struct fwnode_handle *fwnode;
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+ void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
+
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return 0;
+
+ pp = kzalloc_obj(*pp);
+ if (!pp)
+ return -ENOMEM;
+
+ pp->fwnode = fwnode_handle_get(fwnode);
+ pp->data = data;
+ pp->get = get;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_add(&pp->link, &fwnode_pcs_providers);
+ mutex_unlock(&fwnode_pcs_mutex);
+ pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+ fwnode_dev_initialized(fwnode, true);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(pp, &fwnode_pcs_providers, link) {
+ if (pp->fwnode == fwnode) {
+ list_del(&pp->link);
+ fwnode_dev_initialized(pp->fwnode, false);
+ fwnode_handle_put(pp->fwnode);
+ kfree(pp);
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode,
+ int index, const char *name,
+ struct fwnode_reference_args *out_args)
+{
+ int ret;
+
+ if (!fwnode)
+ return -EINVAL;
+
+ if (name) {
+ index = fwnode_property_match_string(fwnode, "pcs-names",
+ name);
+ if (index < 0)
+ return index;
+ }
+
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, out_args);
+ if (ret || (name && index < 0))
+ return ret;
+
+ return 0;
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+ struct fwnode_pcs_provider *provider;
+ struct phylink_pcs *pcs = ERR_PTR(-ENODEV);
+
+ if (!pcsspec)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+ if (provider->fwnode == pcsspec->fwnode) {
+ pcs = provider->get(pcsspec, provider->data);
+ if (!IS_ERR(pcs))
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ return pcs;
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index, const char *con_id)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+ fwnode_handle_put(pcsspec.fwnode);
+
+ return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, unsigned int index)
+{
+ return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ struct fwnode_reference_args out_args;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, &out_args);
+ /* We expect to reach an -ENOENT error while counting */
+ if (ret)
+ break;
+
+ fwnode_handle_put(out_args.fwnode);
+ index++;
+ }
+
+ return index;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count);
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ unsigned int i, found = 0;
+
+ if (!available_pcs)
+ return -EINVAL;
+
+ if (!fwnode_property_present(fwnode, "pcs-handle"))
+ return -ENODEV;
+
+ for (i = 0; i < num_pcs; i++) {
+ struct phylink_pcs *pcs;
+
+ pcs = fwnode_pcs_get(fwnode, i);
+ if (IS_ERR(pcs)) {
+ /* Exit early if no PCS remain.*/
+ if (PTR_ERR(pcs) == -ENOENT)
+ break;
+
+ /*
+ * Ignore -ENODEV error for PCS that still
+ * needs to probe.
+ */
+ if (PTR_ERR(pcs) == -ENODEV)
+ continue;
+
+ return PTR_ERR(pcs);
+ }
+
+ available_pcs[found] = pcs;
+ found++;
+ }
+
+ return found;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 000000000000..ae51c108147e
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+/**
+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns: the PCS pointed by data.
+ */
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @fwnode: Firmware node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the firmware node. A function to get the PCS from
+ * firmware node with the use fwnode reference arguments.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns: 0 on success or -ENOMEM on allocation failure.
+ */
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @fwnode: Firmware node
+ */
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 000000000000..b7cfdd680b2a
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -ENODEV if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed).
+ */
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index);
+
+/**
+ * fwnode_phylink_pcs_count - count PCS entries described in firmware node
+ * @fwnode: firmware node
+ *
+ * Helper function to count the number of PCS entries referenced by the
+ * "pcs-handle" property in a firmware node.
+ *
+ * Note that this function counts all PCS references in the firmware node,
+ * regardless of whether the corresponding PCS devices are already probed.
+ *
+ * Returns: number of PCS entries described in the firmware node.
+ */
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode);
+
+/**
+ * fwnode_phylink_pcs_parse - parse available PCS from firmware node
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: maximum number of PCS entries to scan
+ *
+ * Helper function that parses PCS references from the "pcs-handle"
+ * property of a firmware node and fills @available_pcs with PCS that are
+ * currently available up to @num_pcs.
+ *
+ * Only PCS that are currently available are stored in @available_pcs.
+ * PCS that returns -ENODEV are skipped.
+ *
+ * Returns: number of PCS stored in @available_pcs, or negative error code.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs);
+#else
+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ return 0;
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
--
2.53.0
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