From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by oss.sgi.com (8.11.3/8.11.3) id f488LC106369 for linux-mips-outgoing; Tue, 8 May 2001 01:21:12 -0700 Received: from kauha.saunalahti.fi (kauha.saunalahti.fi [195.197.53.227]) by oss.sgi.com (8.11.3/8.11.3) with ESMTP id f488LAF06366 for ; Tue, 8 May 2001 01:21:10 -0700 Received: from concertina (dyn-3-085.tku.netti.fi [195.16.220.86]) by kauha.saunalahti.fi (8.10.1/8.10.1) with SMTP id f488L5P10473; Tue, 8 May 2001 11:21:05 +0300 (EEST) Message-ID: <001d01c0d798$4303d7a0$56dc10c3@tal.org> From: "Kaj-Michael Lang" To: "Geert Uytterhoeven" Cc: References: Subject: Re: Linux on a Tektronix XP217C xterm Date: Tue, 8 May 2001 11:24:11 +0300 Organization: Tal.Org MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Sender: owner-linux-mips@oss.sgi.com Precedence: bulk > IIRC there's a different separate graphics chip in the 217. I think the 33020 > is not a MIPS, but a RISC chip from LSI Logic. > LR33020/33120: Embedded R3000 for X-terminals; reimplemented core; static design; 25 to 40 MHz; 4-kbyte instruction cache; 1-kbyte data cache; graphics coprocessor with bitblt processor and DMA channel. From mboxrd@z Thu Jan 1 00:00:00 1970 Message-ID: <001d01c0d798$4303d7a0$56dc10c3@tal.org> From: "Kaj-Michael Lang" References: Subject: Re: Linux on a Tektronix XP217C xterm Date: Tue, 8 May 2001 11:24:11 +0300 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Sender: owner-linux-mips@oss.sgi.com To: Geert Uytterhoeven Cc: linux-mips@oss.sgi.com Message-ID: <20010508082411.EWO8fTmvjjzD51Riai3YJbb8g9s7MGFprISfT0FZ5rk@z> > IIRC there's a different separate graphics chip in the 217. I think the 33020 > is not a MIPS, but a RISC chip from LSI Logic. > LR33020/33120: Embedded R3000 for X-terminals; reimplemented core; static design; 25 to 40 MHz; 4-kbyte instruction cache; 1-kbyte data cache; graphics coprocessor with bitblt processor and DMA channel.