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AJvYcCWAHhUK03cDBEJRa+sOFgEe9U0g0eL4BfMebxXYhWNMgbEG5oORMwFlWQ8MX+4QAK5g8cnb7FBiUc8hpk/IMJey6m89KBC9Uizl1Q== X-Gm-Message-State: AOJu0YzqAqtIwDrOHqyEAvR2qAYP7WTU0AU+ox0IiObBXb1meWqQjV5o NerT9LMs2+3QaPgKvlEjbVzaJbVviDl5r1CXz6paNqdLX9tx42Ga/Ytw0YuiUXq3VeAYwUKCe3V 9H7U= X-Google-Smtp-Source: AGHT+IH4Kh0h4/Hczoc0Zp0xPOSEe6v0ZhamuCceNxDEYLUCUwyJEorjIWlpkcHWZTjNRoyxbVymmg== X-Received: by 2002:adf:f801:0:b0:354:eb62:3653 with SMTP id ffacd0b85a97d-3552fdc8090mr6257038f8f.53.1716813092584; Mon, 27 May 2024 05:31:32 -0700 (PDT) Received: from [192.168.69.100] ([176.176.152.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-356c8daef27sm6814638f8f.115.2024.05.27.05.31.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 May 2024 05:31:32 -0700 (PDT) Message-ID: <06b06b65-8eb7-43f6-8fb5-e5663876edb5@linaro.org> Date: Mon, 27 May 2024 14:31:29 +0200 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 08/14] clocksource: mips-gic-timer: Enable counter when CPUs start To: Aleksandar Rikalo , Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang References: <20240511104341.151550-1-aleksandar.rikalo@syrmia.com> <20240511104341.151550-9-aleksandar.rikalo@syrmia.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240511104341.151550-9-aleksandar.rikalo@syrmia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 11/5/24 12:43, Aleksandar Rikalo wrote: > From: Paul Burton > > In multi-cluster MIPS I6500 systems we have a GIC in each cluster, each > with its own counter. When a cluster powers up the counter will be > stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. > > In single cluster systems it has been fine for us to clear COUNTSTOP > once in gic_clocksource_of_init() in order to start the counter, since > with only one cluster we know that we won't be resetting that cluster's > GIC at any point (ignoring suspend/resume cycles which would need to > handle clearing COUNTSTOP in the resume path). Once we support > multi-cluster systems this will only have started the counter in the > boot cluster, and any CPUs in other clusters will find their counter > stopped which will break the GIC clock_event_device. > > Resolve this by having CPUs clear the COUNTSTOP bit when they come > online, using the existing gic_starting_cpu() CPU hotplug callback. This > will allow CPUs in secondary clusters to ensure that the cluster's GIC > counter is running as expected. > > Signed-off-by: Paul Burton > Signed-off-by: Chao-ying Fu > Signed-off-by: Dragan Mladjenovic > Signed-off-by: Aleksandar Rikalo > --- > drivers/clocksource/mips-gic-timer.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé