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From: Pete Popov <ppopov@pacbell.net>
To: "TWEDE,ROGER   ""(HP-Boise,ex1)" <roger_twede@hp.com>
Cc: linux-mips <linux-mips@oss.sgi.com>
Subject: Re: Mips IRQ support
Date: 22 Jan 2002 17:26:19 -0800	[thread overview]
Message-ID: <1011749179.28944.262.camel@zeus> (raw)
In-Reply-To: <CBD6266EA291D5118144009027AA63353F92B7@xboi05.boi.hp.com>

On Tue, 2002-01-22 at 17:15, TWEDE,ROGER (HP-Boise,ex1) wrote:
> 
> Are there any plans to provide full MIPS irq support in the general mips irq
> code?
> 
> The only machine that appears to attempt to fully support the MIPS interrupt
> set currently is the gt64120/momenco_ocelot machine.
 
> It uses the define CP0_S1_INTCONTROL ($20) to get at the upper interrupt
> lines ( > 8 ).

That's really a QED rm7k cpu feature, not a mips generic one.
 
> Anyone else find that support for this MIPS hardware would be best placed in
> the standard irq code rather than each machine variant having to
> re-implement it itself (as the irq code was in the past).

Might be a good feature for arch/mips/kernel/irq_cpu.c and it wouldn't
be difficult to add.  I don't think arch/mips/kernel/irq.c needs to
change.

Pete

  reply	other threads:[~2002-01-23  2:24 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2002-01-23  1:15 Mips IRQ support TWEDE,ROGER (HP-Boise,ex1)
2002-01-23  1:26 ` Pete Popov [this message]
2002-01-23  1:26   ` Pete Popov
2002-01-23  1:27 ` Jun Sun
2002-01-23  1:40   ` Jason Gunthorpe

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