From: Michael Uhler <uhler@mips.com>
To: karthikeyan natarajan <karthik_96cse@yahoo.com>
Cc: linux-mips@linux-mips.org
Subject: Re: Regarding branch delay instructions in R4000
Date: 18 Dec 2003 22:41:32 -0800 [thread overview]
Message-ID: <1071816092.30316.8.camel@gmu-linux> (raw)
In-Reply-To: <20031219060127.90257.qmail@web10107.mail.yahoo.com>
The MIPS architecture specifies a single delay slot after a branch
or jump. The fact that the R4000 implementation (and pretty much
any of the ones following) had a pipeline in which more instructions
had already entered the pipe before the branch is resolved is not
relevant to the architecture specification. In the case you
mention, a single instruction is executed after the branch, as
architecturally required, and any subsequent instructions in the
pipe are killed.
/gmu
On Thu, 2003-12-18 at 22:01, karthikeyan natarajan wrote:
> Hi All,
>
> If this is not a right forum to ask this Question,
>
> please redirect me to the appropriate one...
> Since R4000 is using the 8 stage pipeline, three
> instructions are already entered into the pipeline
> when the branch instruction is executed. Out of these
> three instructions, the first instruction will be
> executed for sure.
>
> My question is:
> What happens to the other two instruction that are
> in the delay slots? are they nullified?
> Could anyone please shed some light on this.
>
> Thanks much,
> -karthi
>
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Michael Uhler, Chief Technology Officer
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next prev parent reply other threads:[~2003-12-19 6:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-12-19 6:01 Regarding branch delay instructions in R4000 karthikeyan natarajan
2003-12-19 6:41 ` Michael Uhler [this message]
2003-12-20 9:53 ` karthikeyan natarajan
2003-12-20 10:16 ` Kevin D. Kissell
2003-12-20 10:16 ` Kevin D. Kissell
2003-12-22 12:47 ` Maciej W. Rozycki
2004-01-04 9:09 ` Regarding the LL & SC instructions karthikeyan natarajan
2004-01-04 21:47 ` Kevin D. Kissell
2004-01-04 21:47 ` Kevin D. Kissell
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