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Wed, 15 Jan 2025 04:26:30 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Wed, 15 Jan 2025 09:26:11 +0000 From: "Jiaxun Yang" To: "Arnd Bergmann" , "Thomas Bogendoerfer" , "Baoquan He" Cc: "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org, "stable@vger.kernel.org" , =?UTF-8?Q?Mateusz_Jo=C5=84czyk?= Message-Id: <11e402c9-ea38-4132-9ab6-0bd346a82c88@app.fastmail.com> In-Reply-To: <23f46c23-a58e-4a85-8733-480b5ebf993b@app.fastmail.com> References: <20250114-malta-io-fixes-v1-1-74ef1dc402ec@flygoat.com> <5ef27e01-2c5a-400a-be32-d3bcdeea6d26@app.fastmail.com> <23f46c23-a58e-4a85-8733-480b5ebf993b@app.fastmail.com> Subject: Re: [PATCH] MIPS: pci-legacy: Override pci_address_to_pio Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B41=E6=9C=8815=E6=97=A5=E4=B8=80=E6=9C=88 =E4=B8=8A=E5= =8D=887:38=EF=BC=8CArnd Bergmann=E5=86=99=E9=81=93=EF=BC=9A [...] > > Where "range->cpu_addr" is the phys_addr_t location of the > MMIO window that maps the host controllers port ranges, i.e. > the fully translated address from the "ranges" property. This is valid for MIPS's PCI_DRIVERS_GENERIC, but not for PCI_DRIVERS_LE= GACY, which have it's own implementation of various functions. See arch/mips/pci/pci-legacy.c, pci_load_of_ranges. The address translation is handled by io_map_base, which usually comes from mips_io_port_base. > > The point of the pci_address_to_pio() function is to convert > this into the Linux-internal virtual port number that gets > used as an argument to inb()/outb() and reported in > /proc/ioports and that may or may not be the same as the > address on the bus itself, depending on the how the translation > gets set up. > > On loongson, we seem to have two port ranges that are set up > like > > isa@18000000 { > compatible =3D "isa"; > ranges =3D <1 0x0 0x0 0x18000000 0x4000>; > }; > > pci@1a000000 { > ranges =3D <0x01000000 0x0 0x00020000 0x0=20 > 0x18020000 0x0 0x00020000>, > <0x02000000 0x0 0x40000000 0x0=20 > 0x40000000 0x0 0x40000000>; > } > > Here, the cpu_addr is 0x18000000 for the isa bus and=20 > 0x18020000 for the PCI bus, apparently the intention being that > these are consecutive in physical space, though Linux is free > to rearrange the logical port numbers in a different way, e.g. > to ensure that the PCI bus can use port numbers below 0x10000. > > On Malta, I see a very strange > > isa { > compatible =3D "isa"; > ranges =3D <1 0 0 0x1000>; > }; > > which maps the first 4096 port numbers into cpu_addr=3D0x0. The > actual port window appears to be at a board specific location > > #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) > #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0= x10000)) > #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) > > So e.g. on Bonito, the ranges property would have to be > > ranges =3D <1 0 0x1fd00000 0x1000>; > > Not sure if this is patched in by the bootloader, or where the > corresponding window for PCI gets defined, but I suspect that > the reason for the regression is that the caller of > pci_address_to_pio() accidentally passed in '0' instead of > the physical address, and it happened to work because of the > missing PCI_IOBASE definition but broke after that got defined. Many other pci-legacy drivers are also working this way, PCI core is not aware of virtual port to physical MMIO address mapping. PCI core just see it as x86 style port. Thanks > > Arnd --=20 - Jiaxun