From: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: John Crispin <blogic@openwrt.org>,
Ralf Baechle <ralf@linux-mips.org>,
Manuel Lauss <manuel.lauss@gmail.com>,
Zi Shen Lim <zlim@netlogicmicro.com>,
Jayachandran C <jchandra@broadcom.com>
Subject: [PATCH v2] MIPS: perf: fix build failure in XLP perf support.
Date: Mon, 17 Dec 2012 08:26:19 +0100 [thread overview]
Message-ID: <1355729179-5442-1-git-send-email-manuel.lauss@gmail.com> (raw)
Commit 4be3d2f3966b9f010bb997dcab25e7af489a841e ("MIPS: perf: Add
XLP support for hardware perf.") added UNSUPPORTED_PERF_EVENT_ID
which was removed a while back.
Cc: Zi Shen Lim <zlim@netlogicmicro.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
---
v2: one escaped me and I left the array in a bad state. Now fixed and compile tested!
Against Linus' latest -git. That's also where the commit-id is from.
arch/mips/kernel/perf_event_mipsxx.c | 38 ------------------------------------
1 file changed, 38 deletions(-)
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index b14c14d..d9c81c5 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -847,7 +847,6 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
[PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
[PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
- [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
};
/* 24K/34K/1004K cores can share the same cache event map. */
@@ -1115,24 +1114,12 @@ static const struct mips_perf_event xlp_cache_map
[C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
[C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
},
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
},
[C(L1I)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
[C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
},
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
},
[C(LL)] = {
[C(OP_READ)] = {
@@ -1143,10 +1130,6 @@ static const struct mips_perf_event xlp_cache_map
[C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
[C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
},
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
},
[C(DTLB)] = {
/*
@@ -1154,45 +1137,24 @@ static const struct mips_perf_event xlp_cache_map
* read and write.
*/
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
[C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
[C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
},
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
},
[C(ITLB)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
[C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
[C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
},
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
},
[C(BPU)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
[C(RESULT_MISS)] = { 0x25, CNTR_ALL },
},
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
- [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
- },
},
};
--
1.8.0.2
next reply other threads:[~2012-12-17 7:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-17 7:26 Manuel Lauss [this message]
2012-12-17 12:46 ` [PATCH v2] MIPS: perf: fix build failure in XLP perf support Jayachandran C.
2012-12-18 12:09 ` John Crispin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1355729179-5442-1-git-send-email-manuel.lauss@gmail.com \
--to=manuel.lauss@gmail.com \
--cc=blogic@openwrt.org \
--cc=jchandra@broadcom.com \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
--cc=zlim@netlogicmicro.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox