From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 30 Aug 2014 00:15:09 +0200 (CEST) Received: from mail-ig0-f202.google.com ([209.85.213.202]:53358 "EHLO mail-ig0-f202.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27007389AbaH2WOuwhZ0c (ORCPT ); Sat, 30 Aug 2014 00:14:50 +0200 Received: by mail-ig0-f202.google.com with SMTP id r2so652805igi.3 for ; Fri, 29 Aug 2014 15:14:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EmJy+NPVQ3/iFjk/Vn0Moyi4UwnkZhAu7Y7crGG1OCw=; b=d6tgCoNwZ9rdK8chD2e4ddEx9PkyHChihXanGPqT5Fmm83Bg1EcmbR9ly0pvO3GgOz c/v0s8D69buJ1oz9nyImlv27UcDPwc+CCxOpoKI6YB7dSYYopgW91OW3/Y1kLNDPX10J mVkfel6fLDJw+9GJk8oQ0CRZLyScIz89m8ST3u9HF/lcr4z69WyI6diok9TZwn97fUEV 4IFmm0MZwXlcJSC60aCiWZKz0IdvA4dQPyQ701U3LHnt0JxjFyPG7tyJLzPZJeZtkxcW vpkLYEnleoBLrwDd6SSy0ReuLZMAnLD1p9SQTHx3EzELAHZWyL7gzqYL8pxKlQsMR6f3 dqKA== X-Gm-Message-State: ALoCoQmIy0SG2qyMkypYOPBurSxjlrzo89FcsJfABfbH84kNiRj7vSieBnlJxvH/YtaQxQLZmWJd X-Received: by 10.182.28.194 with SMTP id d2mr7437563obh.19.1409350484567; Fri, 29 Aug 2014 15:14:44 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id t28si345yhb.4.2014.08.29.15.14.44 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Aug 2014 15:14:44 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.65.70]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 64CBD31C514; Fri, 29 Aug 2014 15:14:44 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 25403221060; Fri, 29 Aug 2014 15:14:44 -0700 (PDT) From: Andrew Bresticker To: Ralf Baechle , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Cc: Andrew Bresticker , Jeffrey Deans , Markos Chandras , Paul Burton , Thomas Gleixner , Jason Cooper , linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/12] MIPS: GIC: Move MIPS_GIC_IRQ_BASE into platform irq.h Date: Fri, 29 Aug 2014 15:14:31 -0700 Message-Id: <1409350479-19108-5-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1409350479-19108-1-git-send-email-abrestic@chromium.org> References: <1409350479-19108-1-git-send-email-abrestic@chromium.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 42324 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: abrestic@chromium.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Define a generic MIPS_GIC_IRQ_BASE which is suitable for Malta and the upcoming Danube board in . Since Sead-3 is different and uses a MIPS_GIC_IRQ_BASE equal to the CPU IRQ base (0), define its MIPS_GIC_IRQ_BASE in . Signed-off-by: Andrew Bresticker --- arch/mips/include/asm/mach-generic/irq.h | 6 ++++++ arch/mips/include/asm/mach-sead3/irq.h | 1 + arch/mips/include/asm/mips-boards/maltaint.h | 2 -- arch/mips/include/asm/mips-boards/sead3int.h | 2 -- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h index 139cd20..c0fc62b 100644 --- a/arch/mips/include/asm/mach-generic/irq.h +++ b/arch/mips/include/asm/mach-generic/irq.h @@ -36,4 +36,10 @@ #endif /* CONFIG_IRQ_CPU */ +#ifdef CONFIG_IRQ_GIC +#ifndef MIPS_GIC_IRQ_BASE +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) +#endif +#endif /* CONFIG_IRQ_GIC */ + #endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h index d8106f7..52c75d5 100644 --- a/arch/mips/include/asm/mach-sead3/irq.h +++ b/arch/mips/include/asm/mach-sead3/irq.h @@ -1,6 +1,7 @@ #ifndef __ASM_MACH_MIPS_IRQ_H #define __ASM_MACH_MIPS_IRQ_H +#define MIPS_GIC_IRQ_BASE 0 #define GIC_NUM_INTRS (24 + NR_CPUS * 2) #define NR_IRQS 256 diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index e330732..9d23343 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -10,8 +10,6 @@ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) - /* * Interrupts 0..15 are used for Malta ISA compatible interrupts */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index 6b17aaf..11ebec9 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -14,6 +14,4 @@ #define GIC_BASE_ADDR 0x1b1c0000 #define GIC_ADDRSPACE_SZ (128 * 1024) -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) - #endif /* !(_MIPS_SEAD3INT_H) */ -- 2.1.0.rc2.206.gedb03e5