From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 25 Sep 2014 04:56:43 +0200 (CEST) Received: from szxga03-in.huawei.com ([119.145.14.66]:65342 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009732AbaIYCxRrMloY (ORCPT ); Thu, 25 Sep 2014 04:53:17 +0200 Received: from 172.24.2.119 (EHLO szxeml409-hub.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id AUU79105; Thu, 25 Sep 2014 10:50:38 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml409-hub.china.huawei.com (10.82.67.136) with Microsoft SMTP Server id 14.3.158.1; Thu, 25 Sep 2014 10:50:31 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , , , , Arnd Bergmann , Thomas Gleixner , "Konrad Rzeszutek Wilk" , , Joerg Roedel , , , Benjamin Herrenschmidt , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Yijing Wang Subject: [PATCH v2 08/22] x86/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Thu, 25 Sep 2014 11:14:18 +0800 Message-ID: <1411614872-4009-9-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.542382FF.0049,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c4e39c14b6c3ae43a9c1f63abab913d5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 42792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wangyijing@huawei.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/x86/include/asm/pci.h | 1 + arch/x86/kernel/apic/io_apic.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 0892ea0..878a06d 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -101,6 +101,7 @@ void native_teardown_msi_irq(unsigned int irq); void native_restore_msi_irqs(struct pci_dev *dev); int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, unsigned int irq_base, unsigned int irq_offset); +extern struct msi_chip *x86_msi_chip; #else #define native_setup_msi_irqs NULL #define native_teardown_msi_irq NULL diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 2a2ec28..882b95e 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -3337,6 +3337,18 @@ int default_setup_hpet_msi(unsigned int irq, unsigned int id) } #endif +struct msi_chip apic_msi_chip = { + .setup_irqs = native_setup_msi_irqs, + .teardown_irq = native_teardown_msi_irq, +}; + +struct msi_chip *arch_find_msi_chip(struct pci_dev *dev) +{ + return x86_msi_chip; +} + +struct msi_chip *x86_msi_chip = &apic_msi_chip; + #endif /* CONFIG_PCI_MSI */ /* * Hypertransport interrupt support -- 1.7.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga03-in.huawei.com ([119.145.14.66]:65342 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009732AbaIYCxRrMloY (ORCPT ); Thu, 25 Sep 2014 04:53:17 +0200 From: Yijing Wang Subject: [PATCH v2 08/22] x86/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Thu, 25 Sep 2014 11:14:18 +0800 Message-ID: <1411614872-4009-9-git-send-email-wangyijing@huawei.com> In-Reply-To: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Hu , Wuyun , linux-arm-kernel@lists.infradead.org, Russell King , linux-arch@vger.kernel.org, arnab.basu@freescale.com, Bharat.Bhushan@freescale.com, x86@kernel.org, Arnd Bergmann , Thomas Gleixner , Konrad Rzeszutek Wilk , xen-devel@lists.xenproject.org, Joerg Roedel , iommu@lists.linux-foundation.org, linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Sebastian Ott , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , Sergei Shtylyov , Michael Ellerman , Thierry Reding , Thomas Petazzoni , Yijing Wang Message-ID: <20140925031418.znA7WMGfdeD830f1iGVF9C9fP6P7SmP_laYtGw0Js0k@z> Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/x86/include/asm/pci.h | 1 + arch/x86/kernel/apic/io_apic.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 0892ea0..878a06d 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -101,6 +101,7 @@ void native_teardown_msi_irq(unsigned int irq); void native_restore_msi_irqs(struct pci_dev *dev); int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, unsigned int irq_base, unsigned int irq_offset); +extern struct msi_chip *x86_msi_chip; #else #define native_setup_msi_irqs NULL #define native_teardown_msi_irq NULL diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 2a2ec28..882b95e 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -3337,6 +3337,18 @@ int default_setup_hpet_msi(unsigned int irq, unsigned int id) } #endif +struct msi_chip apic_msi_chip = { + .setup_irqs = native_setup_msi_irqs, + .teardown_irq = native_teardown_msi_irq, +}; + +struct msi_chip *arch_find_msi_chip(struct pci_dev *dev) +{ + return x86_msi_chip; +} + +struct msi_chip *x86_msi_chip = &apic_msi_chip; + #endif /* CONFIG_PCI_MSI */ /* * Hypertransport interrupt support -- 1.7.1