From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Jun 2015 12:16:36 +0200 (CEST) Received: from smtpbg298.qq.com ([184.105.67.102]:49322 "EHLO smtpbg298.qq.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27008377AbbFQKO3Pb4lp (ORCPT ); Wed, 17 Jun 2015 12:14:29 +0200 X-QQ-mid: bizesmtp4t1434536029t317t318 Received: from software.domain.org (unknown [222.92.8.142]) by esmtp4.qq.com (ESMTP) with id ; Wed, 17 Jun 2015 18:13:48 +0800 (CST) X-QQ-SSF: 01100000002000F0F642000A0000000 X-QQ-FEAT: r8geFCKg7nZsy5JGJixvDrpl8j2/Yoag4gT2b74ApiL52B/3iN/mEBMKll8JU SD2TQwrsla40PbxWsV0394eIUnEhGkza5ZR11sdYmZyVTS6V2UucKf2RNxnvpWiAB2evXgt XO+qimywxpUSh9mEvXoRcEkywBCWcanr/GPiXnSTBJcut2kcRYPw83h65Nvxdsrzdhq0VD0 02MKMzMBZg4xfUui+yIOZPsTw1r8eojeKyrCNx4dns5Ew5jhz5Uwq X-QQ-GoodBg: 0 From: Binbin Zhou To: Ralf Baechle Cc: John Crispin , "Steven J. Hill" , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Kelvin Cheung , Binbin Zhou , Chunbo Cui , Huacai Chen Subject: [PATCH v2 1/8] MIPS: Loongson: Add basic Loongson-1A CPU support Date: Wed, 17 Jun 2015 18:32:39 +0800 Message-Id: <1434537166-5385-2-git-send-email-zhoubb@lemote.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1434537166-5385-1-git-send-email-zhoubb@lemote.com> References: <1434537166-5385-1-git-send-email-zhoubb@lemote.com> X-QQ-SENDSIZE: 520 X-QQ-FName: 2F7B4A94B76D49F38895F0CB8F428CF6 X-QQ-LocalIP: 127.0.0.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 47958 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhoubb@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips The Loongson 1A is similar with Loongson 1B, which is a 32-bit SoC. It implements the MIPS32 release 2 instruction set. They share the same PRID, so we rewrite the PRID_REV_LOONGSON1B to PRID_REV_LOONGSON1A_1B, and use their CPU macros to distinguish. Signed-off-by: Chunbo Cui Signed-off-by: Binbin Zhou Signed-off-by: Huacai Chen --- arch/mips/include/asm/cpu-type.h | 3 ++- arch/mips/include/asm/cpu.h | 2 +- arch/mips/kernel/cpu-probe.c | 6 +++++- arch/mips/loongson32/Platform | 1 + arch/mips/loongson32/common/setup.c | 6 +++++- arch/mips/mm/c-r4k.c | 7 +++++++ 6 files changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index d41e8e2..b05908c 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -24,7 +24,8 @@ static inline int __pure __get_cpu_type(const int cpu_type) case CPU_LOONGSON3: #endif -#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B +#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1A) || \ + defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) case CPU_LOONGSON1: #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index e46e406..a868441 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -233,7 +233,7 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 -#define PRID_REV_LOONGSON1B 0x0020 +#define PRID_REV_LOONGSON1A_1B 0x0020 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 #define PRID_REV_LOONGSON3A 0x0005 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index dbe0792..fa5c33e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1006,8 +1006,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_LOONGSON1; switch (c->processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: + case PRID_REV_LOONGSON1A_1B: +#ifdef CONFIG_CPU_LOONGSON1A + __cpu_name[cpu] = "Loongson 1A"; +#else __cpu_name[cpu] = "Loongson 1B"; +#endif break; } diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform index ebb6dc2..e114c85 100644 --- a/arch/mips/loongson32/Platform +++ b/arch/mips/loongson32/Platform @@ -4,4 +4,5 @@ cflags-$(CONFIG_CPU_LOONGSON1) += \ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32 +load-$(CONFIG_LOONGSON1_LS1A) += 0xffffffff80200000 load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000 diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c index 62f41af..c3d2036 100644 --- a/arch/mips/loongson32/common/setup.c +++ b/arch/mips/loongson32/common/setup.c @@ -21,8 +21,12 @@ const char *get_system_type(void) unsigned int processor_id = (¤t_cpu_data)->processor_id; switch (processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: + case PRID_REV_LOONGSON1A_1B: +#ifdef CONFIG_CPU_LOONGSON1A + return "LOONGSON LS1A"; +#else return "LOONGSON LS1B"; +#endif default: return "LOONGSON (unknown)"; } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 7f660dc..cec179f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1277,6 +1277,13 @@ static void probe_pcache(void) c->dcache.flags |= MIPS_CACHE_PINDEX; break; } + case CPU_LOONGSON1: + if ((read_c0_config7() & (1 << 16))) { + /* effectively physically indexed dcache, + thus no virtual aliases. */ + c->dcache.flags |= MIPS_CACHE_PINDEX; + break; + } default: if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) c->dcache.flags |= MIPS_CACHE_ALIASES; -- 1.9.0