From: Huacai Chen <chenhc@lemote.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: John Crispin <john@phrozen.org>,
"Steven J . Hill" <Steven.Hill@cavium.com>,
linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>,
Huacai Chen <chenhc@lemote.com>
Subject: [PATCH 1/8] MIPS: Loongson-3: Enable Store Fill Buffer at runtime
Date: Thu, 10 Aug 2017 10:00:26 +0800 [thread overview]
Message-ID: <1502330433-16670-2-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1502330433-16670-1-git-send-email-chenhc@lemote.com>
New Loongson-3 (Loongson-3A R2, Loongson-3A R3, and newer) has SFB
(Store Fill Buffer) which can improve the performance of memory access.
Now, SFB enablement is controlled by CONFIG_LOONGSON3_ENHANCEMENT, and
the generic kernel has no benefit from SFB (even it is running on a new
Loongson-3 machine). With this patch, we can enable SFB at runtime by
detecting the CPU type (the expense is war_io_reorder_wmb() will always
be a 'sync', which will hurt the performance of old Loongson-3).
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/io.h | 2 +-
.../asm/mach-loongson64/kernel-entry-init.h | 38 +++++++++++++---------
arch/mips/include/asm/mipsregs.h | 2 ++
3 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index ecabc00..d3e38af 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -304,7 +304,7 @@ static inline void iounmap(const volatile void __iomem *addr)
#undef __IS_KSEG1
}
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
#define war_io_reorder_wmb() wmb()
#else
#define war_io_reorder_wmb() do { } while (0)
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index 8393bc54..4b7f58a 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -19,19 +19,22 @@
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
- mfc0 t0, $16, 3
+ mfc0 t0, CP0_CONFIG3
or t0, (0x1 << 7)
- mtc0 t0, $16, 3
+ mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
- mfc0 t0, $5, 1
+ mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
- mtc0 t0, $5, 1
-#ifdef CONFIG_LOONGSON3_ENHANCEMENT
+ mtc0 t0, CP0_PAGEGRAIN
/* Enable STFill Buffer */
- mfc0 t0, $16, 6
+ mfc0 t0, CP0_PRID
+ andi t0, 0xffff
+ slti t0, 0x6308
+ bnez t0, 1f
+ mfc0 t0, CP0_CONFIG6
or t0, 0x100
- mtc0 t0, $16, 6
-#endif
+ mtc0 t0, CP0_CONFIG6
+1:
_ehb
.set pop
#endif
@@ -45,19 +48,22 @@
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
- mfc0 t0, $16, 3
+ mfc0 t0, CP0_CONFIG3
or t0, (0x1 << 7)
- mtc0 t0, $16, 3
+ mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
- mfc0 t0, $5, 1
+ mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
- mtc0 t0, $5, 1
-#ifdef CONFIG_LOONGSON3_ENHANCEMENT
+ mtc0 t0, CP0_PAGEGRAIN
/* Enable STFill Buffer */
- mfc0 t0, $16, 6
+ mfc0 t0, CP0_PRID
+ andi t0, 0xffff
+ slti t0, 0x6308
+ bnez t0, 1f
+ mfc0 t0, CP0_CONFIG6
or t0, 0x100
- mtc0 t0, $16, 6
-#endif
+ mtc0 t0, CP0_CONFIG6
+1:
_ehb
.set pop
#endif
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index dbb0ece..cb1ebc6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -50,6 +50,7 @@
#define CP0_CONF $3
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
+#define CP0_PAGEGRAIN $5, 1
#define CP0_SEGCTL0 $5, 2
#define CP0_SEGCTL1 $5, 3
#define CP0_SEGCTL2 $5, 4
@@ -76,6 +77,7 @@
#define CP0_CONFIG $16
#define CP0_CONFIG3 $16, 3
#define CP0_CONFIG5 $16, 5
+#define CP0_CONFIG6 $16, 6
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
#define CP0_WATCHHI $19
--
2.7.0
next prev parent reply other threads:[~2017-08-10 2:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-10 2:00 [PATCH 0/8] MIPS: Loongson: new features and improvements Huacai Chen
2017-08-10 2:00 ` Huacai Chen [this message]
2018-01-24 20:54 ` [PATCH 1/8] MIPS: Loongson-3: Enable Store Fill Buffer at runtime James Hogan
2017-08-10 2:04 ` [PATCH 2/8] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2017-08-10 2:04 ` [PATCH 3/8] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
2018-01-24 21:47 ` James Hogan
2017-08-10 2:04 ` [PATCH 4/8] MIPS: Add __cpu_full_name[] to make CPU names more human-readable Huacai Chen
2018-01-24 22:14 ` James Hogan
2017-08-10 2:04 ` [PATCH 5/8] MIPS: Align kernel load address to 64KB Huacai Chen
2017-08-10 2:04 ` [PATCH 6/8] MIPS: Loongson: Add kexec/kdump support Huacai Chen
2018-01-24 21:22 ` [PATCH 2/8] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 James Hogan
2017-08-10 2:15 ` [PATCH 7/8] MIPS: Loongson: Make CPUFreq usable " Huacai Chen
2017-08-10 2:15 ` [PATCH 8/8] MIPS: Loongson: Introduce and use WAR_LLSC_MB Huacai Chen
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