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[108.223.40.66]) by smtp.gmail.com with ESMTPSA id q68sm23492071pfb.104.2018.02.12.14.37.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Feb 2018 14:37:03 -0800 (PST) From: Guenter Roeck To: James Hogan Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Guenter Roeck Subject: [RFC PATCH] MIPS: Provide cmpxchg64 for 32-bit builds Date: Mon, 12 Feb 2018 14:37:01 -0800 Message-Id: <1518475021-3337-1-git-send-email-linux@roeck-us.net> X-Mailer: git-send-email 2.7.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 62507 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux@roeck-us.net Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Since commit 60f481b970386 ("i40e: change flags to use 64 bits"), the i40e driver uses cmpxchg64(). This causes mips:allmodconfig builds to fail with drivers/net/ethernet/intel/i40e/i40e_ethtool.c: In function 'i40e_set_priv_flags': drivers/net/ethernet/intel/i40e/i40e_ethtool.c:4443:2: error: implicit declaration of function 'cmpxchg64' Implement a poor-mans-version of cmpxchg64() to fix the problem for 32-bit mips builds. The code is derived from sparc32, but only uses a single spinlock. Fixes: 60f481b970386 ("i40e: change flags to use 64 bits") Signed-off-by: Guenter Roeck --- Compile-tested only. arch/mips/include/asm/cmpxchg.h | 3 +++ arch/mips/kernel/cmpxchg.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 89e9fb7976fe..9f7b1df95b99 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -206,6 +206,9 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) #ifndef CONFIG_SMP #define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n)) +#else +u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new); +#define cmpxchg64(ptr, old, new) __cmpxchg_u64(ptr, old, new) #endif #endif diff --git a/arch/mips/kernel/cmpxchg.c b/arch/mips/kernel/cmpxchg.c index 0b9535bc2c53..30216beb2334 100644 --- a/arch/mips/kernel/cmpxchg.c +++ b/arch/mips/kernel/cmpxchg.c @@ -9,6 +9,7 @@ */ #include +#include #include unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int size) @@ -107,3 +108,19 @@ unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old, return old; } } + +static DEFINE_SPINLOCK(cmpxchg_lock); + +u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new) +{ + unsigned long flags; + u64 prev; + + spin_lock_irqsave(&cmpxchg_lock, flags); + if ((prev = *ptr) == old) + *ptr = new; + spin_unlock_irqrestore(&cmpxchg_lock, flags); + + return prev; +} +EXPORT_SYMBOL(__cmpxchg_u64); -- 2.7.4