From: Stephen Boyd <sboyd@kernel.org>
To: "Benoît Monin" <benoit.monin@bootlin.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Rob Herring" <robh@kernel.org>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Théo Lebrun" <theo.lebrun@bootlin.com>,
"Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>
Cc: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
"Tawfik Bayouk" <tawfik.bayouk@mobileye.com>,
"Sari Khoury" <sari.khoury@mobileye.com>,
"Benoît Monin" <benoit.monin@bootlin.com>
Subject: Re: [PATCH 07/19] clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy
Date: Fri, 19 Sep 2025 22:14:58 -0700 [thread overview]
Message-ID: <175834529869.4354.196538790945051595@lazor> (raw)
In-Reply-To: <20250903-clk-eyeq7-v1-7-3f5024b5d6e2@bootlin.com>
Quoting Benoît Monin (2025-09-03 05:47:14)
> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> index e62ae8794d445f685156276d5135448f340fca3f..7c76658a725f9b268da2485769979e5ba213d25b 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -217,6 +217,18 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
>
> +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy(struct device *dev,
> + const char *name, const char *parent_name, unsigned long flags,
> + unsigned int mult, unsigned int div, unsigned long acc)
> +{
> + const struct clk_parent_data pdata = { .index = -1 };
This is wrong. We're passing parent data and also setting the parent
name with a string the original way. Do you have a parent?
> +
> + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
> + &pdata, flags, mult, div, acc,
> + CLK_FIXED_FACTOR_FIXED_ACCURACY, false);
> +}
> +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy);
There are a handful of these wrappers now. Can we have one function that
takes all possibilities and then static inline functions that call one
exported function? We can pass some structs to that function to keep
the argument count "low", so those structs live on the stack for a short
time.
> +
> struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
> struct device_node *np, const char *name, const char *fw_name,
> unsigned long flags, unsigned int mult, unsigned int div)
next prev parent reply other threads:[~2025-09-20 5:14 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-03 12:47 [PATCH 00/19] Add clock and reset support for Mobileye eyeQ7H Benoît Monin
2025-09-03 12:47 ` [PATCH 01/19] dt-bindings: soc: mobileye: rename to eyeq-olb.yaml Benoît Monin
2025-09-04 9:20 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 02/19] dt-bindings: clock: mobileye: rename to eyeq-clk.h Benoît Monin
2025-09-04 9:24 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 03/19] dt-bindings: soc: mobileye: add eyeQ7H compatibles Benoît Monin
2025-09-04 9:22 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 04/19] dt-bindings: clock: mobileye: add eyeQ7H clock indexes Benoît Monin
2025-09-04 9:23 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 05/19] dt-bindings: reset: add Mobileye eyeQ Benoît Monin
2025-09-04 9:25 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 06/19] reset: eyeq: add eyeQ7H compatibles Benoît Monin
2025-09-03 12:47 ` [PATCH 07/19] clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy Benoît Monin
2025-09-20 5:14 ` Stephen Boyd [this message]
2025-09-25 11:47 ` Benoît Monin
2025-09-03 12:47 ` [PATCH 08/19] clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS Benoît Monin
2025-09-20 5:15 ` Stephen Boyd
2025-09-25 11:51 ` Benoît Monin
2025-09-03 12:47 ` [PATCH 09/19] clk: divider: check validity of flags when a table is provided Benoît Monin
2025-09-20 5:24 ` Stephen Boyd
2025-09-25 11:55 ` Benoît Monin
2025-09-03 12:47 ` [PATCH 10/19] clk: eyeq: skip post-divisor when computing pll divisor Benoît Monin
2025-09-03 12:47 ` [PATCH 11/19] clk: eyeq: rename the parent field to parent_idx Benoît Monin
2025-09-03 12:47 ` [PATCH 12/19] clk: eyeq: lookup parent clock by name Benoît Monin
2025-09-03 12:47 ` [PATCH 13/19] clk: eyeq: prefix the PLL registers with the PLL type Benoît Monin
2025-09-03 12:47 ` [PATCH 14/19] clk: eyeq: rename the reg64 field of eqc_pll Benoît Monin
2025-09-03 12:47 ` [PATCH 15/19] clk: eyeq: add a type for the PLL Benoît Monin
2025-09-03 12:47 ` [PATCH 16/19] clk: eyeq: add two PLL types Benoît Monin
2025-09-03 12:47 ` [PATCH 17/19] clk: eyeq: add a parent field to the pll Benoît Monin
2025-09-03 12:47 ` [PATCH 18/19] clk: eyeq: add an optional clk_div_table to divider Benoît Monin
2025-09-03 12:47 ` [PATCH 19/19] clk: eyeq: add eyeQ7H compatibles Benoît Monin
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