Re: It booooooooooots!

["William J. Earl" <wje@fir.esd.sgi.com>]

Alistair Lambie writes:
 > On Apr 9, 11:38am, William J. Earl wrote:
 > > Subject: Re: It booooooooooots!
 > > Mike Shaver writes:
...
 > >  > Checking for 'wait' instruction...  unavailable.
 > > ...
 > >
 > >      This appears to be a bug.  The R5000 does have the wait instruction.
 > 
 > I don't think David ever worked on an R5000.  The only platforms were R4600 &
 > R4400...soooo, there may be some issues to be resolved.
...

     On an Indy, the R5000 and R4600 are basically equivalent, except
for the MIPS IV extensions and larger caches (32 KB versus 16 KB) on the R5000.
The R5000 does have built-in secondary cache control, which is used on the O2,
but it is not used on the Indy.  On the Indy, the R5000 uses the same off-chip
secondary cache controller as the R4600.  The wait instruction operates the
same on both processors.  The wait instruction is not really essential in any
case, since its main purpose is to save power, and the R5000 and R4600 don't
use much power anyway.