[PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Sergio Paracuellos]

Hi all!

Ralinks SoCs have a system controller node which serves as clock and reset
providers for the rest of the world. This patch series introduces clock
definitions for these SoCs. The clocks are registered in the driver using
a bunch of arrays in specific order so these definitions represent the assigned
identifier that is used when this happens so client nodes can easily use it
to specify the clock which they consume without the need of checking driver code.

DTS files which are currently on tree are not matching system controller
bindings. So all of them are updated to properly match them.

I'd like this series to go through kernel mips git tree if possible.

Thanks in advance for your time.

Changes in v3:
- Address Krzysztof comments in v2 (Thanks!):
  + Drop reset include file since what it was defined there were hardware
    constants and no binding related indexes at all.
  + Update patches for not referring to this reset removed file.

Changes in v2:
- Redo commit messages in all the patches in the series to clarify why the changes
  are needed asked by Krzysztof in v1.
  
v2 of this series:
- https://lore.kernel.org/linux-clk/20250119154447.462857-1-sergio.paracuellos@gmail.com/T/#t 

v1 of this series:
- https://lore.kernel.org/linux-clk/20250115153019.407646-1-sergio.paracuellos@gmail.com/T/#t

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (6):
  dt-bindings: clock: add clock definitions for Ralink SoCs
  mips: dts: ralink: rt2880: update system controller node and its
    consumers
  mips: dts: ralink: rt3050: update system controller node and its
    consumers
  mips: dts: ralink: rt3883: update system controller node and its
    consumers
  mips: dts: ralink: mt7620a: update system controller node and its
    consumers
  mips: dts: ralink: mt7628a: update system controller node and its
    consumers

 .../bindings/clock/mediatek,mtmips-sysc.yaml  |  11 +-
 arch/mips/boot/dts/ralink/mt7620a.dtsi        |  10 +-
 arch/mips/boot/dts/ralink/mt7628a.dtsi        |  38 +++--
 arch/mips/boot/dts/ralink/rt2880.dtsi         |  10 +-
 arch/mips/boot/dts/ralink/rt3050.dtsi         |  10 +-
 arch/mips/boot/dts/ralink/rt3883.dtsi         |  10 +-
 .../dt-bindings/clock/mediatek,mtmips-sysc.h  | 130 ++++++++++++++++++
 7 files changed, 196 insertions(+), 23 deletions(-)
 create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h

-- 
2.25.1

[PATCH v3 1/6] dt-bindings: clock: add clock definitions for Ralink SoCs

[Sergio Paracuellos]

Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350,
MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending
on these new introduced constants so consumer nodes can easily use the
correct one in DTS files matching properly what is being used in driver
code (clock IDs are implicitly used there).

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 .../bindings/clock/mediatek,mtmips-sysc.yaml  |  11 +-
 .../dt-bindings/clock/mediatek,mtmips-sysc.h  | 130 ++++++++++++++++++
 2 files changed, 140 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
index ba7ffc5b16a0..83c1803ffd16 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
@@ -18,6 +18,12 @@ description: |
   These SoCs have an XTAL from where the cpu clock is
   provided as well as derived clocks for the bus and the peripherals.
 
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
+
 properties:
   compatible:
     items:
@@ -38,7 +44,8 @@ properties:
 
   '#clock-cells':
     description:
-      The first cell indicates the clock number.
+      The first cell indicates the clock number, see [1] for available
+      clocks.
     const: 1
 
   '#reset-cells':
@@ -56,6 +63,8 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
     syscon@0 {
       compatible = "ralink,rt5350-sysc", "syscon";
       reg = <0x0 0x100>;
diff --git a/include/dt-bindings/clock/mediatek,mtmips-sysc.h b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
new file mode 100644
index 000000000000..a03335b0e077
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MTMIPS_H
+#define _DT_BINDINGS_CLK_MTMIPS_H
+
+/* Ralink RT-2880 clocks */
+
+#define RT2880_CLK_XTAL		0
+#define RT2880_CLK_CPU		1
+#define RT2880_CLK_BUS		2
+#define RT2880_CLK_TIMER	3
+#define RT2880_CLK_WATCHDOG	4
+#define RT2880_CLK_UART		5
+#define RT2880_CLK_I2C		6
+#define RT2880_CLK_UARTLITE	7
+#define RT2880_CLK_ETHERNET	8
+#define RT2880_CLK_WMAC		9
+
+/* Ralink RT-305X clocks */
+
+#define RT305X_CLK_XTAL		0
+#define RT305X_CLK_CPU		1
+#define RT305X_CLK_BUS		2
+#define RT305X_CLK_TIMER	3
+#define RT305X_CLK_WATCHDOG	4
+#define RT305X_CLK_UART		5
+#define RT305X_CLK_I2C		6
+#define RT305X_CLK_I2S		7
+#define RT305X_CLK_SPI1		8
+#define RT305X_CLK_SPI2		9
+#define RT305X_CLK_UARTLITE	10
+#define RT305X_CLK_ETHERNET	11
+#define RT305X_CLK_WMAC		12
+
+/* Ralink RT-3352 clocks */
+
+#define RT3352_CLK_XTAL		0
+#define RT3352_CLK_CPU		1
+#define RT3352_CLK_PERIPH	2
+#define RT3352_CLK_BUS		3
+#define RT3352_CLK_TIMER	4
+#define RT3352_CLK_WATCHDOG	5
+#define RT3352_CLK_UART		6
+#define RT3352_CLK_I2C		7
+#define RT3352_CLK_I2S		8
+#define RT3352_CLK_SPI1		9
+#define RT3352_CLK_SPI2		10
+#define RT3352_CLK_UARTLITE	11
+#define RT3352_CLK_ETHERNET	12
+#define RT3352_CLK_WMAC		13
+
+/* Ralink RT-3883 clocks */
+
+#define RT3883_CLK_XTAL		0
+#define RT3883_CLK_CPU		1
+#define RT3883_CLK_BUS		2
+#define RT3883_CLK_PERIPH	3
+#define RT3883_CLK_TIMER	4
+#define RT3883_CLK_WATCHDOG	5
+#define RT3883_CLK_UART		6
+#define RT3883_CLK_I2C		7
+#define RT3883_CLK_I2S		8
+#define RT3883_CLK_SPI1		9
+#define RT3883_CLK_SPI2		10
+#define RT3883_CLK_UARTLITE	11
+#define RT3883_CLK_ETHERNET	12
+#define RT3883_CLK_WMAC		13
+
+/* Ralink RT-5350 clocks */
+
+#define RT5350_CLK_XTAL		0
+#define RT5350_CLK_CPU		1
+#define RT5350_CLK_BUS		2
+#define RT5350_CLK_PERIPH	3
+#define RT5350_CLK_TIMER	4
+#define RT5350_CLK_WATCHDOG	5
+#define RT5350_CLK_UART		6
+#define RT5350_CLK_I2C		7
+#define RT5350_CLK_I2S		8
+#define RT5350_CLK_SPI1		9
+#define RT5350_CLK_SPI2		10
+#define RT5350_CLK_UARTLITE	11
+#define RT5350_CLK_ETHERNET	12
+#define RT5350_CLK_WMAC		13
+
+/* Ralink MT-7620 clocks */
+
+#define MT7620_CLK_XTAL		0
+#define MT7620_CLK_PLL		1
+#define MT7620_CLK_CPU		2
+#define MT7620_CLK_PERIPH	3
+#define MT7620_CLK_BUS		4
+#define MT7620_CLK_BBPPLL	5
+#define MT7620_CLK_SDHC		6
+#define MT7620_CLK_TIMER	7
+#define MT7620_CLK_WATCHDOG	8
+#define MT7620_CLK_UART		9
+#define MT7620_CLK_I2C		10
+#define MT7620_CLK_I2S		11
+#define MT7620_CLK_SPI1		12
+#define MT7620_CLK_SPI2		13
+#define MT7620_CLK_UARTLITE	14
+#define MT7620_CLK_MMC		15
+#define MT7620_CLK_WMAC		16
+
+/* Ralink MT-76X8 clocks */
+
+#define MT76X8_CLK_XTAL		0
+#define MT76X8_CLK_CPU		1
+#define MT76X8_CLK_BBPPLL	2
+#define MT76X8_CLK_PCMI2S	3
+#define MT76X8_CLK_PERIPH	4
+#define MT76X8_CLK_BUS		5
+#define MT76X8_CLK_SDHC		6
+#define MT76X8_CLK_TIMER	7
+#define MT76X8_CLK_WATCHDOG	8
+#define MT76X8_CLK_I2C		9
+#define MT76X8_CLK_I2S		10
+#define MT76X8_CLK_SPI1		11
+#define MT76X8_CLK_SPI2		12
+#define MT76X8_CLK_UART0	13
+#define MT76X8_CLK_UART1	14
+#define MT76X8_CLK_UART2	15
+#define MT76X8_CLK_MMC		16
+#define MT76X8_CLK_WMAC		17
+
+#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
-- 
2.25.1

Re: [PATCH v3 1/6] dt-bindings: clock: add clock definitions for Ralink SoCs

[Krzysztof Kozlowski]

On 20/01/2025 10:21, Sergio Paracuellos wrote:
> Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350,
> MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending
> on these new introduced constants so consumer nodes can easily use the
> correct one in DTS files matching properly what is being used in driver
> code (clock IDs are implicitly used there).
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 1/6] dt-bindings: clock: add clock definitions for Ralink SoCs

[Stephen Boyd]

Quoting Sergio Paracuellos (2025-01-20 01:21:41)
> Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350,
> MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending
> on these new introduced constants so consumer nodes can easily use the
> correct one in DTS files matching properly what is being used in driver
> code (clock IDs are implicitly used there).
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

[PATCH v3 2/6] mips: dts: ralink: rt2880: update system controller node and its consumers

[Sergio Paracuellos]

Current RT2880 device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/rt2880.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi
index 8fc1987d9063..1f2ea3434324 100644
--- a/arch/mips/boot/dts/ralink/rt2880.dtsi
+++ b/arch/mips/boot/dts/ralink/rt2880.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@300000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,rt2880-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,rt2880-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc RT2880_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <8>;
 
-- 
2.25.1

[PATCH v3 3/6] mips: dts: ralink: rt3050: update system controller node and its consumers

[Sergio Paracuellos]

Current RT3050 device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/rt3050.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi
index 23062333a76d..a7d9bb9bc1af 100644
--- a/arch/mips/boot/dts/ralink/rt3050.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3050.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc RT305X_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;
 
-- 
2.25.1

[PATCH v3 4/6] mips: dts: ralink: rt3883: update system controller node and its consumers

[Sergio Paracuellos]

Current RT3883 device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/rt3883.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi
index 61132cf157e5..11d111a06037 100644
--- a/arch/mips/boot/dts/ralink/rt3883.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3883.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,rt3883-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc RT3883_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;
 
-- 
2.25.1

[PATCH v3 5/6] mips: dts: ralink: mt7620a: update system controller node and its consumers

[Sergio Paracuellos]

Current MT7620A device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 1f6e5320f486..d66045948a83 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,mt7620a-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,mt7620-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc MT7620_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;
 
-- 
2.25.1

[PATCH v3 6/6] mips: dts: ralink: mt7628a: update system controller node and its consumers

[Sergio Paracuellos]

Current MT7628A device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/mt7628a.dtsi | 38 ++++++++++++++++----------
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 45a15e005cc4..309966049c56 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -1,4 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
 
 / {
 	#address-cells = <1>;
@@ -16,11 +17,6 @@ cpu@0 {
 		};
 	};
 
-	resetc: reset-controller {
-		compatible = "ralink,rt2880-reset";
-		#reset-cells = <1>;
-	};
-
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
@@ -36,9 +32,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc: system-controller@0 {
-			compatible = "ralink,mt7620a-sysc", "syscon";
+		sysc: syscon@0 {
+			compatible = "ralink,mt7628-sysc", "syscon";
 			reg = <0x0 0x60>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		pinmux: pinmux@60 {
@@ -138,7 +136,7 @@ watchdog: watchdog@100 {
 			compatible = "mediatek,mt7621-wdt";
 			reg = <0x100 0x30>;
 
-			resets = <&resetc 8>;
+			resets = <&sysc 8>;
 			reset-names = "wdt";
 
 			interrupt-parent = <&intc>;
@@ -154,7 +152,7 @@ intc: interrupt-controller@200 {
 			interrupt-controller;
 			#interrupt-cells = <1>;
 
-			resets = <&resetc 9>;
+			resets = <&sysc 9>;
 			reset-names = "intc";
 
 			interrupt-parent = <&cpuintc>;
@@ -190,7 +188,9 @@ spi: spi@b00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_spi_spi>;
 
-			resets = <&resetc 18>;
+			clocks = <&sysc MT76X8_CLK_SPI1>;
+
+			resets = <&sysc 18>;
 			reset-names = "spi";
 
 			#address-cells = <1>;
@@ -206,7 +206,9 @@ i2c: i2c@900 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_i2c_i2c>;
 
-			resets = <&resetc 16>;
+			clocks = <&sysc MT76X8_CLK_I2C>;
+
+			resets = <&sysc 16>;
 			reset-names = "i2c";
 
 			#address-cells = <1>;
@@ -222,7 +224,9 @@ uart0: uartlite@c00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_uart0_uart>;
 
-			resets = <&resetc 12>;
+			clocks = <&sysc MT76X8_CLK_UART0>;
+
+			resets = <&sysc 12>;
 			reset-names = "uart0";
 
 			interrupt-parent = <&intc>;
@@ -238,7 +242,9 @@ uart1: uart1@d00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_uart1_uart>;
 
-			resets = <&resetc 19>;
+			clocks = <&sysc MT76X8_CLK_UART1>;
+
+			resets = <&sysc 19>;
 			reset-names = "uart1";
 
 			interrupt-parent = <&intc>;
@@ -254,7 +260,9 @@ uart2: uart2@e00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_uart2_uart>;
 
-			resets = <&resetc 20>;
+			clocks = <&sysc MT76X8_CLK_UART2>;
+
+			resets = <&sysc 20>;
 			reset-names = "uart2";
 
 			interrupt-parent = <&intc>;
@@ -290,6 +298,8 @@ wmac: wmac@10300000 {
 		compatible = "mediatek,mt7628-wmac";
 		reg = <0x10300000 0x100000>;
 
+		clocks = <&sysc MT76X8_CLK_WMAC>;
+
 		interrupt-parent = <&cpuintc>;
 		interrupts = <6>;
 
-- 
2.25.1

Re: [PATCH v3 6/6] mips: dts: ralink: mt7628a: update system controller node and its consumers

[Thomas Bogendoerfer]

On Mon, Jan 20, 2025 at 10:21:46AM +0100, Sergio Paracuellos wrote:
> Current MT7628A device tree file system controller node is wrong since it is
> not matching bindings. Hence, update it to match current bindings updating
> it also to use new introduced clock constants.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  arch/mips/boot/dts/ralink/mt7628a.dtsi | 38 ++++++++++++++++----------
>  1 file changed, 24 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> index 45a15e005cc4..309966049c56 100644
> --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> @@ -1,4 +1,5 @@
>  // SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
>  
>  / {
>  	#address-cells = <1>;
> @@ -16,11 +17,6 @@ cpu@0 {
>  		};
>  	};
>  
> -	resetc: reset-controller {
> -		compatible = "ralink,rt2880-reset";
> -		#reset-cells = <1>;
> -	};
> -
>  	cpuintc: interrupt-controller {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
> @@ -36,9 +32,11 @@ palmbus@10000000 {
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  
> -		sysc: system-controller@0 {
> -			compatible = "ralink,mt7620a-sysc", "syscon";
> +		sysc: syscon@0 {
> +			compatible = "ralink,mt7628-sysc", "syscon";
>  			reg = <0x0 0x60>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
>  		};
>  
>  		pinmux: pinmux@60 {
> @@ -138,7 +136,7 @@ watchdog: watchdog@100 {
>  			compatible = "mediatek,mt7621-wdt";
>  			reg = <0x100 0x30>;
>  
> -			resets = <&resetc 8>;
> +			resets = <&sysc 8>;
>  			reset-names = "wdt";
>  
>  			interrupt-parent = <&intc>;
> @@ -154,7 +152,7 @@ intc: interrupt-controller@200 {
>  			interrupt-controller;
>  			#interrupt-cells = <1>;
>  
> -			resets = <&resetc 9>;
> +			resets = <&sysc 9>;
>  			reset-names = "intc";
>  
>  			interrupt-parent = <&cpuintc>;
> @@ -190,7 +188,9 @@ spi: spi@b00 {
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&pinmux_spi_spi>;
>  
> -			resets = <&resetc 18>;
> +			clocks = <&sysc MT76X8_CLK_SPI1>;
> +
> +			resets = <&sysc 18>;
>  			reset-names = "spi";
>  
>  			#address-cells = <1>;
> @@ -206,7 +206,9 @@ i2c: i2c@900 {
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&pinmux_i2c_i2c>;
>  
> -			resets = <&resetc 16>;
> +			clocks = <&sysc MT76X8_CLK_I2C>;
> +
> +			resets = <&sysc 16>;
>  			reset-names = "i2c";
>  
>  			#address-cells = <1>;
> @@ -222,7 +224,9 @@ uart0: uartlite@c00 {
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&pinmux_uart0_uart>;
>  
> -			resets = <&resetc 12>;
> +			clocks = <&sysc MT76X8_CLK_UART0>;
> +
> +			resets = <&sysc 12>;
>  			reset-names = "uart0";
>  
>  			interrupt-parent = <&intc>;
> @@ -238,7 +242,9 @@ uart1: uart1@d00 {
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&pinmux_uart1_uart>;
>  
> -			resets = <&resetc 19>;
> +			clocks = <&sysc MT76X8_CLK_UART1>;
> +
> +			resets = <&sysc 19>;
>  			reset-names = "uart1";
>  
>  			interrupt-parent = <&intc>;
> @@ -254,7 +260,9 @@ uart2: uart2@e00 {
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&pinmux_uart2_uart>;
>  
> -			resets = <&resetc 20>;
> +			clocks = <&sysc MT76X8_CLK_UART2>;
> +
> +			resets = <&sysc 20>;
>  			reset-names = "uart2";
>  
>  			interrupt-parent = <&intc>;
> @@ -290,6 +298,8 @@ wmac: wmac@10300000 {
>  		compatible = "mediatek,mt7628-wmac";
>  		reg = <0x10300000 0x100000>;
>  
> +		clocks = <&sysc MT76X8_CLK_WMAC>;
> +
>  		interrupt-parent = <&cpuintc>;
>  		interrupts = <6>;
>  
> -- 
> 2.25.1

I get

  DTC     arch/mips/boot/dts/ralink/vocore2.dtb
/local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/mt7628a.dtsi:275.28-284.4: ERROR (phandle_references): /usb-phy@10120000: Reference to non-existent node or label "resetc"

/local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/mt7628a.dtsi:275.28-284.4: ERROR (phandle_references): /usb-phy@10120000: Reference to non-existent node or label "resetc"

ERROR: Input tree has errors, aborting (use -f to force output)

for CONFIG_DTB_VOCORE2=y and a similair failure for CONFIG_DTB_OMEGA2P=y

I'll apply rest of the series, please send a fixed patch for mt7628a

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v3 6/6] mips: dts: ralink: mt7628a: update system controller node and its consumers

[Sergio Paracuellos]

On Fri, Feb 21, 2025 at 6:19 PM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Mon, Jan 20, 2025 at 10:21:46AM +0100, Sergio Paracuellos wrote:
> > Current MT7628A device tree file system controller node is wrong since it is
> > not matching bindings. Hence, update it to match current bindings updating
> > it also to use new introduced clock constants.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> >  arch/mips/boot/dts/ralink/mt7628a.dtsi | 38 ++++++++++++++++----------
> >  1 file changed, 24 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> > index 45a15e005cc4..309966049c56 100644
> > --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
> > +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> > @@ -1,4 +1,5 @@
> >  // SPDX-License-Identifier: GPL-2.0
> > +#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
> >
> >  / {
> >       #address-cells = <1>;
> > @@ -16,11 +17,6 @@ cpu@0 {
> >               };
> >       };
> >
> > -     resetc: reset-controller {
> > -             compatible = "ralink,rt2880-reset";
> > -             #reset-cells = <1>;
> > -     };
> > -
> >       cpuintc: interrupt-controller {
> >               #address-cells = <0>;
> >               #interrupt-cells = <1>;
> > @@ -36,9 +32,11 @@ palmbus@10000000 {
> >               #address-cells = <1>;
> >               #size-cells = <1>;
> >
> > -             sysc: system-controller@0 {
> > -                     compatible = "ralink,mt7620a-sysc", "syscon";
> > +             sysc: syscon@0 {
> > +                     compatible = "ralink,mt7628-sysc", "syscon";
> >                       reg = <0x0 0x60>;
> > +                     #clock-cells = <1>;
> > +                     #reset-cells = <1>;
> >               };
> >
> >               pinmux: pinmux@60 {
> > @@ -138,7 +136,7 @@ watchdog: watchdog@100 {
> >                       compatible = "mediatek,mt7621-wdt";
> >                       reg = <0x100 0x30>;
> >
> > -                     resets = <&resetc 8>;
> > +                     resets = <&sysc 8>;
> >                       reset-names = "wdt";
> >
> >                       interrupt-parent = <&intc>;
> > @@ -154,7 +152,7 @@ intc: interrupt-controller@200 {
> >                       interrupt-controller;
> >                       #interrupt-cells = <1>;
> >
> > -                     resets = <&resetc 9>;
> > +                     resets = <&sysc 9>;
> >                       reset-names = "intc";
> >
> >                       interrupt-parent = <&cpuintc>;
> > @@ -190,7 +188,9 @@ spi: spi@b00 {
> >                       pinctrl-names = "default";
> >                       pinctrl-0 = <&pinmux_spi_spi>;
> >
> > -                     resets = <&resetc 18>;
> > +                     clocks = <&sysc MT76X8_CLK_SPI1>;
> > +
> > +                     resets = <&sysc 18>;
> >                       reset-names = "spi";
> >
> >                       #address-cells = <1>;
> > @@ -206,7 +206,9 @@ i2c: i2c@900 {
> >                       pinctrl-names = "default";
> >                       pinctrl-0 = <&pinmux_i2c_i2c>;
> >
> > -                     resets = <&resetc 16>;
> > +                     clocks = <&sysc MT76X8_CLK_I2C>;
> > +
> > +                     resets = <&sysc 16>;
> >                       reset-names = "i2c";
> >
> >                       #address-cells = <1>;
> > @@ -222,7 +224,9 @@ uart0: uartlite@c00 {
> >                       pinctrl-names = "default";
> >                       pinctrl-0 = <&pinmux_uart0_uart>;
> >
> > -                     resets = <&resetc 12>;
> > +                     clocks = <&sysc MT76X8_CLK_UART0>;
> > +
> > +                     resets = <&sysc 12>;
> >                       reset-names = "uart0";
> >
> >                       interrupt-parent = <&intc>;
> > @@ -238,7 +242,9 @@ uart1: uart1@d00 {
> >                       pinctrl-names = "default";
> >                       pinctrl-0 = <&pinmux_uart1_uart>;
> >
> > -                     resets = <&resetc 19>;
> > +                     clocks = <&sysc MT76X8_CLK_UART1>;
> > +
> > +                     resets = <&sysc 19>;
> >                       reset-names = "uart1";
> >
> >                       interrupt-parent = <&intc>;
> > @@ -254,7 +260,9 @@ uart2: uart2@e00 {
> >                       pinctrl-names = "default";
> >                       pinctrl-0 = <&pinmux_uart2_uart>;
> >
> > -                     resets = <&resetc 20>;
> > +                     clocks = <&sysc MT76X8_CLK_UART2>;
> > +
> > +                     resets = <&sysc 20>;
> >                       reset-names = "uart2";
> >
> >                       interrupt-parent = <&intc>;
> > @@ -290,6 +298,8 @@ wmac: wmac@10300000 {
> >               compatible = "mediatek,mt7628-wmac";
> >               reg = <0x10300000 0x100000>;
> >
> > +             clocks = <&sysc MT76X8_CLK_WMAC>;
> > +
> >               interrupt-parent = <&cpuintc>;
> >               interrupts = <6>;
> >
> > --
> > 2.25.1
>
> I get
>
>   DTC     arch/mips/boot/dts/ralink/vocore2.dtb
> /local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/mt7628a.dtsi:275.28-284.4: ERROR (phandle_references): /usb-phy@10120000: Reference to non-existent node or label "resetc"
>
> /local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/mt7628a.dtsi:275.28-284.4: ERROR (phandle_references): /usb-phy@10120000: Reference to non-existent node or label "resetc"
>
> ERROR: Input tree has errors, aborting (use -f to force output)
>
> for CONFIG_DTB_VOCORE2=y and a similair failure for CONFIG_DTB_OMEGA2P=y
>
> I'll apply rest of the series, please send a fixed patch for mt7628a

Sure, thanks a lot!

Best regards,
     Sergio Paracuellos

>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Thomas Bogendoerfer]

On Fri, Feb 21, 2025 at 11:48:34AM +0100, Sergio Paracuellos wrote:
> Hi Thomas,
> 
> El El lun, 20 ene 2025 a las 10:21, Sergio Paracuellos <
> sergio.paracuellos@gmail.com> escribió:
> 
> > Hi all!
> >
> > Ralinks SoCs have a system controller node which serves as clock and reset
> > providers for the rest of the world. This patch series introduces clock
> > definitions for these SoCs. The clocks are registered in the driver using
> > a bunch of arrays in specific order so these definitions represent the
> > assigned
> > identifier that is used when this happens so client nodes can easily use it
> > to specify the clock which they consume without the need of checking
> > driver code.
> >
> > DTS files which are currently on tree are not matching system controller
> > bindings. So all of them are updated to properly match them.
> >
> > I'd like this series to go through kernel mips git tree if possible.
> >
> > Thanks in advance for your time.
> >
> > Changes in v3:
> > - Address Krzysztof comments in v2 (Thanks!):
> >   + Drop reset include file since what it was defined there were hardware
> >     constants and no binding related indexes at all.
> >   + Update patches for not referring to this reset removed file.
> 
> 
> I was expecting this series going through the mips tree.

  DTC     arch/mips/boot/dts/ralink/rt3883_eval.dtb
Error: /local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/rt3883.dtsi:2.1-9 syntax error
FATAL ERROR: Unable to parse input tree

that's what I get after applying the series building for RT3883.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Sergio Paracuellos]

Hi Thomas,

On Fri, Feb 21, 2025 at 3:05 PM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Fri, Feb 21, 2025 at 11:48:34AM +0100, Sergio Paracuellos wrote:
> > Hi Thomas,
> >
> > El El lun, 20 ene 2025 a las 10:21, Sergio Paracuellos <
> > sergio.paracuellos@gmail.com> escribió:
> >
> > > Hi all!
> > >
> > > Ralinks SoCs have a system controller node which serves as clock and reset
> > > providers for the rest of the world. This patch series introduces clock
> > > definitions for these SoCs. The clocks are registered in the driver using
> > > a bunch of arrays in specific order so these definitions represent the
> > > assigned
> > > identifier that is used when this happens so client nodes can easily use it
> > > to specify the clock which they consume without the need of checking
> > > driver code.
> > >
> > > DTS files which are currently on tree are not matching system controller
> > > bindings. So all of them are updated to properly match them.
> > >
> > > I'd like this series to go through kernel mips git tree if possible.
> > >
> > > Thanks in advance for your time.
> > >
> > > Changes in v3:
> > > - Address Krzysztof comments in v2 (Thanks!):
> > >   + Drop reset include file since what it was defined there were hardware
> > >     constants and no binding related indexes at all.
> > >   + Update patches for not referring to this reset removed file.
> >
> >
> > I was expecting this series going through the mips tree.
>
>   DTC     arch/mips/boot/dts/ralink/rt3883_eval.dtb
> Error: /local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/rt3883.dtsi:2.1-9 syntax error
> FATAL ERROR: Unable to parse input tree

Weird, it looks like dtc is not happy with the "include" line with new
definitions? Are you getting this only with rt3883? Since all the
patches are almost the same and I compile tested this before sending..
Something got corrupted? I don't have my laptop now to check but I
will recheck again on monday.

Thanks,
    Sergio Paracuellos
>
> that's what I get after applying the series building for RT3883.
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Thomas Bogendoerfer]

On Fri, Feb 21, 2025 at 03:50:09PM +0100, Sergio Paracuellos wrote:
> Hi Thomas,
> 
> On Fri, Feb 21, 2025 at 3:05 PM Thomas Bogendoerfer
> <tsbogend@alpha.franken.de> wrote:
> >
> > On Fri, Feb 21, 2025 at 11:48:34AM +0100, Sergio Paracuellos wrote:
> > > Hi Thomas,
> > >
> > > El El lun, 20 ene 2025 a las 10:21, Sergio Paracuellos <
> > > sergio.paracuellos@gmail.com> escribió:
> > >
> > > > Hi all!
> > > >
> > > > Ralinks SoCs have a system controller node which serves as clock and reset
> > > > providers for the rest of the world. This patch series introduces clock
> > > > definitions for these SoCs. The clocks are registered in the driver using
> > > > a bunch of arrays in specific order so these definitions represent the
> > > > assigned
> > > > identifier that is used when this happens so client nodes can easily use it
> > > > to specify the clock which they consume without the need of checking
> > > > driver code.
> > > >
> > > > DTS files which are currently on tree are not matching system controller
> > > > bindings. So all of them are updated to properly match them.
> > > >
> > > > I'd like this series to go through kernel mips git tree if possible.
> > > >
> > > > Thanks in advance for your time.
> > > >
> > > > Changes in v3:
> > > > - Address Krzysztof comments in v2 (Thanks!):
> > > >   + Drop reset include file since what it was defined there were hardware
> > > >     constants and no binding related indexes at all.
> > > >   + Update patches for not referring to this reset removed file.
> > >
> > >
> > > I was expecting this series going through the mips tree.
> >
> >   DTC     arch/mips/boot/dts/ralink/rt3883_eval.dtb
> > Error: /local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/rt3883.dtsi:2.1-9 syntax error
> > FATAL ERROR: Unable to parse input tree
> 
> Weird, it looks like dtc is not happy with the "include" line with new
> definitions? Are you getting this only with rt3883? Since all the
> patches are almost the same and I compile tested this before sending..
> Something got corrupted? I don't have my laptop now to check but I
> will recheck again on monday.

rt2880_eval.dts:/include/ "rt2880.dtsi"
rt3052_eval.dts:#include "rt3050.dtsi"
rt3883_eval.dts:/include/ "rt3883.dtsi"

rt3052 works, rt2880 and rt3883 don't.

changing the /include/ to #include makes them compile.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Sergio Paracuellos]

On Fri, Feb 21, 2025 at 4:37 PM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Fri, Feb 21, 2025 at 03:50:09PM +0100, Sergio Paracuellos wrote:
> > Hi Thomas,
> >
> > On Fri, Feb 21, 2025 at 3:05 PM Thomas Bogendoerfer
> > <tsbogend@alpha.franken.de> wrote:
> > >
> > > On Fri, Feb 21, 2025 at 11:48:34AM +0100, Sergio Paracuellos wrote:
> > > > Hi Thomas,
> > > >
> > > > El El lun, 20 ene 2025 a las 10:21, Sergio Paracuellos <
> > > > sergio.paracuellos@gmail.com> escribió:
> > > >
> > > > > Hi all!
> > > > >
> > > > > Ralinks SoCs have a system controller node which serves as clock and reset
> > > > > providers for the rest of the world. This patch series introduces clock
> > > > > definitions for these SoCs. The clocks are registered in the driver using
> > > > > a bunch of arrays in specific order so these definitions represent the
> > > > > assigned
> > > > > identifier that is used when this happens so client nodes can easily use it
> > > > > to specify the clock which they consume without the need of checking
> > > > > driver code.
> > > > >
> > > > > DTS files which are currently on tree are not matching system controller
> > > > > bindings. So all of them are updated to properly match them.
> > > > >
> > > > > I'd like this series to go through kernel mips git tree if possible.
> > > > >
> > > > > Thanks in advance for your time.
> > > > >
> > > > > Changes in v3:
> > > > > - Address Krzysztof comments in v2 (Thanks!):
> > > > >   + Drop reset include file since what it was defined there were hardware
> > > > >     constants and no binding related indexes at all.
> > > > >   + Update patches for not referring to this reset removed file.
> > > >
> > > >
> > > > I was expecting this series going through the mips tree.
> > >
> > >   DTC     arch/mips/boot/dts/ralink/rt3883_eval.dtb
> > > Error: /local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/rt3883.dtsi:2.1-9 syntax error
> > > FATAL ERROR: Unable to parse input tree
> >
> > Weird, it looks like dtc is not happy with the "include" line with new
> > definitions? Are you getting this only with rt3883? Since all the
> > patches are almost the same and I compile tested this before sending..
> > Something got corrupted? I don't have my laptop now to check but I
> > will recheck again on monday.
>
> rt2880_eval.dts:/include/ "rt2880.dtsi"
> rt3052_eval.dts:#include "rt3050.dtsi"
> rt3883_eval.dts:/include/ "rt3883.dtsi"
>
> rt3052 works, rt2880 and rt3883 don't.
>
> changing the /include/ to #include makes them compile.

Mmmm...does this mean that this was broken before my patches? Since I
have not touched the files that need the replacement. So I probably
checked in the openwrt tree and missed this totally. Sorry for that.
How do you want to handle this? Should I send v4 including these
replacements? Or do you prefer to handle them directly?

Thanks again and sorry for the inconvenience.

Best regards,
     Sergio Paracuellos
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Thomas Bogendoerfer]

On Fri, Feb 21, 2025 at 05:40:34PM +0100, Sergio Paracuellos wrote:
> On Fri, Feb 21, 2025 at 4:37 PM Thomas Bogendoerfer
> <tsbogend@alpha.franken.de> wrote:
> >
> > On Fri, Feb 21, 2025 at 03:50:09PM +0100, Sergio Paracuellos wrote:
> > > Hi Thomas,
> > >
> > > On Fri, Feb 21, 2025 at 3:05 PM Thomas Bogendoerfer
> > > <tsbogend@alpha.franken.de> wrote:
> > > >
> > > > On Fri, Feb 21, 2025 at 11:48:34AM +0100, Sergio Paracuellos wrote:
> > > > > Hi Thomas,
> > > > >
> > > > > El El lun, 20 ene 2025 a las 10:21, Sergio Paracuellos <
> > > > > sergio.paracuellos@gmail.com> escribió:
> > > > >
> > > > > > Hi all!
> > > > > >
> > > > > > Ralinks SoCs have a system controller node which serves as clock and reset
> > > > > > providers for the rest of the world. This patch series introduces clock
> > > > > > definitions for these SoCs. The clocks are registered in the driver using
> > > > > > a bunch of arrays in specific order so these definitions represent the
> > > > > > assigned
> > > > > > identifier that is used when this happens so client nodes can easily use it
> > > > > > to specify the clock which they consume without the need of checking
> > > > > > driver code.
> > > > > >
> > > > > > DTS files which are currently on tree are not matching system controller
> > > > > > bindings. So all of them are updated to properly match them.
> > > > > >
> > > > > > I'd like this series to go through kernel mips git tree if possible.
> > > > > >
> > > > > > Thanks in advance for your time.
> > > > > >
> > > > > > Changes in v3:
> > > > > > - Address Krzysztof comments in v2 (Thanks!):
> > > > > >   + Drop reset include file since what it was defined there were hardware
> > > > > >     constants and no binding related indexes at all.
> > > > > >   + Update patches for not referring to this reset removed file.
> > > > >
> > > > >
> > > > > I was expecting this series going through the mips tree.
> > > >
> > > >   DTC     arch/mips/boot/dts/ralink/rt3883_eval.dtb
> > > > Error: /local/tbogendoerfer/korg/linux/arch/mips/boot/dts/ralink/rt3883.dtsi:2.1-9 syntax error
> > > > FATAL ERROR: Unable to parse input tree
> > >
> > > Weird, it looks like dtc is not happy with the "include" line with new
> > > definitions? Are you getting this only with rt3883? Since all the
> > > patches are almost the same and I compile tested this before sending..
> > > Something got corrupted? I don't have my laptop now to check but I
> > > will recheck again on monday.
> >
> > rt2880_eval.dts:/include/ "rt2880.dtsi"
> > rt3052_eval.dts:#include "rt3050.dtsi"
> > rt3883_eval.dts:/include/ "rt3883.dtsi"
> >
> > rt3052 works, rt2880 and rt3883 don't.
> >
> > changing the /include/ to #include makes them compile.
> 
> Mmmm...does this mean that this was broken before my patches? Since I
> have not touched the files that need the replacement.

no, without your patches everything compiles. I guess dtc (?) doesn't
allow #include in files, which were included via / include /. But that's
just guesswork

 So I probably
> checked in the openwrt tree and missed this totally. Sorry for that.
> How do you want to handle this? Should I send v4 including these
> replacements? Or do you prefer to handle them directly?

I'll fix the includes while applying.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v3 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Thomas Bogendoerfer]

On Mon, Jan 20, 2025 at 10:21:40AM +0100, Sergio Paracuellos wrote:
> Hi all!
> 
> Ralinks SoCs have a system controller node which serves as clock and reset
> providers for the rest of the world. This patch series introduces clock
> definitions for these SoCs. The clocks are registered in the driver using
> a bunch of arrays in specific order so these definitions represent the assigned
> identifier that is used when this happens so client nodes can easily use it
> to specify the clock which they consume without the need of checking driver code.
> 
> DTS files which are currently on tree are not matching system controller
> bindings. So all of them are updated to properly match them.
> 
> I'd like this series to go through kernel mips git tree if possible.
> 
> Thanks in advance for your time.
> 
> Changes in v3:
> - Address Krzysztof comments in v2 (Thanks!):
>   + Drop reset include file since what it was defined there were hardware
>     constants and no binding related indexes at all.
>   + Update patches for not referring to this reset removed file.
> 
> Changes in v2:
> - Redo commit messages in all the patches in the series to clarify why the changes
>   are needed asked by Krzysztof in v1.
>   
> v2 of this series:
> - https://lore.kernel.org/linux-clk/20250119154447.462857-1-sergio.paracuellos@gmail.com/T/#t 
> 
> v1 of this series:
> - https://lore.kernel.org/linux-clk/20250115153019.407646-1-sergio.paracuellos@gmail.com/T/#t
> 
> Best regards,
>     Sergio Paracuellos
> 
> Sergio Paracuellos (6):
>   dt-bindings: clock: add clock definitions for Ralink SoCs
>   mips: dts: ralink: rt2880: update system controller node and its
>     consumers
>   mips: dts: ralink: rt3050: update system controller node and its
>     consumers
>   mips: dts: ralink: rt3883: update system controller node and its
>     consumers
>   mips: dts: ralink: mt7620a: update system controller node and its
>     consumers
>   mips: dts: ralink: mt7628a: update system controller node and its
>     consumers
> 
>  .../bindings/clock/mediatek,mtmips-sysc.yaml  |  11 +-
>  arch/mips/boot/dts/ralink/mt7620a.dtsi        |  10 +-
>  arch/mips/boot/dts/ralink/mt7628a.dtsi        |  38 +++--
>  arch/mips/boot/dts/ralink/rt2880.dtsi         |  10 +-
>  arch/mips/boot/dts/ralink/rt3050.dtsi         |  10 +-
>  arch/mips/boot/dts/ralink/rt3883.dtsi         |  10 +-
>  .../dt-bindings/clock/mediatek,mtmips-sysc.h  | 130 ++++++++++++++++++
>  7 files changed, 196 insertions(+), 23 deletions(-)
>  create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h

applied patches 1-5 to mips-next

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]