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([2409:251:20c0:100:fe80:8e59:9ae1:e028]) by smtp.gmail.com with ESMTPSA id r24sm51157410pfd.120.2019.05.01.04.33.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 May 2019 04:33:27 -0700 (PDT) Subject: Re: [RFC v2 2/5] dt-bindings: clk: add document for ralink clock driver To: Stephen Boyd Cc: John Crispin , Michael Turquette , Rob Herring , Mark Rutland , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org References: <20190405000129.19331-1-drvlabo@gmail.com> <20190405000129.19331-3-drvlabo@gmail.com> <155622059236.15276.15417177789148260137@swboyd.mtv.corp.google.com> From: NOGUCHI Hiroshi Message-ID: <1fe454d3-f24e-4169-5f57-97d516a16cc8@gmail.com> Date: Wed, 1 May 2019 20:33:24 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <155622059236.15276.15417177789148260137@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On 2019/04/26 4:29, Stephen Boyd wrote: >> +Required properties: >> + - compatible: must be "ralink,rt2880-clock" >> + - #clock-cells: must be 1 >> + - ralink,sysctl: a phandle to a ralink syscon register region >> + - clock-indices: identifying number. >> + These must correspond to the bit number in CLKCFG1. > > These look like driver level details that we're putting in the DT so we > can compress the number space that consumers use. Is that right? If so, > I don't get it. Can we not use this property? I understand that the bit numbers in clock gating register are hardware resource informations. Therefore, it is not strange that they are described in DT, I think. >> + Clock consumers use one of them as #clock-cells index. >> + - clock-output-names: array of gating clocks' names >> + - clocks: array of phandles which points the parent clock >> + for gating clocks. >> + If gating clock does not need parent clock linkage, >> + we bind to dummy clock whose frequency is zero. >> + >> + >> +Example: >> + >> +/* dummy parent clock node */ >> +dummy_ck: dummy_ck { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <0>; >> +}; > > Would this ever exist in practice? If not, please remove from the > example so we don't get the wrong idea. I referred to arch/arm/boot/dts/. omap24xx-clocks.dtsi : defines dummy_ck omap2420-clocks.dtsi : refers dummy_ck In practice, There is no problem in specifying another existing clock, eg MT7620_CLK_PERIPH which is always active. >> + >> +clkctrl: clkctrl { >> + compatible = "ralink,rt2880-clock"; >> + #clock-cells = <1>; >> + ralink,sysctl = <&sysc>; >> + >> + clock-indices = >> + <12>, >> + <16>, <17>, <18>, <19>, >> + <20>, >> + <26>; >> + clock-output-names = >> + "uart0", >> + "i2c", "i2s", "spi", "uart1", >> + "uart2", >> + "pcie0"; >> + clocks = >> + <&pll MT7620_CLK_PERIPH>, >> + <&pll MT7620_CLK_PERIPH>, <&pll MT7620_CLK_PCMI2S>, <&pll MT7620_CLK_SYS>, <&pll MT7620_CLK_PERIPH>, >> + <&pll MT7620_CLK_PERIPH>, >> + <&dummy_ck>; >> + }; >> +}; >> + >> +/* consumer which refers "uart0" clock */ >> +uart0: uartlite@c00 { >> + compatible = "ns16550a"; >> + reg = <0xc00 0x100>; >> + >> + clocks = <&clkctrl 12>; > > So 12 matches in indices and then that is really "uart0" clk? > >> + clock-names = "uart0"; >> + That is right. rt2880-clock driver is implemented to let clock cell indices match indcies in "clock-indices" property.