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Date: Thu, 4 Oct 2001 10:24:08 -0700
From: Richard Henderson <rth@twiddle.net>
To: Jakub Jelinek <jakub@redhat.com>
Cc: Kjeld Borch Egevang <kjelde@mips.com>, "H . J . Lu" <hjl@lucon.org>,
   GNU C Library <libc-alpha@sourceware.cygnus.com>,
   linux-mips mailing list <linux-mips@oss.sgi.com>
Subject: Re: PATCH: Update sysdeps/mips/fpu/libm-test-ulps
Message-ID: <20011004102408.A11412@twiddle.net>
References: <20010914111751.A17316@lucon.org> <Pine.LNX.4.30.0110011106360.16270-100000@coplin19.mips.com> <20011001121053.F3251@sunsite.ms.mff.cuni.cz>
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In-Reply-To: <20011001121053.F3251@sunsite.ms.mff.cuni.cz>; from jakub@redhat.com on Mon, Oct 01, 2001 at 12:10:53PM +0200
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On Mon, Oct 01, 2001 at 12:10:53PM +0200, Jakub Jelinek wrote:
> The way soft-fp interprets Quiet NaNs is not just Intel-way, e.g. SPARC,
> Alpha work the same way. E.g. on SPARC, signalling NaN is exp=max,
> f=.0xxxxxxxxxx...xxx where at least one of the x bits is set, quiet NaN is
> exp=max, f=.1xxxxxxxxxx...xxxxxx.
> If MIPS has it backwards,

Yes indeed.  From the Mips32 spec I have handy:

Unbiased E    f    s b1    Value V    Typical Single Bit Pattern
E_max+1	    != 0   x 1     SNaN        16#7fffffff 
E_max+1     != 0   x 0     QNaN        16#7fbfffff


r~