From: Ralf Baechle <ralf@oss.sgi.com>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: Petko Manolov <pmanolov@lnxw.com>, linux-mips@oss.sgi.com
Subject: Re: Malta probs
Date: Wed, 24 Oct 2001 18:56:44 +0200 [thread overview]
Message-ID: <20011024185644.A3025@dea.linux-mips.net> (raw)
In-Reply-To: <004501c15cab$88055b60$0deca8c0@Ulysses>; from kevink@mips.com on Wed, Oct 24, 2001 at 06:47:10PM +0200
On Wed, Oct 24, 2001 at 06:47:10PM +0200, Kevin D. Kissell wrote:
> A clue - a machine check exception results
> when there are two identical values in the
> TLB, which is unhealthy for associative RAM
> arrays (never mind that synthesized MIPS
> 4K and 5K cores may or may not actually
> have associative RAM for the TLB). In the
> 4K cores, this condition results even if the
> two identical values are non-Valid, which was
> not true in the R4000 and R5000 CPUs, and
> which necessitated a tweak to the TLB flush
> and invaldate routines to ensure that each entry
> is written with a unique invalid value (a function
> of the index).
>
> Please double-check that the TLB flush
> code that you are using does this.
I fixed this problem already last night.
Ralf
prev parent reply other threads:[~2001-10-24 16:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200110230102.f9N12kb20443@oss.sgi.com>
[not found] ` <3BD5D236.8D0CE33C@lnxw.com>
2001-10-23 20:47 ` Malta probs Ralf Baechle
2001-10-23 21:30 ` Petko Manolov
2001-10-24 0:43 ` Ralf Baechle
2001-10-24 13:07 ` Atsushi Nemoto
2001-10-24 19:45 ` Petko Manolov
2001-10-24 23:13 ` Ralf Baechle
2001-10-24 16:47 ` Kevin D. Kissell
2001-10-24 16:47 ` Kevin D. Kissell
2001-10-24 16:56 ` Ralf Baechle [this message]
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