Toshiba TX3927 board boot problem.

Toshiba TX3927 board boot problem.

[8route]

Dear all:
  Hi!
  I'm working on Toshiba TX3927 RISC Processor Reference board.During 
development I met a problem.Can someone give me some good suggestions?
  Let me describe the problem in details:
  TX3927 board cann't boot up via NFS.It will halt at 
  ==================================
  VFS: Mounted root (NFS filesystem).
  Freeing unused kernel memory: 44k freed 
  ========================================
and the reset switch on the TX3927 board cann't work anymore.
The kernel is linux-2.2.13-20000211.tar.bz2 with Toshiba TX3927 patch,
the NFS root file system is declinuxroot-990611.tgz.
I've checked /var/log/messages and find sentence like this:
   authenticated mount request from 192.168.255.202...
so I think NFS file system works well.Can someone give me some 
good suggestions to solve this problem?

These are serial port output: 
=============================
Toshiba Bootloader for TX RISC Reference Kit Ver 000.10
Copyright (c) 1999, 2000 TOSHIBA Corporation  
TX3927JMR/JMI TX3927 Rev ( 0) CPU Clk 133Mhz, BUS Clk  66Mhz
Slot [0] : MEM Base = 0x80040000, MEM Size = 0x00fc0000
FlashROM BFC00000 - BFFFFFFF
Find Toshiba TX3927 PCI Controller.
Find Toshiba TC35815 100Mbps Ethernet Controller.
MON> info
TX3927JMR/JMI TX3927 Rev ( 0) CPU Clk 133Mhz, BUS Clk  66Mhz
Slot [0] : MEM Base = 0x80040000, MEM Size = 0x00fc0000
Chip Config TX3927 [ccfg]  = 0004303b
Pin  Config TX3927 [pcfg]  = 0ffc7101
SDCCR0 Reg TX3927 [sdccr0] = 000300e8
SDCCR1 Reg TX3927 [sdccr1] = 00000000
SDCCR2 Reg TX3927 [sdccr2] = 00000000
SDCCR3 Reg TX3927 [sdccr3] = 00000000
SDCCR4 Reg TX3927 [sdccr4] = 00000000
SDCCR5 Reg TX3927 [sdccr5] = 00000000
SDCCR6 Reg TX3927 [sdccr6] = 00000000
SDCCR7 Reg TX3927 [sdccr7] = 00000000
SDCTR1 Reg TX3927 [sdctr1] = 08010400
SDCTR2 Reg TX3927 [sdctr2] = 000000ff
SDCTR3 Reg TX3927 [sdctr3] = 02020000
SDCCMD Reg TX3927 [sdccmd] = 20100031
RCCR 0 Reg TX3927 [rccr0]  = 1fc35208
RCCR 1 Reg TX3927 [rccr1]  = 00000000
RCCR 2 Reg TX3927 [rccr2]  = 140064c8
RCCR 3 Reg TX3927 [rccr3]  = 1003f698
RCCR 4 Reg TX3927 [rccr4]  = 00000000
RCCR 5 Reg TX3927 [rccr5]  = 00000000
RCCR 6 Reg TX3927 [rccr6]  = 00000000
RCCR 7 Reg TX3927 [rccr7]  = 00000000
Port 0. dbg 1.onbrd [serp] =        0
Baud Rate           [baud] =    38400
Init exec cmd 1 [icmd1] = 
Init exec cmd 2 [icmd2] = 
Init exec cmd 3 [icmd3] = 
Init exec cmd 4 [icmd4] = 
cmdline [cmdl] = root=/dev/nfs rw ip=::::::rarp console=ttyS0 
nfsroot=192.168.255.8:/work/nfsroot 
MON> br
initialize TC35815 [100Mbps Ethernet].
tc35815 base address (0xa4000000)
Link Speed : 100Mbps
initialize TC35815 completion.
Booting...: Using Reverse ARP.
Ethernet address 00:00:39:04:F8:14
IP address 192.168.255.202 = C0A8FFCA
Booting TFTP server from 192.168.255.8 = C0A8FF08
kernel file : C0A8FFCA ...
Downloaded 1126720 (  113140) bytes at a0080000 from TFTP server.
Default:root=/dev/nfs rw ip=::::::rarp console=ttyS0 
nfsroot=192.168.255.8:/work/nfsroot 
boot:
Loading R[23]00 MMU routines.
CPU revision is: 00002240
config reg = 001a0030
Instruction cache 8kb, linesize 16byte
Data cache 4kb, linesize 16byte
Linux version 2.2.13 (root@desktop) (gcc version egcs-2.90.29 980515 (egcs-1.0.3 
release)) #1 Tue Oct 23 09:45:59 HKT 2001
Toshiba Reference System Setup
TX3927 133Mhz
Initialize TX3927 PCI Controller.
Calibrating delay loop... 105.68 BogoMIPS
Memory: 14476k/16380k available (980k kernel code, 408k data)
Checking for 'wait' instruction...  unavailable.
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
Linux NET4.0 for Linux 2.2
Based upon Swansea University Computer Society NET3.039
NET4: Unix domain sockets 1.0 for Linux NET4.0.
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
Starting kswapd v 1.5 
setup_machine_info:Cpu typtx39_initialize: cflags set to 77
TX39 UART driver version 0.04
loop: registered device at major 7
initialize TC35815 [100Mbps Ethernet].
TC35815 : at 0xa4000000 IRQ:3
Link Speed : 100Mbps
ADDR: 00:00:39:04:f8:14 
initialize TC35815 completion.
Sending RARP requests..... OK
IP-Config: Got RARP answer from 192.168.255.8, my address is 192.168.255.202
IP-Config: Guessing netmask 255.255.255.0
Looking up port of RPC 100003/2 on 192.168.255.8
Looking up port of RPC 100005/1 on 192.168.255.8
VFS: Mounted root (NFS filesystem).
Freeing unused kernel memory: 44k freed
========================================

Regards,
8route

Re: Toshiba TX3927 board boot problem.

[Atsushi Nemoto]

>>>>> On Fri, 26 Oct 2001 17:49:26 +0800, 8route <ajob4me@21cn.com> said:
ajob4me>   I'm working on Toshiba TX3927 RISC Processor Reference
ajob4me> board.During development I met a problem.Can someone give me
ajob4me> some good suggestions?
...
ajob4me> and the reset switch on the TX3927 board cann't work anymore.

I have seen TX39 dead on "cfc1" insturuction if STATUS.CU1 bit
enabled.  Such codes were in arch/mips/kernel/process.c.

---
Atsushi Nemoto

Re: Toshiba TX3927 board boot problem.

[Atsushi Nemoto]

>>>>> On Fri, 26 Oct 2001 22:58:06 +0900 (JST), Atsushi Nemoto <nemoto@toshiba-tops.co.jp> said:
nemoto> I have seen TX39 dead on "cfc1" insturuction if STATUS.CU1 bit
nemoto> enabled.  Such codes were in arch/mips/kernel/process.c.

So, please apply this patch to CVS for TX39XX support.

I use CONFIG_CPU_TX39XX in this patch, but I suppose other FPU-less
CPUs may need this also.

Does anybody know how about on other CPUs?

diff -u linux-sgi-cvs/arch/mips/kernel/process.c linux.new/arch/mips/kernel/
--- linux-sgi-cvs/arch/mips/kernel/process.c	Mon Oct 22 10:29:56 2001
+++ linux.new/arch/mips/kernel/process.c	Mon Oct 29 15:49:37 2001
@@ -57,6 +57,12 @@
 {
 	/* Forget lazy fpu state */
 	if (last_task_used_math == current) {
+#ifdef CONFIG_CPU_TX39XX
+		if (!(mips_cpu.options & MIPS_CPU_FPU)) {
+			last_task_used_math = NULL;
+			return;
+		}
+#endif
 		set_cp0_status(ST0_CU1);
 		__asm__ __volatile__("cfc1\t$0,$31");
 		last_task_used_math = NULL;
@@ -67,6 +73,12 @@
 {
 	/* Forget lazy fpu state */
 	if (last_task_used_math == current) {
+#ifdef CONFIG_CPU_TX39XX
+		if (!(mips_cpu.options & MIPS_CPU_FPU)) {
+			last_task_used_math = NULL;
+			return;
+		}
+#endif
 		set_cp0_status(ST0_CU1);
 		__asm__ __volatile__("cfc1\t$0,$31");
 		last_task_used_math = NULL;
---
Atsushi Nemoto

Re: Toshiba TX3927 board boot problem.

[Carsten Langgaard]

This doesn't look right, you still need to enable the CU1 bit in the status register to let the FP
emulator kick-in.
FPU-less CPUs should take a coprocessor unusable exception on any floating-point instructions.
I have been running this on several FPU-less CPUs, and it works fine for me.

Actually there is a problem with this code on CPUs, which have a FPU. The problem is that a lot of
CPUs have a CP0 hazard of 4 nops, between setting the CU1 bit in the status register and executing
the first floating point instruction thereafter. It probably only a performance issue, because if
the setting of CU1 hasn't taken effect yet, then we get a coprocessor unusable exception and the
the exception handler will also set the CU1 bit.

/Carsten

Atsushi Nemoto wrote:

> >>>>> On Fri, 26 Oct 2001 22:58:06 +0900 (JST), Atsushi Nemoto <nemoto@toshiba-tops.co.jp> said:
> nemoto> I have seen TX39 dead on "cfc1" insturuction if STATUS.CU1 bit
> nemoto> enabled.  Such codes were in arch/mips/kernel/process.c.
>
> So, please apply this patch to CVS for TX39XX support.
>
> I use CONFIG_CPU_TX39XX in this patch, but I suppose other FPU-less
> CPUs may need this also.
>
> Does anybody know how about on other CPUs?
>
> diff -u linux-sgi-cvs/arch/mips/kernel/process.c linux.new/arch/mips/kernel/
> --- linux-sgi-cvs/arch/mips/kernel/process.c    Mon Oct 22 10:29:56 2001
> +++ linux.new/arch/mips/kernel/process.c        Mon Oct 29 15:49:37 2001
> @@ -57,6 +57,12 @@
>  {
>         /* Forget lazy fpu state */
>         if (last_task_used_math == current) {
> +#ifdef CONFIG_CPU_TX39XX
> +               if (!(mips_cpu.options & MIPS_CPU_FPU)) {
> +                       last_task_used_math = NULL;
> +                       return;
> +               }
> +#endif
>                 set_cp0_status(ST0_CU1);
>                 __asm__ __volatile__("cfc1\t$0,$31");
>                 last_task_used_math = NULL;
> @@ -67,6 +73,12 @@
>  {
>         /* Forget lazy fpu state */
>         if (last_task_used_math == current) {
> +#ifdef CONFIG_CPU_TX39XX
> +               if (!(mips_cpu.options & MIPS_CPU_FPU)) {
> +                       last_task_used_math = NULL;
> +                       return;
> +               }
> +#endif
>                 set_cp0_status(ST0_CU1);
>                 __asm__ __volatile__("cfc1\t$0,$31");
>                 last_task_used_math = NULL;
> ---
> Atsushi Nemoto

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com

Re: Toshiba TX3927 board boot problem.

[Alice Hennessy]

Carsten Langgaard wrote:

> This doesn't look right, you still need to enable the CU1 bit in the status register to let the FP
> emulator kick-in.
> FPU-less CPUs should take a coprocessor unusable exception on any floating-point instructions.
> I have been running this on several FPU-less CPUs, and it works fine for me.

Maybe the FPU-less CPUs you have been using define the CU1 bit as reserved
or is unused (ignore on write, zero on read)? The TX3927 actually allows the setting of the CU1 bit.
Have you seen
a case where you need to set the CU1 bit for the emulation to kick-in?   I would think that the CU1
bit should
never be set to one for FPU-less CPUs.

Alice

>
>
> Actually there is a problem with this code on CPUs, which have a FPU. The problem is that a lot of
> CPUs have a CP0 hazard of 4 nops, between setting the CU1 bit in the status register and executing
> the first floating point instruction thereafter. It probably only a performance issue, because if
> the setting of CU1 hasn't taken effect yet, then we get a coprocessor unusable exception and the
> the exception handler will also set the CU1 bit.
>
> /Carsten
>
> Atsushi Nemoto wrote:
>
> > >>>>> On Fri, 26 Oct 2001 22:58:06 +0900 (JST), Atsushi Nemoto <nemoto@toshiba-tops.co.jp> said:
> > nemoto> I have seen TX39 dead on "cfc1" insturuction if STATUS.CU1 bit
> > nemoto> enabled.  Such codes were in arch/mips/kernel/process.c.
> >
> > So, please apply this patch to CVS for TX39XX support.
> >
> > I use CONFIG_CPU_TX39XX in this patch, but I suppose other FPU-less
> > CPUs may need this also.
> >
> > Does anybody know how about on other CPUs?
> >
> > diff -u linux-sgi-cvs/arch/mips/kernel/process.c linux.new/arch/mips/kernel/
> > --- linux-sgi-cvs/arch/mips/kernel/process.c    Mon Oct 22 10:29:56 2001
> > +++ linux.new/arch/mips/kernel/process.c        Mon Oct 29 15:49:37 2001
> > @@ -57,6 +57,12 @@
> >  {
> >         /* Forget lazy fpu state */
> >         if (last_task_used_math == current) {
> > +#ifdef CONFIG_CPU_TX39XX
> > +               if (!(mips_cpu.options & MIPS_CPU_FPU)) {
> > +                       last_task_used_math = NULL;
> > +                       return;
> > +               }
> > +#endif
> >                 set_cp0_status(ST0_CU1);
> >                 __asm__ __volatile__("cfc1\t$0,$31");
> >                 last_task_used_math = NULL;
> > @@ -67,6 +73,12 @@
> >  {
> >         /* Forget lazy fpu state */
> >         if (last_task_used_math == current) {
> > +#ifdef CONFIG_CPU_TX39XX
> > +               if (!(mips_cpu.options & MIPS_CPU_FPU)) {
> > +                       last_task_used_math = NULL;
> > +                       return;
> > +               }
> > +#endif
> >                 set_cp0_status(ST0_CU1);
> >                 __asm__ __volatile__("cfc1\t$0,$31");
> >                 last_task_used_math = NULL;
> > ---
> > Atsushi Nemoto
>
> --
> _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark             http://www.mips.com

Re: Toshiba TX3927 board boot problem.

[Ralf Baechle]

On Mon, Oct 29, 2001 at 04:17:23PM -0800, Alice Hennessy wrote:

> > This doesn't look right, you still need to enable the CU1 bit in the
> > status register to let the FP emulator kick-in.  FPU-less CPUs should
> > take a coprocessor unusable exception on any floating-point instructions.
> > I have been running this on several FPU-less CPUs, and it works fine for
> me.
> 
> Maybe the FPU-less CPUs you have been using define the CU1 bit as reserved
> or is unused (ignore on write, zero on read)? The TX3927 actually allows
> the setting of the CU1 bit.  Have you seen a case where you need to set
> the CU1 bit for the emulation to kick-in?   I would think that the CU1
> bit should never be set to one for FPU-less CPUs.

There are subtle differences in how CUx bits for unimplemented coprocessors
are handled in the various processors.  MIPS32 and MIPS64 specifies the
behaviour as 0 on read, writes ignored; previous processors such as the
R4000 handled this differently and as a consequence a fp instruction on
a fpu-less r4000 class cpu may either throw a CU or a reserved instruction
exception.  To make things easier for everybody this is documented in the
R10000 user's manual ...

  Ralf

Re: Toshiba TX3927 board boot problem.

[Alice Hennessy]

Ralf Baechle wrote:

> On Mon, Oct 29, 2001 at 04:17:23PM -0800, Alice Hennessy wrote:
>
> > > This doesn't look right, you still need to enable the CU1 bit in the
> > > status register to let the FP emulator kick-in.  FPU-less CPUs should
> > > take a coprocessor unusable exception on any floating-point instructions.
> > > I have been running this on several FPU-less CPUs, and it works fine for
> > me.
> >
> > Maybe the FPU-less CPUs you have been using define the CU1 bit as reserved
> > or is unused (ignore on write, zero on read)? The TX3927 actually allows
> > the setting of the CU1 bit.  Have you seen a case where you need to set
> > the CU1 bit for the emulation to kick-in?   I would think that the CU1
> > bit should never be set to one for FPU-less CPUs.
>
> There are subtle differences in how CUx bits for unimplemented coprocessors
> are handled in the various processors.  MIPS32 and MIPS64 specifies the
> behaviour as 0 on read, writes ignored; previous processors such as the
> R4000 handled this differently and as a consequence a fp instruction on
> a fpu-less r4000 class cpu may either throw a CU or a reserved instruction
> exception.  To make things easier for everybody this is documented in the
> R10000 user's manual ...
>
>   Ralf

So,  we should not set CU1 generically for FPU-less CPUs especially since a
known problem exists
for the tx3927?  Ie, qualify all setting of CU1 as follows:

if (mips_cpu.options & MIPS_CPU_FPU)
                   set_cp0_status(ST0_CU1);


Alice

Re: Toshiba TX3927 board boot problem.

[Atsushi Nemoto]

>>>>> On Mon, 29 Oct 2001 16:17:23 -0800, Alice Hennessy <ahennessy@mvista.com> said:
ahennessy> I would think that the CU1 bit should never be set to one
ahennessy> for FPU-less CPUs.

I think so too.

Talking about TX3927, When I tried, TX3927 did NOT raise any exception
on cp1 instruction if CU1 bit enabled.  The CPU just locked there.  So
some workaround is necessary for TX3927.

---
Atsushi Nemoto

Re: Toshiba TX3927 board boot problem.

[Carsten Langgaard]

Alice Hennessy wrote:

> Carsten Langgaard wrote:
>
> > This doesn't look right, you still need to enable the CU1 bit in the status register to let the FP
> > emulator kick-in.
> > FPU-less CPUs should take a coprocessor unusable exception on any floating-point instructions.
> > I have been running this on several FPU-less CPUs, and it works fine for me.
>
> Maybe the FPU-less CPUs you have been using define the CU1 bit as reserved
> or is unused (ignore on write, zero on read)? The TX3927 actually allows the setting of the CU1 bit.
> Have you seen
> a case where you need to set the CU1 bit for the emulation to kick-in?   I would think that the CU1
> bit should
> never be set to one for FPU-less CPUs.

You are right, you don't need to set the CU1 bit for the emulator to kick-in (you just need a
coprocessor unusable exception), sorry my mistake.
So generally I think we should use the check against a FPU present (mips_cpu.options & MIPS_CPU_FPU),
instead of the TX39XX specific fix.

>
> Alice
>
> >
> >
> > Actually there is a problem with this code on CPUs, which have a FPU. The problem is that a lot of
> > CPUs have a CP0 hazard of 4 nops, between setting the CU1 bit in the status register and executing
> > the first floating point instruction thereafter. It probably only a performance issue, because if
> > the setting of CU1 hasn't taken effect yet, then we get a coprocessor unusable exception and the
> > the exception handler will also set the CU1 bit.
> >
> > /Carsten
> >
> > Atsushi Nemoto wrote:
> >
> > > >>>>> On Fri, 26 Oct 2001 22:58:06 +0900 (JST), Atsushi Nemoto <nemoto@toshiba-tops.co.jp> said:
> > > nemoto> I have seen TX39 dead on "cfc1" insturuction if STATUS.CU1 bit
> > > nemoto> enabled.  Such codes were in arch/mips/kernel/process.c.
> > >
> > > So, please apply this patch to CVS for TX39XX support.
> > >
> > > I use CONFIG_CPU_TX39XX in this patch, but I suppose other FPU-less
> > > CPUs may need this also.
> > >
> > > Does anybody know how about on other CPUs?
> > >
> > > diff -u linux-sgi-cvs/arch/mips/kernel/process.c linux.new/arch/mips/kernel/
> > > --- linux-sgi-cvs/arch/mips/kernel/process.c    Mon Oct 22 10:29:56 2001
> > > +++ linux.new/arch/mips/kernel/process.c        Mon Oct 29 15:49:37 2001
> > > @@ -57,6 +57,12 @@
> > >  {
> > >         /* Forget lazy fpu state */
> > >         if (last_task_used_math == current) {
> > > +#ifdef CONFIG_CPU_TX39XX
> > > +               if (!(mips_cpu.options & MIPS_CPU_FPU)) {
> > > +                       last_task_used_math = NULL;
> > > +                       return;
> > > +               }
> > > +#endif
> > >                 set_cp0_status(ST0_CU1);
> > >                 __asm__ __volatile__("cfc1\t$0,$31");
> > >                 last_task_used_math = NULL;
> > > @@ -67,6 +73,12 @@
> > >  {
> > >         /* Forget lazy fpu state */
> > >         if (last_task_used_math == current) {
> > > +#ifdef CONFIG_CPU_TX39XX
> > > +               if (!(mips_cpu.options & MIPS_CPU_FPU)) {
> > > +                       last_task_used_math = NULL;
> > > +                       return;
> > > +               }
> > > +#endif
> > >                 set_cp0_status(ST0_CU1);
> > >                 __asm__ __volatile__("cfc1\t$0,$31");
> > >                 last_task_used_math = NULL;
> > > ---
> > > Atsushi Nemoto
> >
> > --
> > _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >                    Denmark            http://www.mips.com

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com

Re: Toshiba TX3927 board boot problem.

[Carsten Langgaard]

Alice Hennessy wrote:

> Ralf Baechle wrote:
>
> > On Mon, Oct 29, 2001 at 04:17:23PM -0800, Alice Hennessy wrote:
> >
> > > > This doesn't look right, you still need to enable the CU1 bit in the
> > > > status register to let the FP emulator kick-in.  FPU-less CPUs should
> > > > take a coprocessor unusable exception on any floating-point instructions.
> > > > I have been running this on several FPU-less CPUs, and it works fine for
> > > me.
> > >
> > > Maybe the FPU-less CPUs you have been using define the CU1 bit as reserved
> > > or is unused (ignore on write, zero on read)? The TX3927 actually allows
> > > the setting of the CU1 bit.  Have you seen a case where you need to set
> > > the CU1 bit for the emulation to kick-in?   I would think that the CU1
> > > bit should never be set to one for FPU-less CPUs.
> >
> > There are subtle differences in how CUx bits for unimplemented coprocessors
> > are handled in the various processors.  MIPS32 and MIPS64 specifies the
> > behaviour as 0 on read, writes ignored; previous processors such as the
> > R4000 handled this differently and as a consequence a fp instruction on
> > a fpu-less r4000 class cpu may either throw a CU or a reserved instruction
> > exception.  To make things easier for everybody this is documented in the
> > R10000 user's manual ...
> >
> >   Ralf
>
> So,  we should not set CU1 generically for FPU-less CPUs especially since a
> known problem exists
> for the tx3927?  Ie, qualify all setting of CU1 as follows:
>
> if (mips_cpu.options & MIPS_CPU_FPU)
>                    set_cp0_status(ST0_CU1);

And while we are at it, could we handle the CP0 hazard of 4 nops, between setting
the CU1 bit in the status register and executing
the first floating point instruction, on CPU which got a FPU.

>
>
> Alice

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com

Re: Toshiba TX3927 board boot problem.

[Ralf Baechle]

On Tue, Oct 30, 2001 at 09:36:01AM +0100, Carsten Langgaard wrote:

> > So,  we should not set CU1 generically for FPU-less CPUs especially since a
> > known problem exists
> > for the tx3927?  Ie, qualify all setting of CU1 as follows:
> >
> > if (mips_cpu.options & MIPS_CPU_FPU)
> >                    set_cp0_status(ST0_CU1);
> 
> And while we are at it, could we handle the CP0 hazard of 4 nops, between
> setting the CU1 bit in the status register and executing
> the first floating point instruction, on CPU which got a FPU.

Which CPUs actually need four nops?

Just working on a patch; I found a bunch more place where we were playing
with the CU1 bit.

  Ralf

Re: Toshiba TX3927 board boot problem.

[Carsten Langgaard]

Ralf Baechle wrote:

> On Tue, Oct 30, 2001 at 09:36:01AM +0100, Carsten Langgaard wrote:
>
> > > So,  we should not set CU1 generically for FPU-less CPUs especially since a
> > > known problem exists
> > > for the tx3927?  Ie, qualify all setting of CU1 as follows:
> > >
> > > if (mips_cpu.options & MIPS_CPU_FPU)
> > >                    set_cp0_status(ST0_CU1);
> >
> > And while we are at it, could we handle the CP0 hazard of 4 nops, between
> > setting the CU1 bit in the status register and executing
> > the first floating point instruction, on CPU which got a FPU.
>
> Which CPUs actually need four nops?
>
> Just working on a patch; I found a bunch more place where we were playing
> with the CU1 bit.

The MIPS32 spec specify 4 nops.

>
>   Ralf

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
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  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
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Re: Toshiba TX3927 board boot problem.

[Ralf Baechle]

On Tue, Oct 30, 2001 at 09:20:04AM +0100, Carsten Langgaard wrote:

> You are right, you don't need to set the CU1 bit for the emulator to kick-in
> (you just need a coprocessor unusable exception), sorry my mistake.
> So generally I think we should use the check against a FPU present
> (mips_cpu.options & MIPS_CPU_FPU), instead of the TX39XX specific fix.

So here is a preliminiary version of my patch.  Still untested and needs
to be applied to mips64 also.

  Ralf

Index: arch/mips/kernel/process.c
===================================================================
RCS file: /home/pub/cvs/linux/arch/mips/kernel/process.c,v
retrieving revision 1.31
diff -u -r1.31 process.c
--- arch/mips/kernel/process.c 2001/10/19 01:23:37 1.31  
+++ arch/mips/kernel/process.c 2001/10/30 14:46:30   
@@ -56,8 +56,8 @@
 void exit_thread(void)
 {
 	/* Forget lazy fpu state */
-	if (last_task_used_math == current) {
-		set_cp0_status(ST0_CU1);
+	if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
+		__enable_fpu();
 		__asm__ __volatile__("cfc1\t$0,$31");
 		last_task_used_math = NULL;
 	}
@@ -66,8 +66,8 @@
 void flush_thread(void)
 {
 	/* Forget lazy fpu state */
-	if (last_task_used_math == current) {
-		set_cp0_status(ST0_CU1);
+	if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
+		__enable_fpu();
 		__asm__ __volatile__("cfc1\t$0,$31");
 		last_task_used_math = NULL;
 	}
@@ -85,7 +85,7 @@
 
 	if (last_task_used_math == current)
 		if (mips_cpu.options & MIPS_CPU_FPU) {
-			set_cp0_status(ST0_CU1);
+			__enable_fpu();
 			save_fp(p);
 		}
 	/* set up new TSS. */
Index: arch/mips/kernel/ptrace.c
===================================================================
RCS file: /home/pub/cvs/linux/arch/mips/kernel/ptrace.c,v
retrieving revision 1.32
diff -u -r1.32 ptrace.c
--- arch/mips/kernel/ptrace.c 2001/10/19 01:23:37 1.32  
+++ arch/mips/kernel/ptrace.c 2001/10/30 14:46:30   
@@ -20,7 +20,6 @@
 #include <linux/smp_lock.h>
 #include <linux/user.h>
 
-#include <asm/fp.h>
 #include <asm/mipsregs.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -126,9 +125,9 @@
 						child->thread.fpu.soft.regs;
 				} else 
 					if (last_task_used_math == child) {
-						enable_cp1();
+						__enable_fpu();
 						save_fp(child);
-						disable_cp1();
+						__disable_fpu();
 						last_task_used_math = NULL;
 						regs->cp0_status &= ~ST0_CU1;
 					}
@@ -174,8 +173,13 @@
 		case FPC_EIR: {	/* implementation / version register */
 			unsigned int flags;
 
+			if (!(mips_cpu.options & MIPS_CPU_FPU)) {
+				res = -EIO;
+				goto out;
+			}
+
 			__save_flags(flags);
-			enable_cp1();
+			__enable_fpu();
 			__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 			__restore_flags(flags);
 			break;
@@ -217,9 +221,9 @@
 						fregs = (unsigned long long *)
 						child->thread.fpu.soft.regs;
 					} else {
-						enable_cp1();
+						__enable_fpu();
 						save_fp(child);
-						disable_cp1();
+						__disable_fpu();
 						last_task_used_math = NULL;
 						regs->cp0_status &= ~ST0_CU1;
 					}
Index: arch/mips/kernel/signal.c
===================================================================
RCS file: /home/pub/cvs/linux/arch/mips/kernel/signal.c,v
retrieving revision 1.37
diff -u -r1.37 signal.c
--- arch/mips/kernel/signal.c 2001/10/19 01:23:37 1.37  
+++ arch/mips/kernel/signal.c 2001/10/30 14:46:30   
@@ -22,6 +22,7 @@
 
 #include <asm/asm.h>
 #include <asm/bitops.h>
+#include <asm/cpu.h>
 #include <asm/pgalloc.h>
 #include <asm/stackframe.h>
 #include <asm/uaccess.h>
@@ -355,7 +356,7 @@
 	err |= __put_user(owned_fp, &sc->sc_ownedfp);
 
 	if (current->used_math) {	/* fp is active.  */
-		set_cp0_status(ST0_CU1);
+		enable_fpu();
 		err |= save_fp_context(sc);
 		last_task_used_math = NULL;
 		regs->cp0_status &= ~ST0_CU1;
Index: arch/mips64/kernel/ptrace.c
===================================================================
RCS file: /home/pub/cvs/linux/arch/mips64/kernel/ptrace.c,v
retrieving revision 1.12
diff -u -r1.12 ptrace.c
--- arch/mips64/kernel/ptrace.c 2001/10/27 00:49:55 1.12  
+++ arch/mips64/kernel/ptrace.c 2001/10/30 14:46:33   
@@ -119,9 +119,9 @@
 
 #ifndef CONFIG_SMP
 				if (last_task_used_math == child) {
-					set_cp0_status(ST0_CU1);
+					__enable_fpu();
 					save_fp(child);
-					clear_cp0_status(ST0_CU1, 0);
+					__disable_fpu();
 					last_task_used_math = NULL;
 				}
 #endif
@@ -197,9 +197,9 @@
 			if (child->used_math) {
 #ifndef CONFIG_SMP
 				if (last_task_used_math == child) {
-					set_cp0_status(ST0_CU1);
+					__enable_fpu();
 					save_fp(child);
-					clear_cp0_status(ST0_CU1);
+					__disable_fpu(ST0_CU1);
 					last_task_used_math = NULL;
 					regs->cp0_status &= ~ST0_CU1;
 				}
Index: include/asm-mips/bootinfo.h
===================================================================
RCS file: /home/pub/cvs/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.37
diff -u -r1.37 bootinfo.h
--- include/asm-mips/bootinfo.h 2001/10/24 23:00:44 1.37  
+++ include/asm-mips/bootinfo.h 2001/10/30 14:46:46   
@@ -298,7 +298,6 @@
  * values in setup.c (or whereever suitable) so they are in
  * .data section
  */
-extern struct mips_cpu mips_cpu;
 extern unsigned long mips_machtype;
 extern unsigned long mips_machgroup;
 extern unsigned long mips_tlb_entries;
Index: include/asm-mips/cpu.h
===================================================================
RCS file: /home/pub/cvs/linux/include/asm-mips/cpu.h,v
retrieving revision 1.16
diff -u -r1.16 cpu.h
--- include/asm-mips/cpu.h 2001/10/26 21:28:47 1.16  
+++ include/asm-mips/cpu.h 2001/10/30 14:46:46   
@@ -111,6 +111,8 @@
 	struct cache_desc tcache;	/* Tertiary/split secondary cache */
 };
 
+extern struct mips_cpu mips_cpu;
+
 #endif
 
 /*
Index: include/asm-mips/fp.h
===================================================================
RCS file: fp.h
diff -N fp.h
--- include/asm-mips/fp.h Tue Oct 30 15:48:07 2001
+++ include/asm-mips/fp.h Tue May 5 22:32:27 1998
@@ -1,33 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 by Ralf Baechle
- */
-
-/*
- * Activate and deactive the floatingpoint accelerator.
- */
-#define enable_cp1()							\
-	__asm__ __volatile__(						\
-		".set\tpush\n\t"					\
-		".set\tnoat\n\t"					\
-		".set\treorder\n\t"					\
-		"mfc0\t$1,$12\n\t"					\
-		"or\t$1,%0\n\t"						\
-		"mtc0\t$1,$12\n\t"					\
-		".set\tpop"						\
-		: : "r" (ST0_CU1));
-
-#define disable_cp1()							\
-	__asm__ __volatile__(						\
-		".set\tpush\n\t"					\
-		".set\tnoat\n\t"					\
-		".set\treorder\n\t"					\
-		"mfc0\t$1,$12\n\t"					\
-		"or\t$1,%0\n\t"						\
-		"xor\t$1,%0\n\t"					\
-		"mtc0\t$1,$12\n\t"					\
-		".set\tpop"						\
-		: : "r" (ST0_CU1));
Index: include/asm-mips/mipsregs.h
===================================================================
RCS file: /home/pub/cvs/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.26
diff -u -r1.26 mipsregs.h
--- include/asm-mips/mipsregs.h 2001/10/27 00:49:55 1.26  
+++ include/asm-mips/mipsregs.h 2001/10/30 14:46:46   
@@ -148,12 +148,15 @@
  */
 #include <linux/config.h>
 #ifdef CONFIG_CPU_VR41XX
+
 #define PM_1K   0x00000000
 #define PM_4K   0x00001800
 #define PM_16K  0x00007800
 #define PM_64K  0x0001f800
 #define PM_256K 0x0007f800
+
 #else
+
 #define PM_4K   0x00000000
 #define PM_16K  0x00006000
 #define PM_64K  0x0001e000
@@ -161,6 +164,7 @@
 #define PM_1M   0x001fe000
 #define PM_4M   0x007fe000
 #define PM_16M  0x01ffe000
+
 #endif
 
 /*
@@ -175,75 +179,6 @@
 #define PL_16M  24
 
 /*
- * Macros to access the system control coprocessor
- */
-#define read_32bit_cp0_register(source)                         \
-({ int __res;                                                   \
-        __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
-        "mfc0\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
-        : "=r" (__res));                                        \
-        __res;})
-
-#define read_32bit_cp0_set1_register(source)                    \
-({ int __res;                                                   \
-        __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
-        "cfc0\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
-        : "=r" (__res));                                        \
-        __res;})
-
-/*
- * For now use this only with interrupts disabled!
- */
-#define read_64bit_cp0_register(source)                         \
-({ int __res;                                                   \
-        __asm__ __volatile__(                                   \
-        ".set\tmips3\n\t"                                       \
-        "dmfc0\t%0,"STR(source)"\n\t"                           \
-        ".set\tmips0"                                           \
-        : "=r" (__res));                                        \
-        __res;})
-
-#define write_32bit_cp0_register(register,value)                \
-        __asm__ __volatile__(                                   \
-        "mtc0\t%0,"STR(register)"\n\t"				\
-	"nop"							\
-        : : "r" (value));
-
-#define write_32bit_cp0_set1_register(register,value)           \
-        __asm__ __volatile__(                                   \
-        "ctc0\t%0,"STR(register)"\n\t"				\
-	"nop"							\
-        : : "r" (value));
-
-#define write_64bit_cp0_register(register,value)                \
-        __asm__ __volatile__(                                   \
-        ".set\tmips3\n\t"                                       \
-        "dmtc0\t%0,"STR(register)"\n\t"                         \
-        ".set\tmips0"                                           \
-        : : "r" (value))
-
-/* 
- * This should be changed when we get a compiler that support the MIPS32 ISA. 
- */
-#define read_mips32_cp0_config1()                               \
-({ int __res;                                                   \
-        __asm__ __volatile__(                                   \
-	".set\tnoreorder\n\t"                                   \
-	".set\tnoat\n\t"                                        \
-     	".word\t0x40018001\n\t"                                 \
-	"move\t%0,$1\n\t"                                       \
-	".set\tat\n\t"                                          \
-	".set\treorder"                                         \
-	:"=r" (__res));                                         \
-        __res;})
-
-/*
  * R4x00 interrupt enable / cause bits
  */
 #define IE_SW0          (1<< 8)
@@ -267,55 +202,6 @@
 #define C_IRQ4          (1<<14)
 #define C_IRQ5          (1<<15)
 
-#ifndef _LANGUAGE_ASSEMBLY
-/*
- * Manipulate the status register.
- * Mostly used to access the interrupt bits.
- */
-#define __BUILD_SET_CP0(name,register)				\
-extern inline unsigned int					\
-set_cp0_##name(unsigned int set)				\
-{								\
-	unsigned int res;					\
-								\
-	res = read_32bit_cp0_register(register);		\
-	res |= set;						\
-	write_32bit_cp0_register(register, res);		\
-								\
-	return res;						\
-}								\
-								\
-extern inline unsigned int					\
-clear_cp0_##name(unsigned int clear)				\
-{								\
-	unsigned int res;					\
-								\
-	res = read_32bit_cp0_register(register);		\
-	res &= ~clear;						\
-	write_32bit_cp0_register(register, res);		\
-								\
-	return res;						\
-}								\
-								\
-extern inline unsigned int					\
-change_cp0_##name(unsigned int change, unsigned int new)	\
-{								\
-	unsigned int res;					\
-								\
-	res = read_32bit_cp0_register(register);		\
-	res &= ~change;						\
-	res |= (new & change);					\
-	write_32bit_cp0_register(register, res);		\
-								\
-	return res;						\
-}
-
-__BUILD_SET_CP0(status,CP0_STATUS)
-__BUILD_SET_CP0(cause,CP0_CAUSE)
-__BUILD_SET_CP0(config,CP0_CONFIG)
-
-#endif /* defined (_LANGUAGE_ASSEMBLY) */
-
 /*
  * Bitfields in the R4xx0 cp0 status register
  */
@@ -547,5 +433,440 @@
 #define CEB_SUPERVISOR	4	/* Count events in supvervisor mode EXL = ERL = 0 */
 #define CEB_KERNEL	2	/* Count events in kernel mode EXL = ERL = 0 */
 #define CEB_EXL		1	/* Count events with EXL = 1, ERL = 0 */
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source)                         \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "mfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
+#define read_32bit_cp0_set1_register(source)                    \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "cfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
+/*
+ * For now use this only with interrupts disabled!
+ */
+#define read_64bit_cp0_register(source)                         \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+        ".set\tmips3\n\t"                                       \
+        "dmfc0\t%0,"STR(source)"\n\t"                           \
+        ".set\tmips0"                                           \
+        : "=r" (__res));                                        \
+        __res;})
+
+#define write_32bit_cp0_register(register,value)                \
+        __asm__ __volatile__(                                   \
+        "mtc0\t%0,"STR(register)"\n\t"				\
+	"nop"							\
+        : : "r" (value));
+
+#define write_32bit_cp0_set1_register(register,value)           \
+        __asm__ __volatile__(                                   \
+        "ctc0\t%0,"STR(register)"\n\t"				\
+	"nop"							\
+        : : "r" (value));
+
+#define write_64bit_cp0_register(register,value)                \
+        __asm__ __volatile__(                                   \
+        ".set\tmips3\n\t"                                       \
+        "dmtc0\t%0,"STR(register)"\n\t"                         \
+        ".set\tmips0"                                           \
+        : : "r" (value))
+
+/* 
+ * This should be changed when we get a compiler that support the MIPS32 ISA. 
+ */
+#define read_mips32_cp0_config1()                               \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tnoreorder\n\t"                                   \
+	".set\tnoat\n\t"                                        \
+     	".word\t0x40018001\n\t"                                 \
+	"move\t%0,$1\n\t"                                       \
+	".set\tat\n\t"                                          \
+	".set\treorder"                                         \
+	:"=r" (__res));                                         \
+        __res;})
+
+/* TLB operations. */
+static inline void tlb_probe(void)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"tlbp\n\t"
+		".set pop");
+}
+
+static inline void tlb_read(void)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"tlbr\n\t"
+		".set pop");
+}
+
+static inline void tlb_write_indexed(void)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"tlbwi\n\t"
+		".set pop");
+}
+
+static inline void tlb_write_random(void)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"tlbwr\n\t"
+		".set pop");
+}
+
+/* Dealing with various CP0 mmu/cache related registers. */
+
+
+static inline unsigned long get_pagemask(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $5\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+static inline void set_pagemask(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $5\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
+static inline unsigned long get_entrylo0(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(	
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $2\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+static inline void set_entrylo0(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $2\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+static inline unsigned long get_entrylo1(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $3\n\t"
+		".set pop" : "=r" (val));
+
+	return val;
+}
+
+static inline void set_entrylo1(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $3\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+/* CP0_ENTRYHI register */
+static inline unsigned long get_entryhi(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $10\n\t"
+		".set pop"
+		: "=r" (val));
+
+	return val;
+}
+
+static inline void set_entryhi(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $10\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+/* CP0_INDEX register */
+static inline unsigned long get_index(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $0\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+static inline void set_index(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $0\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+/* CP0_WIRED register */
+static inline unsigned long get_wired(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $6\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+static inline void set_wired(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $6\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+/* CP0_STATUS register */
+static inline unsigned int get_status(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $12\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+static inline void set_status(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $12\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+static inline unsigned long get_info(void)
+{
+	unsigned long val;
+
+	__asm__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $7\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+/* CP0_TAGLO and CP0_TAGHI registers */
+static inline unsigned long get_taglo(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $28\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+static inline void set_taglo(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $28\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+static inline unsigned long get_taghi(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $29\n\t"
+		".set pop"
+		: "=r" (val));
+	return val;
+}
+
+static inline void set_taghi(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $29\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+/* CP0_CONTEXT register */
+static inline unsigned long get_context(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $4\n\t"
+		".set pop"
+		: "=r" (val));
+
+	return val;
+}
+
+static inline void set_context(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $4\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
+/*
+ * Manipulate the status register.
+ * Mostly used to access the interrupt bits.
+ */
+#define __BUILD_SET_CP0(name,register)				\
+static inline unsigned int					\
+set_cp0_##name(unsigned int set)				\
+{								\
+	unsigned int res;					\
+								\
+	res = read_32bit_cp0_register(register);		\
+	res |= set;						\
+	write_32bit_cp0_register(register, res);		\
+								\
+	return res;						\
+}								\
+								\
+static inline unsigned int					\
+clear_cp0_##name(unsigned int clear)				\
+{								\
+	unsigned int res;					\
+								\
+	res = read_32bit_cp0_register(register);		\
+	res &= ~clear;						\
+	write_32bit_cp0_register(register, res);		\
+								\
+	return res;						\
+}								\
+								\
+static inline unsigned int					\
+change_cp0_##name(unsigned int change, unsigned int new)	\
+{								\
+	unsigned int res;					\
+								\
+	res = read_32bit_cp0_register(register);		\
+	res &= ~change;						\
+	res |= (new & change);					\
+	write_32bit_cp0_register(register, res);		\
+								\
+	return res;						\
+}
+
+__BUILD_SET_CP0(status,CP0_STATUS)
+__BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(config,CP0_CONFIG)
+
+#define __enable_fpu()							\
+do {									\
+	set_cp0_status(ST0_CU1);					\
+	asm("nop;nop;nop;nop");		/* max. hazard */		\
+} while (0)
+
+#define __disable_fpu()							\
+do {									\
+	clear_cp0_status(ST0_CU1);					\
+	/* We don't care about the cp0 hazard here  */			\
+} while (0)
+
+#define enable_fpu()							\
+do {									\
+	if (mips_cpu.options & MIPS_CPU_FPU)				\
+		__enable_fpu();						\
+} while (0)
+
+#define disable_fpu()							\
+do {									\
+	if (mips_cpu.options & MIPS_CPU_FPU)				\
+		__disable_fpu();					\
+} while (0)
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 #endif /* _ASM_MIPSREGS_H */
Index: include/asm-mips/pgtable.h
===================================================================
RCS file: /home/pub/cvs/linux/include/asm-mips/pgtable.h,v
retrieving revision 1.60
diff -u -r1.60 pgtable.h
--- include/asm-mips/pgtable.h 2001/10/24 23:00:44 1.60  
+++ include/asm-mips/pgtable.h 2001/10/30 14:46:46   
@@ -507,274 +507,6 @@
 #define PageSkip(page)		(0)
 #define kern_addr_valid(addr)	(1)
 
-/* TLB operations. */
-extern inline void tlb_probe(void)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"tlbp\n\t"
-		".set pop");
-}
-
-extern inline void tlb_read(void)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"tlbr\n\t"
-		".set pop");
-}
-
-extern inline void tlb_write_indexed(void)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"tlbwi\n\t"
-		".set pop");
-}
-
-extern inline void tlb_write_random(void)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"tlbwr\n\t"
-		".set pop");
-}
-
-/* Dealing with various CP0 mmu/cache related registers. */
-
-/* CP0_PAGEMASK register */
-extern inline unsigned long get_pagemask(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $5\n\t"
-		".set pop"
-		: "=r" (val));
-	return val;
-}
-
-extern inline void set_pagemask(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $5\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
-extern inline unsigned long get_entrylo0(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(	
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $2\n\t"
-		".set pop"
-		: "=r" (val));
-	return val;
-}
-
-extern inline void set_entrylo0(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $2\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-extern inline unsigned long get_entrylo1(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $3\n\t"
-		".set pop" : "=r" (val));
-
-	return val;
-}
-
-extern inline void set_entrylo1(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $3\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-/* CP0_ENTRYHI register */
-extern inline unsigned long get_entryhi(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $10\n\t"
-		".set pop"
-		: "=r" (val));
-
-	return val;
-}
-
-extern inline void set_entryhi(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $10\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-/* CP0_INDEX register */
-extern inline unsigned long get_index(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $0\n\t"
-		".set pop"
-		: "=r" (val));
-	return val;
-}
-
-extern inline void set_index(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $0\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-/* CP0_WIRED register */
-extern inline unsigned long get_wired(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $6\n\t"
-		".set pop"
-		: "=r" (val));
-	return val;
-}
-
-extern inline void set_wired(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $6\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-extern inline unsigned long get_info(void)
-{
-	unsigned long val;
-
-	__asm__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $7\n\t"
-		".set pop"
-		: "=r" (val));
-	return val;
-}
-
-/* CP0_TAGLO and CP0_TAGHI registers */
-extern inline unsigned long get_taglo(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $28\n\t"
-		".set pop"
-		: "=r" (val));
-	return val;
-}
-
-extern inline void set_taglo(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $28\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-extern inline unsigned long get_taghi(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $29\n\t"
-		".set pop"
-		: "=r" (val));
-	return val;
-}
-
-extern inline void set_taghi(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $29\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
-/* CP0_CONTEXT register */
-extern inline unsigned long get_context(void)
-{
-	unsigned long val;
-
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mfc0 %0, $4\n\t"
-		".set pop"
-		: "=r" (val));
-
-	return val;
-}
-
-extern inline void set_context(unsigned long val)
-{
-	__asm__ __volatile__(
-		".set push\n\t"
-		".set reorder\n\t"
-		"mtc0 %z0, $4\n\t"
-		".set pop"
-		: : "Jr" (val));
-}
-
 #include <asm-generic/pgtable.h>
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */

Re: Toshiba TX3927 board boot problem.

[Atsushi Nemoto]

>>>>> On Tue, 30 Oct 2001 15:55:33 +0100, Ralf Baechle <ralf@oss.sgi.com> said:
ralf> So here is a preliminiary version of my patch.  Still untested
ralf> and needs to be applied to mips64 also.

Thank you.  This patch works fine for me.

One request: with this patch, a ptrace call for FPC_EIR returns error
on FPU-less CPUs.  The call can be handled without error (as for other
FP registers).

--- /tmp/ptrace.c	Wed Oct 31 11:44:16 2001
+++ arch/mips/kernel/ptrace.c	Wed Oct 31 11:46:10 2001
@@ -174,8 +174,7 @@
 			unsigned int flags;
 
 			if (!(mips_cpu.options & MIPS_CPU_FPU)) {
-				res = -EIO;
-				goto out;
+				break;
 			}
 
 			__save_flags(flags);
---
Atsushi Nemoto

Re: Toshiba TX3927 board boot problem.

[Ralf Baechle]

On Wed, Oct 31, 2001 at 11:58:56AM +0900, Atsushi Nemoto wrote:

> ralf> So here is a preliminiary version of my patch.  Still untested
> ralf> and needs to be applied to mips64 also.
> 
> Thank you.  This patch works fine for me.
> 
> One request: with this patch, a ptrace call for FPC_EIR returns error
> on FPU-less CPUs.  The call can be handled without error (as for other
> FP registers).

I don't think there is much point in returning a version number if there is
nothing we could return a version number of.  Well, maybe the fp emulation
sw version or kernel version.  What would you consider a sensible return
value?

  Ralf

Re: Toshiba TX3927 board boot problem.

[Atsushi Nemoto]

>>>>> On Wed, 31 Oct 2001 05:06:37 +0100, Ralf Baechle <ralf@oss.sgi.com> said:
ralf> I don't think there is much point in returning a version number
ralf> if there is nothing we could return a version number of.  Well,
ralf> maybe the fp emulation sw version or kernel version.  What would
ralf> you consider a sensible return value?

The reason of my request is that user-mode gdb reports error on "info
reg" command.  "info reg" command shows fsr and fir.

So, I don't care the return value.  I think "0" is enough for FPU-less
CPUs.

---
Atsushi Nemoto

Re: Toshiba TX3927 board boot problem.

[Ralf Baechle]

On Wed, Oct 31, 2001 at 01:30:11PM +0900, Atsushi Nemoto wrote:

> >>>>> On Wed, 31 Oct 2001 05:06:37 +0100, Ralf Baechle <ralf@oss.sgi.com> said:
> ralf> I don't think there is much point in returning a version number
> ralf> if there is nothing we could return a version number of.  Well,
> ralf> maybe the fp emulation sw version or kernel version.  What would
> ralf> you consider a sensible return value?
> 
> The reason of my request is that user-mode gdb reports error on "info
> reg" command.  "info reg" command shows fsr and fir.
> 
> So, I don't care the return value.  I think "0" is enough for FPU-less
> CPUs.

Ok, applied.

  Ralf

Re: Toshiba TX3927 board boot problem.

[Daniel Jacobowitz]

On Wed, Oct 31, 2001 at 05:31:42AM +0100, Ralf Baechle wrote:
> On Wed, Oct 31, 2001 at 01:30:11PM +0900, Atsushi Nemoto wrote:
> 
> > >>>>> On Wed, 31 Oct 2001 05:06:37 +0100, Ralf Baechle <ralf@oss.sgi.com> said:
> > ralf> I don't think there is much point in returning a version number
> > ralf> if there is nothing we could return a version number of.  Well,
> > ralf> maybe the fp emulation sw version or kernel version.  What would
> > ralf> you consider a sensible return value?
> > 
> > The reason of my request is that user-mode gdb reports error on "info
> > reg" command.  "info reg" command shows fsr and fir.
> > 
> > So, I don't care the return value.  I think "0" is enough for FPU-less
> > CPUs.
> 
> Ok, applied.

Thanks; returning 0 is the best GDB can expect here.

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer