From: Jun Sun <jsun@mvista.com>
To: Jim Paris <jim@jtan.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>,
Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>,
"Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
Linux/MIPS Development <linux-mips@oss.sgi.com>
Subject: Re: ISA
Date: Tue, 1 Jan 2002 11:22:23 -0800 [thread overview]
Message-ID: <20020101112223.A14847@mvista.com> (raw)
In-Reply-To: <20011221134452.A21586@neurosis.mit.edu>; from jim@jtan.com on Fri, Dec 21, 2001 at 01:44:52PM -0500
On Fri, Dec 21, 2001 at 01:44:52PM -0500, Jim Paris wrote:
> > Interesting - I'd not considered that. Is ISA and non ISA space seperate on
> > MIPS or is it all rather ambiguous ?
>
> On my particular machine, system RAM is at 0x00000000, and ISA I/O
> memory is at 0x10000000. The driver I'm currently trying to work with
> calls check_mem_region with ISA addresses, which of course breaks when
> ISA memory isn't at zero. One suggestion was to patch the driver to
> use something like
>
> check_mem_region(virt_to_phys(ioremap(ISA_address)), ...)
>
> which might be the best way for now?
I agree with Geert and think isa_xxx_mem_region is a better approach.
Unfortunately, this requires a change in both dirver and
arch-specific part.
> I think a more generic way to
> abstract away a bus (and support multiple types and numbers of I/O
> busses) is really necessary though. Some way to register a bus with
> the kernel, and bind particular busses to particular instances of
> drivers, or something.
>
I have talked with somebody before about the address apace idea, which
is rather similar to what you are talking :
1. each address space has an id.
2. kernel pre-defines a couple of well-known ones, 0 for CPU physical,
1 for virtual, etc.
3. When drivers discover the devices, they get the address and also
the address space id where the address resides.
4. there are a set of macro's that converts/maps an address or an
address region from one space to another.
This generalized form allows multiple-PCI buses to use substractive decoding.
Also removes the 1:1 mapping requirement between PCI memory space and
CPU physical address space.
However, the detailed implementation can be hairy, which is why it
is still an idea. :-)
Jun
next prev parent reply other threads:[~2002-01-01 20:23 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-12-18 20:04 ISA Jim Paris
2001-12-18 20:27 ` ISA Bradley D. LaRonde
2001-12-18 20:27 ` ISA Bradley D. LaRonde
2001-12-18 21:44 ` ISA Jim Paris
2001-12-18 22:01 ` ISA Maciej W. Rozycki
2001-12-18 22:24 ` ISA Jim Paris
2001-12-19 1:17 ` ISA Jun Sun
2001-12-19 1:50 ` ISA Maciej W. Rozycki
2001-12-19 2:05 ` ISA Bradley D. LaRonde
2001-12-19 2:05 ` ISA Bradley D. LaRonde
2001-12-19 2:09 ` ISA Jun Sun
2001-12-19 2:30 ` ISA Maciej W. Rozycki
2001-12-19 9:52 ` ISA Geert Uytterhoeven
2001-12-19 13:59 ` ISA Alan Cox
2001-12-19 13:59 ` ISA Alan Cox
2001-12-19 14:06 ` ISA Geert Uytterhoeven
2001-12-20 13:09 ` ISA Maciej W. Rozycki
2001-12-20 13:14 ` ISA Geert Uytterhoeven
2001-12-20 13:39 ` ISA Maciej W. Rozycki
2001-12-20 13:45 ` ISA Geert Uytterhoeven
2001-12-20 14:06 ` ISA Maciej W. Rozycki
2001-12-21 16:12 ` ISA Alan Cox
2001-12-21 16:12 ` ISA Alan Cox
2001-12-21 18:44 ` ISA Jim Paris
2002-01-01 19:22 ` Jun Sun [this message]
2002-01-01 19:34 ` ISA Bradley D. LaRonde
2002-01-02 1:03 ` ISA M. Warner Losh
2002-01-02 9:41 ` ISA Geert Uytterhoeven
2002-01-02 14:36 ` ISA Bradley D. LaRonde
2002-01-01 20:13 ` ISA Alan Cox
2002-01-01 20:13 ` ISA Alan Cox
2001-12-19 1:28 ` ISA Maciej W. Rozycki
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