Re: [Oops] Indy R4600 Oops(es) w/ 2.4.19-rc1

[Jan-Benedict Glaw <jbglaw@lug-owl.de>]

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On Mon, 2002-07-01 16:28:13 +0200, Maciej W. Rozycki <macro@ds2.pg.gda.pl>
wrote in message <Pine.GSO.3.96.1020701161009.7601E-100000@delta.ds2.pg.gda.pl>:
> On Mon, 1 Jul 2002, Jan-Benedict Glaw wrote:
> 
> > Okay, stupid idea. All these flush functions seem to be never called in
> > parallel or recursive, so if might be possible to have a global flags
> > variable and instead of always calling __save..() and __restore..(),
> > we bulid a pair of inline functions doing this. This wouldn't give
> > any penalty for !CONFIG_CPU_R4X00 and doesn't obscure the code so much
> > as all those #ifdef and #endif's would do... I'll test my suggestion
> > as fast as I reach my Indy again (is powered down at home...).
> 
>  Feel free to use the change privately.  Otherwise please code a real fix,
> i.e. a set of buggy-R4600-specific functions, as CONFIG_CPU_R4X00 means
> other processors as well, e.g. R4000 or R4400 which are fine here. 
> 
>  Actually blocking interrupts for over 0.01s as it used to be done is

Ah. That would explain the huge time drifts when the box is under
load...

> unacceptable, even for buggy R4600 processors.  A fix should use a more
> fine-grained interrupt masking. 

I'm just compiling with my proposed "fix". However, is it really a good
idea to duplicate so much code? Taking my 2nd idea (having inline
functions for saveing/restoring flags which are complete no-ops if
!CONFIG_CPU_R4X00), would it be much overhead for 4400 and 4000 to check
if we need to shuffle around flags and cut off interrupts?

I'm not really familiar w/ cache and interrupt handling/masking, and I
don't (yet) exactly know how to check for the buggy old R4600, but I
think I'll have to become an expert around that:-O

Any hints for online resources? I've had a look at idt.com (found it in
./asm-mips/war.h), but I cannot find the resources there:-(

MfG, JBG

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Jan-Benedict Glaw   .   jbglaw@lug-owl.de   .   +49-172-7608481
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