From: Ralf Baechle <ralf@oss.sgi.com>
To: Jun Sun <jsun@mvista.com>
Cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
Subject: Re: LTP testing (shmat01)
Date: Mon, 8 Jul 2002 19:45:39 +0200 [thread overview]
Message-ID: <20020708194539.C2758@dea.linux-mips.net> (raw)
In-Reply-To: <3D29CC6B.5090004@mvista.com>; from jsun@mvista.com on Mon, Jul 08, 2002 at 10:31:23AM -0700
On Mon, Jul 08, 2002 at 10:31:23AM -0700, Jun Sun wrote:
> I think this is also an effective way to avoid cache aliasing.
Correct. At the same time the choice of this value also tends to cause
bad use of L2 caches ...
> As long as your cache size is less than 256K, you don't get cache aliasing
> through shared memory.
Actually the "alias set" has to be less than 256kB. On existing MIPS
implementations it's at most 16kB; a sillyness of the R4000 / R4400 VCE
exceptions makes a value of 32kB mandatory for poerformance reasons.
> Perhaps other arches don't have cache aliasing? I know for sure i386
> does not have that effect.
The problem doesn't exist on physically indexed caches. Also on read-only
caches such as the instruction cache it usually can be ignored. So for
example the R2000, R3000, SB1 cores, RM7000, R4kc and R5kc in the right
configurations and the R10000 family don't suffer from aliases. Details
are messy :)
Ralf
next prev parent reply other threads:[~2002-07-08 17:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-07-04 15:26 LTP testing (shmat01) Carsten Langgaard
2002-07-04 17:34 ` Ralf Baechle
2002-07-04 18:18 ` Carsten Langgaard
2002-07-04 19:56 ` Ralf Baechle
2002-07-05 6:30 ` Carsten Langgaard
2002-07-05 14:37 ` Ralf Baechle
2002-07-08 17:31 ` Jun Sun
2002-07-08 17:45 ` Ralf Baechle [this message]
2002-07-08 18:13 ` Carsten Langgaard
2002-07-08 18:29 ` PATCH: Fix SHMLBA for mips (Re: LTP testing (shmat01)) H. J. Lu
2002-07-08 18:33 ` Ralf Baechle
2002-07-09 6:11 ` Carsten Langgaard
2002-07-09 6:34 ` Andreas Jaeger
2002-07-10 6:57 ` Ulrich Drepper
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