[PATCH] pciatuo setup P2P bridge properly

[Jun Sun <jsun@mvista.com>]

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This patches solves two problems:

1) if there are no devices behind P2P bridge, the xxx_base and xxx_limit
will be set to the same address, which willd decode 4Kb for MEM space
or 16 bytes for IO space at at that address.  This address will overlap
with the next pci device resources assigned right after the P2P bridge.

Simply adding 1 byte would leave proper cushion.

2) Sometimes P2P bridge controller may need resources.  (Don't ask me why)
We were ignoring this before.

Jun

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diff -Nru link/arch/mips/kernel/pci_auto.c.orig link/arch/mips/kernel/pci_auto.c
--- link/arch/mips/kernel/pci_auto.c.orig	Wed Apr  9 16:17:02 2003
+++ link/arch/mips/kernel/pci_auto.c	Wed Apr  9 16:28:09 2003
@@ -260,6 +260,14 @@
 {
 	u32 temp;
 
+	/* 
+	 * [jsun] we always bump up baselines a little, so that if there
+	 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
+	 * spaces.
+	 */
+	pciauto_lower_memspc += 1;
+	pciauto_lower_iospc += 1;
+
 	/* Configure bus number registers */
 	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 				PCI_SUBORDINATE_BUS, sub_bus);
@@ -419,6 +427,8 @@
 		if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 			DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 				current_bus, sub_bus + 1);
+			pciauto_setup_bars(hose, top_bus, current_bus, 
+					pci_devfn, PCI_BASE_ADDRESS_1);
 			pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 						     pci_devfn, sub_bus);
 			DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",