From: Ralf Baechle <ralf@linux-mips.org>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: Gilad Benjamini <yaelgilad@myrealbox.com>, linux-mips@linux-mips.org
Subject: Re: lwl-lwr
Date: Wed, 21 May 2003 01:34:49 +0100 [thread overview]
Message-ID: <20030521013449.A16378@linux-mips.org> (raw)
In-Reply-To: <025401c31f03$0e993370$10eca8c0@grendel>; from kevink@mips.com on Tue, May 20, 2003 at 09:07:26PM +0200
On Tue, May 20, 2003 at 09:07:26PM +0200, Kevin D. Kissell wrote:
> I don't remember the discussion in question, but it's a question
> which comes up from time to time, due to the existence of
> MIPS-like CPUs which lack the (patented) lwl/lwr mechanism
> for dealing with unaligned data. The Lexra cores, for example.
>
> There's really no such thing as "disabling" lwl/lwr. They are part
> of the base MIPS instruction set. If one wants to live without them,
> one can either rig a compiler to emit multi-instruction sequences instead
> of lwr/lwl to do the appropriate shifts and masks (which is slower on all
> targets), or you can rig the OS to emulate them, and hope that the processors
> lacking support will take clean reserved instruction traps, where the function
> can be emulated (which is "free" for code running on CPUs with lwl/lwr,
> but *really* slow for the guys doing emulation).
Technically you're right ... In reality lwl/lwr are covered by US patent
4,814,976 which would also cover a software implementation. So unless MIPS
grants a license for the purpose of emulation in the Linux kernel ...
Ralf
next prev parent reply other threads:[~2003-05-21 0:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-05-20 18:32 lwl-lwr Gilad Benjamini
2003-05-20 18:34 ` lwl-lwr Will Jhun
2003-05-20 19:07 ` lwl-lwr Kevin D. Kissell
2003-05-20 19:07 ` lwl-lwr Kevin D. Kissell
2003-05-21 0:34 ` Ralf Baechle [this message]
2003-05-21 9:56 ` lwl-lwr Maciej W. Rozycki
2003-05-21 13:40 ` lwl-lwr Kevin D. Kissell
2003-05-21 13:40 ` lwl-lwr Kevin D. Kissell
2003-05-21 12:49 ` lwl-lwr Alan Cox
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