From: Ralf Baechle <ralf@linux-mips.org>
To: ashish anand <ashish_ibm@rediffmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: Assertion duration of edge interrupts can decrease spurious interrupts ..?
Date: Tue, 18 Nov 2003 14:13:33 +0100 [thread overview]
Message-ID: <20031118131333.GC17503@linux-mips.org> (raw)
In-Reply-To: <20031118065741.27152.qmail@webmail29.rediffmail.com>
On Tue, Nov 18, 2003 at 06:57:41AM -0000, ashish anand wrote:
> 1.If i have a compulsion to use egde triggering peripheral on MIPS CP0,
> would it be useful if i can increase the assertion duration of edge
> interupts (this I can do) ..I mean to say probablity of loosing edge
> interrupts will decrasse.
That would help but still not be a safe mechanism. Not only the processor
may be missing the edge - Linux may also disable interrupts for quite a
long time. You'd have to use a hard realtime variant of Linux or you will
loose interrupts ...
> 2.does CP0 interrupt logic samples interrupts after each instruction or
> at some multiplication(..or division.?) of system clock.
This is a very processor specific detail. R4000 for example will sample
interrupts on pipe stage 3; something along that lines is probably done
in most in-order processors.
Ralf
prev parent reply other threads:[~2003-11-18 13:13 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-11-18 6:57 Assertion duration of edge interrupts can decrease spurious interrupts ..? ashish anand
2003-11-18 13:13 ` Ralf Baechle [this message]
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