From: Ralf Baechle <ralf@linux-mips.org>
To: "Kapoor, Pankaj" <pkapoor@telogy.com>
Cc: linux-mips@linux-mips.org
Subject: Re: MIPS Interrupts.
Date: Wed, 26 Nov 2003 00:09:46 +0100 [thread overview]
Message-ID: <20031125230946.GA12422@linux-mips.org> (raw)
In-Reply-To: <37A3C2F21006D611995100B0D0F9B73C02C8FCAE@tnint11.telogy.design.ti.com>
On Tue, Nov 25, 2003 at 04:52:20PM -0500, Kapoor, Pankaj wrote:
> Now there are 2 cases that can happen
>
> 1. Since we have not exited the ISR and the exception level has still not
> been restored there can be no more interrupts that are generated in the
> system. In such a case does that mean that the all bottom half handlers
> pending execution will run with interrupts disabled.
> NOTE: This does not seem likely because the local_irq_enable routine
> calls _sti which clears the exception level in the status register and
> also sets the IE bit.
>
> 2. If we have large number of tasklets or if the bottom half handlers take
> time to execute, then we could get another timer interrupt or other
> device interrupts causing context saves which would cause the stack to
> grow and CRASH the system.
Interrupts are disabled while the respective interrupt handler is running.
Ralf
next prev parent reply other threads:[~2003-11-25 23:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-11-25 21:52 MIPS Interrupts Kapoor, Pankaj
2003-11-25 23:06 ` Jun Sun
2003-11-25 23:09 ` Ralf Baechle [this message]
2003-11-26 0:31 ` Jun Sun
-- strict thread matches above, loose matches on Subject: below --
2003-11-26 0:24 Kapoor, Pankaj
2003-11-26 0:34 ` Jun Sun
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