From: Ralf Baechle <ralf@linux-mips.org>
To: karthikeyan natarajan <karthik_96cse@yahoo.com>
Cc: linux-mips@linux-mips.org
Subject: Re: How to configure the cache size in r4000
Date: Mon, 12 Jan 2004 17:57:24 +0100 [thread overview]
Message-ID: <20040112165724.GA16126@linux-mips.org> (raw)
In-Reply-To: <20040111124828.71884.qmail@web10103.mail.yahoo.com>
On Sun, Jan 11, 2004 at 12:48:28PM +0000, karthikeyan natarajan wrote:
> The cache size is modified by setting the IC/DC
> bits in the 'config' register. Seems they are set only
> by the hardware during the processor reset. And also,
> those bits are mentioned as read only bits..
> Could you please let me know how can we instruct
> the hardware to do so. Can we do this via s/w?.
You can't. These bits are hardwired to indicate the cache size which is
8k per primary cache on the R4000.
Ralf
prev parent reply other threads:[~2004-01-12 16:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-01-11 12:48 How to configure the cache size in r4000 karthikeyan natarajan
2004-01-12 12:51 ` Maciej W. Rozycki
2004-01-13 16:35 ` Ralf Baechle
2004-01-13 16:48 ` Maciej W. Rozycki
2004-01-15 9:48 ` Ralf Baechle
2004-01-15 13:31 ` Maciej W. Rozycki
2004-01-15 14:14 ` Current 2.4 CVS (2.4.24-pre2) doesn't boot on SGI Indy Dominik 'Rathann' Mierzejewski
2004-01-15 14:20 ` Dominik 'Rathann' Mierzejewski
2004-01-15 17:19 ` Martin Boehme
2004-01-15 23:17 ` Dominik 'Rathann' Mierzejewski
2004-01-16 1:03 ` Kumba
2004-01-16 1:26 ` Jun Sun
2004-01-16 11:50 ` Dominik 'Rathann' Mierzejewski
2004-01-20 13:06 ` Dominik 'Rathann' Mierzejewski
2004-01-20 16:28 ` Dominik 'Rathann' Mierzejewski
2004-01-23 16:14 ` Dominik 'Rathann' Mierzejewski
2004-01-26 16:31 ` [patch] pg-r4k.c bugs for R4600 rev.2.0 Maciej W. Rozycki
2004-01-26 17:00 ` Ralf Baechle
2004-01-28 1:37 ` Ralf Baechle
2004-01-28 16:22 ` Dominik 'Rathann' Mierzejewski
2004-01-12 16:57 ` Ralf Baechle [this message]
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